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git01.mediatek.com / filogic / uboot / 31f56b4f9ba176c660bc8cd66443515b197b9bbe / . / drivers / serial / serial_bcm283x_mu.c
blob: 7357bbfb26798ade1fb228140bcfd7f6e25bf052 [file] [log] [blame]
Stephen Warrenf84f9bf2016-03-18 21:41:38 -0600[diff] [blame]1/*
2 * (C) Copyright 2016 Stephen Warren <swarren@wwwdotorg.org>
3 *
4 * Derived from pl01x code:
5 *
6 * (C) Copyright 2000
7 * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
8 *
9 * (C) Copyright 2004
10 * ARM Ltd.
11 * Philippe Robin, <philippe.robin@arm.com>
12 *
13 * SPDX-License-Identifier: GPL-2.0+
14 */
15
16/* Simple U-Boot driver for the BCM283x mini UART */
17
18#include <common.h>
19#include <dm.h>
20#include <errno.h>
21#include <watchdog.h>
22#include <asm/io.h>
23#include <serial.h>
24#include <dm/platform_data/serial_bcm283x_mu.h>
25#include <linux/compiler.h>
26#include <fdtdec.h>
27
28struct bcm283x_mu_regs {
29 u32 io;
30 u32 iir;
31 u32 ier;
32 u32 lcr;
33 u32 mcr;
34 u32 lsr;
35 u32 msr;
36 u32 scratch;
37 u32 cntl;
38 u32 stat;
39 u32 baud;
40};
41
42#define BCM283X_MU_LCR_DATA_SIZE_8 3
43
44#define BCM283X_MU_LSR_TX_IDLE BIT(6)
45/* This actually means not full, but is named not empty in the docs */
46#define BCM283X_MU_LSR_TX_EMPTY BIT(5)
47#define BCM283X_MU_LSR_RX_READY BIT(0)
48
49struct bcm283x_mu_priv {
50 struct bcm283x_mu_regs *regs;
51};
52
53static int bcm283x_mu_serial_setbrg(struct udevice *dev, int baudrate)
54{
55 struct bcm283x_mu_serial_platdata *plat = dev_get_platdata(dev);
56 struct bcm283x_mu_priv *priv = dev_get_priv(dev);
57 struct bcm283x_mu_regs *regs = priv->regs;
58 u32 divider;
59
60 if (plat->skip_init)
61 return 0;
62
63 divider = plat->clock / (baudrate * 8);
64
65 writel(BCM283X_MU_LCR_DATA_SIZE_8, &regs->lcr);
66 writel(divider - 1, &regs->baud);
67
68 return 0;
69}
70
71static int bcm283x_mu_serial_probe(struct udevice *dev)
72{
73 struct bcm283x_mu_serial_platdata *plat = dev_get_platdata(dev);
74 struct bcm283x_mu_priv *priv = dev_get_priv(dev);
75
76 priv->regs = (struct bcm283x_mu_regs *)plat->base;
77
78 return 0;
79}
80
81static int bcm283x_mu_serial_getc(struct udevice *dev)
82{
83 struct bcm283x_mu_priv *priv = dev_get_priv(dev);
84 struct bcm283x_mu_regs *regs = priv->regs;
85 u32 data;
86
87 /* Wait until there is data in the FIFO */
88 if (!(readl(&regs->lsr) & BCM283X_MU_LSR_RX_READY))
89 return -EAGAIN;
90
91 data = readl(&regs->io);
92
93 return (int)data;
94}
95
96static int bcm283x_mu_serial_putc(struct udevice *dev, const char data)
97{
98 struct bcm283x_mu_priv *priv = dev_get_priv(dev);
99 struct bcm283x_mu_regs *regs = priv->regs;
100
101 /* Wait until there is space in the FIFO */
102 if (!(readl(&regs->lsr) & BCM283X_MU_LSR_TX_EMPTY))
103 return -EAGAIN;
104
105 /* Send the character */
106 writel(data, &regs->io);
107
108 return 0;
109}
110
111static int bcm283x_mu_serial_pending(struct udevice *dev, bool input)
112{
113 struct bcm283x_mu_priv *priv = dev_get_priv(dev);
114 struct bcm283x_mu_regs *regs = priv->regs;
115 unsigned int lsr = readl(&regs->lsr);
116
117 if (input) {
118 WATCHDOG_RESET();
Stephen Warren3a036982016-04-13 22:29:52 -0600[diff] [blame]119 return (lsr & BCM283X_MU_LSR_RX_READY) ? 1 : 0;
Stephen Warrenf84f9bf2016-03-18 21:41:38 -0600[diff] [blame]120 } else {
Stephen Warren3a036982016-04-13 22:29:52 -0600[diff] [blame]121 return (lsr & BCM283X_MU_LSR_TX_IDLE) ? 0 : 1;
Stephen Warrenf84f9bf2016-03-18 21:41:38 -0600[diff] [blame]122 }
123}
124
125static const struct dm_serial_ops bcm283x_mu_serial_ops = {
126 .putc = bcm283x_mu_serial_putc,
127 .pending = bcm283x_mu_serial_pending,
128 .getc = bcm283x_mu_serial_getc,
129 .setbrg = bcm283x_mu_serial_setbrg,
130};
131
132U_BOOT_DRIVER(serial_bcm283x_mu) = {
133 .name = "serial_bcm283x_mu",
134 .id = UCLASS_SERIAL,
135 .platdata_auto_alloc_size = sizeof(struct bcm283x_mu_serial_platdata),
136 .probe = bcm283x_mu_serial_probe,
137 .ops = &bcm283x_mu_serial_ops,
138 .flags = DM_FLAG_PRE_RELOC,
139 .priv_auto_alloc_size = sizeof(struct bcm283x_mu_priv),
140};