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Bin Meng81da5a82015-02-02 22:35:27 +08001/*
2 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
Bin Mengd79593b2015-02-04 16:26:13 +08008#include <mmc.h>
Bin Meng81da5a82015-02-02 22:35:27 +08009#include <asm/io.h>
Bin Meng330be032016-05-22 01:45:34 -070010#include <asm/ioapic.h>
Bin Meng4c2af8b2015-10-12 01:30:42 -070011#include <asm/mrccache.h>
Bin Meng0244ef42015-09-14 00:07:41 -070012#include <asm/mtrr.h>
Bin Meng81da5a82015-02-02 22:35:27 +080013#include <asm/pci.h>
14#include <asm/post.h>
Bin Meng34469862015-02-04 16:26:09 +080015#include <asm/arch/device.h>
16#include <asm/arch/msg_port.h>
17#include <asm/arch/quark.h>
18
Bin Meng0244ef42015-09-14 00:07:41 -070019static void quark_setup_mtrr(void)
20{
21 u32 base, mask;
22 int i;
23
24 disable_caches();
25
26 /* mark the VGA RAM area as uncacheable */
27 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_A0000,
28 MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE));
29 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_B0000,
30 MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE));
31
32 /* mark other fixed range areas as cacheable */
33 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_64K_00000,
34 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
35 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_64K_40000,
36 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
37 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_80000,
38 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
39 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_90000,
40 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
41 for (i = MTRR_FIX_4K_C0000; i <= MTRR_FIX_4K_FC000; i++)
42 msg_port_write(MSG_PORT_HOST_BRIDGE, i,
43 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
44
45 /* variable range MTRR#0: ROM area */
46 mask = ~(CONFIG_SYS_MONITOR_LEN - 1);
47 base = CONFIG_SYS_TEXT_BASE & mask;
48 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYBASE(MTRR_VAR_ROM),
49 base | MTRR_TYPE_WRBACK);
50 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYMASK(MTRR_VAR_ROM),
51 mask | MTRR_PHYS_MASK_VALID);
52
53 /* variable range MTRR#1: eSRAM area */
54 mask = ~(ESRAM_SIZE - 1);
55 base = CONFIG_ESRAM_BASE & mask;
56 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYBASE(MTRR_VAR_ESRAM),
57 base | MTRR_TYPE_WRBACK);
58 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYMASK(MTRR_VAR_ESRAM),
59 mask | MTRR_PHYS_MASK_VALID);
60
61 /* enable both variable and fixed range MTRRs */
62 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_DEF_TYPE,
63 MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN);
64
65 enable_caches();
66}
67
Bin Meng34469862015-02-04 16:26:09 +080068static void quark_setup_bars(void)
69{
70 /* GPIO - D31:F0:R44h */
Bin Meng9cdcfd72015-09-03 05:37:24 -070071 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_GBA,
72 CONFIG_GPIO_BASE | IO_BAR_EN);
Bin Meng34469862015-02-04 16:26:09 +080073
74 /* ACPI PM1 Block - D31:F0:R48h */
Bin Meng9cdcfd72015-09-03 05:37:24 -070075 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_PM1BLK,
76 CONFIG_ACPI_PM1_BASE | IO_BAR_EN);
Bin Meng34469862015-02-04 16:26:09 +080077
78 /* GPE0 - D31:F0:R4Ch */
Bin Meng9cdcfd72015-09-03 05:37:24 -070079 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_GPE0BLK,
80 CONFIG_ACPI_GPE0_BASE | IO_BAR_EN);
Bin Meng34469862015-02-04 16:26:09 +080081
82 /* WDT - D31:F0:R84h */
Bin Meng9cdcfd72015-09-03 05:37:24 -070083 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_WDTBA,
84 CONFIG_WDT_BASE | IO_BAR_EN);
Bin Meng34469862015-02-04 16:26:09 +080085
86 /* RCBA - D31:F0:RF0h */
Bin Meng9cdcfd72015-09-03 05:37:24 -070087 qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA,
88 CONFIG_RCBA_BASE | MEM_BAR_EN);
Bin Meng34469862015-02-04 16:26:09 +080089
90 /* ACPI P Block - Msg Port 04:R70h */
91 msg_port_write(MSG_PORT_RMU, PBLK_BA,
92 CONFIG_ACPI_PBLK_BASE | IO_BAR_EN);
93
94 /* SPI DMA - Msg Port 04:R7Ah */
95 msg_port_write(MSG_PORT_RMU, SPI_DMA_BA,
96 CONFIG_SPI_DMA_BASE | IO_BAR_EN);
97
98 /* PCIe ECAM */
99 msg_port_write(MSG_PORT_MEM_ARBITER, AEC_CTRL,
100 CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN);
101 msg_port_write(MSG_PORT_HOST_BRIDGE, HEC_REG,
102 CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN);
103}
Bin Meng81da5a82015-02-02 22:35:27 +0800104
Bin Meng4756cac2015-09-03 05:37:25 -0700105static void quark_pcie_early_init(void)
106{
Bin Meng4756cac2015-09-03 05:37:25 -0700107 /*
108 * Step1: Assert PCIe signal PERST#
109 *
110 * The CPU interface to the PERST# signal is platform dependent.
111 * Call the board-specific codes to perform this task.
112 */
113 board_assert_perst();
114
115 /* Step2: PHY common lane reset */
Bin Mengd8630262015-09-09 23:20:25 -0700116 msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG, PCIE_PHY_LANE_RST);
Bin Meng4756cac2015-09-03 05:37:25 -0700117 /* wait 1 ms for PHY common lane reset */
118 mdelay(1);
119
120 /* Step3: PHY sideband interface reset and controller main reset */
Bin Mengd8630262015-09-09 23:20:25 -0700121 msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG,
122 PCIE_PHY_SB_RST | PCIE_CTLR_MAIN_RST);
Bin Meng4756cac2015-09-03 05:37:25 -0700123 /* wait 80ms for PLL to lock */
124 mdelay(80);
125
126 /* Step4: Controller sideband interface reset */
Bin Mengd8630262015-09-09 23:20:25 -0700127 msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG, PCIE_CTLR_SB_RST);
Bin Meng4756cac2015-09-03 05:37:25 -0700128 /* wait 20ms for controller sideband interface reset */
129 mdelay(20);
130
131 /* Step5: De-assert PERST# */
132 board_deassert_perst();
133
134 /* Step6: Controller primary interface reset */
Bin Mengd8630262015-09-09 23:20:25 -0700135 msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG, PCIE_CTLR_PRI_RST);
Bin Meng4756cac2015-09-03 05:37:25 -0700136
137 /* Mixer Load Lane 0 */
Bin Mengd8630262015-09-09 23:20:25 -0700138 msg_port_io_clrbits(MSG_PORT_PCIE_AFE, PCIE_RXPICTRL0_L0,
139 (1 << 6) | (1 << 7));
Bin Meng4756cac2015-09-03 05:37:25 -0700140
141 /* Mixer Load Lane 1 */
Bin Mengd8630262015-09-09 23:20:25 -0700142 msg_port_io_clrbits(MSG_PORT_PCIE_AFE, PCIE_RXPICTRL0_L1,
143 (1 << 6) | (1 << 7));
Bin Meng4756cac2015-09-03 05:37:25 -0700144}
145
Bin Mengf3763722015-09-03 05:37:27 -0700146static void quark_usb_early_init(void)
147{
Bin Mengf3763722015-09-03 05:37:27 -0700148 /* The sequence below comes from Quark firmware writer guide */
149
Bin Mengd8630262015-09-09 23:20:25 -0700150 msg_port_alt_clrsetbits(MSG_PORT_USB_AFE, USB2_GLOBAL_PORT,
151 1 << 1, (1 << 6) | (1 << 7));
Bin Mengf3763722015-09-03 05:37:27 -0700152
Bin Mengd8630262015-09-09 23:20:25 -0700153 msg_port_alt_clrsetbits(MSG_PORT_USB_AFE, USB2_COMPBG,
154 (1 << 8) | (1 << 9), (1 << 7) | (1 << 10));
Bin Mengf3763722015-09-03 05:37:27 -0700155
Bin Mengd8630262015-09-09 23:20:25 -0700156 msg_port_alt_setbits(MSG_PORT_USB_AFE, USB2_PLL2, 1 << 29);
Bin Mengf3763722015-09-03 05:37:27 -0700157
Bin Mengd8630262015-09-09 23:20:25 -0700158 msg_port_alt_setbits(MSG_PORT_USB_AFE, USB2_PLL1, 1 << 1);
Bin Mengf3763722015-09-03 05:37:27 -0700159
Bin Mengd8630262015-09-09 23:20:25 -0700160 msg_port_alt_clrsetbits(MSG_PORT_USB_AFE, USB2_PLL1,
161 (1 << 3) | (1 << 4) | (1 << 5), 1 << 6);
Bin Mengf3763722015-09-03 05:37:27 -0700162
Bin Mengd8630262015-09-09 23:20:25 -0700163 msg_port_alt_clrbits(MSG_PORT_USB_AFE, USB2_PLL2, 1 << 29);
Bin Mengf3763722015-09-03 05:37:27 -0700164
Bin Mengd8630262015-09-09 23:20:25 -0700165 msg_port_alt_setbits(MSG_PORT_USB_AFE, USB2_PLL2, 1 << 24);
Bin Mengf3763722015-09-03 05:37:27 -0700166}
167
Bin Meng8f578db2015-09-09 23:20:27 -0700168static void quark_thermal_early_init(void)
169{
170 /* The sequence below comes from Quark firmware writer guide */
171
172 /* thermal sensor mode config */
173 msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG1,
174 (1 << 3) | (1 << 4) | (1 << 5), 1 << 5);
175 msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG1,
176 (1 << 8) | (1 << 9) | (1 << 10) | (1 << 11) |
177 (1 << 12), 1 << 9);
178 msg_port_alt_setbits(MSG_PORT_SOC_UNIT, TS_CFG1, 1 << 14);
179 msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG1, 1 << 17);
180 msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG1, 1 << 18);
181 msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG2, 0xffff, 0x011f);
182 msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG3, 0xff, 0x17);
183 msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG3,
184 (1 << 8) | (1 << 9), 1 << 8);
185 msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG3, 0xff000000);
186 msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG4,
187 0x7ff800, 0xc8 << 11);
188
189 /* thermal monitor catastrophic trip set point (105 celsius) */
190 msg_port_clrsetbits(MSG_PORT_RMU, TS_TRIP, 0xff, 155);
191
192 /* thermal monitor catastrophic trip clear point (0 celsius) */
193 msg_port_clrsetbits(MSG_PORT_RMU, TS_TRIP, 0xff0000, 50 << 16);
194
195 /* take thermal sensor out of reset */
196 msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG4, 1 << 0);
197
198 /* enable thermal monitor */
199 msg_port_setbits(MSG_PORT_RMU, TS_MODE, 1 << 15);
200
201 /* lock all thermal configuration */
202 msg_port_setbits(MSG_PORT_RMU, RMU_CTRL, (1 << 5) | (1 << 6));
203}
204
Bin Meng6db14482015-04-27 14:16:02 +0800205static void quark_enable_legacy_seg(void)
206{
Bin Mengd8630262015-09-09 23:20:25 -0700207 msg_port_setbits(MSG_PORT_HOST_BRIDGE, HMISC2,
208 HMISC2_SEGE | HMISC2_SEGF | HMISC2_SEGAB);
Bin Meng6db14482015-04-27 14:16:02 +0800209}
210
Bin Meng81da5a82015-02-02 22:35:27 +0800211int arch_cpu_init(void)
212{
Bin Meng81da5a82015-02-02 22:35:27 +0800213 int ret;
214
215 post_code(POST_CPU_INIT);
Bin Meng81da5a82015-02-02 22:35:27 +0800216
217 ret = x86_cpu_init_f();
218 if (ret)
219 return ret;
220
Bin Meng34469862015-02-04 16:26:09 +0800221 /*
Bin Meng0244ef42015-09-14 00:07:41 -0700222 * Quark SoC does not support MSR MTRRs. Fixed and variable range MTRRs
223 * are accessed indirectly via the message port and not the traditional
224 * MSR mechanism. Only UC, WT and WB cache types are supported.
225 */
226 quark_setup_mtrr();
227
228 /*
Bin Meng34469862015-02-04 16:26:09 +0800229 * Quark SoC has some non-standard BARs (excluding PCI standard BARs)
230 * which need be initialized with suggested values
231 */
232 quark_setup_bars();
233
Bin Mengf3763722015-09-03 05:37:27 -0700234 /* Initialize USB2 PHY */
235 quark_usb_early_init();
236
Bin Meng8f578db2015-09-09 23:20:27 -0700237 /* Initialize thermal sensor */
238 quark_thermal_early_init();
239
Bin Meng6db14482015-04-27 14:16:02 +0800240 /* Turn on legacy segments (A/B/E/F) decode to system RAM */
241 quark_enable_legacy_seg();
242
Bin Meng81da5a82015-02-02 22:35:27 +0800243 return 0;
244}
245
Bin Meng294191c2016-01-18 07:29:32 -0800246int arch_cpu_init_dm(void)
247{
248 /*
249 * Initialize PCIe controller
250 *
251 * Quark SoC holds the PCIe controller in reset following a power on.
252 * U-Boot needs to release the PCIe controller from reset. The PCIe
253 * controller (D23:F0/F1) will not be visible in PCI configuration
254 * space and any access to its PCI configuration registers will cause
255 * system hang while it is held in reset.
256 */
257 quark_pcie_early_init();
258
259 return 0;
260}
261
Simon Glassee7c36f2017-03-28 10:27:30 -0600262int checkcpu(void)
263{
264 return 0;
265}
266
Bin Meng81da5a82015-02-02 22:35:27 +0800267int print_cpuinfo(void)
268{
269 post_code(POST_CPU_INFO);
270 return default_print_cpuinfo();
271}
272
273void reset_cpu(ulong addr)
274{
275 /* cold reset */
Simon Glassd0963d42015-04-28 20:11:31 -0600276 x86_full_reset();
Bin Meng81da5a82015-02-02 22:35:27 +0800277}
Bin Mengd79593b2015-02-04 16:26:13 +0800278
Bin Meng4e19d7c2015-09-11 03:24:37 -0700279static void quark_pcie_init(void)
280{
281 u32 val;
282
283 /* PCIe upstream non-posted & posted request size */
284 qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_CCFG,
285 CCFG_UPRS | CCFG_UNRS);
286 qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_CCFG,
287 CCFG_UPRS | CCFG_UNRS);
288
289 /* PCIe packet fast transmit mode (IPF) */
290 qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_MPC2, MPC2_IPF);
291 qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_MPC2, MPC2_IPF);
292
293 /* PCIe message bus idle counter (SBIC) */
294 qrk_pci_read_config_dword(QUARK_PCIE0, PCIE_RP_MBC, &val);
295 val |= MBC_SBIC;
296 qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_MBC, val);
297 qrk_pci_read_config_dword(QUARK_PCIE1, PCIE_RP_MBC, &val);
298 val |= MBC_SBIC;
299 qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_MBC, val);
300}
301
302static void quark_usb_init(void)
303{
304 u32 bar;
305
306 /* Change USB EHCI packet buffer OUT/IN threshold */
307 qrk_pci_read_config_dword(QUARK_USB_EHCI, PCI_BASE_ADDRESS_0, &bar);
308 writel((0x7f << 16) | 0x7f, bar + EHCI_INSNREG01);
309
310 /* Disable USB device interrupts */
311 qrk_pci_read_config_dword(QUARK_USB_DEVICE, PCI_BASE_ADDRESS_0, &bar);
312 writel(0x7f, bar + USBD_INT_MASK);
313 writel((0xf << 16) | 0xf, bar + USBD_EP_INT_MASK);
314 writel((0xf << 16) | 0xf, bar + USBD_EP_INT_STS);
315}
316
317int arch_early_init_r(void)
318{
319 quark_pcie_init();
320
321 quark_usb_init();
322
323 return 0;
324}
325
Bin Mengef9e9f92015-05-25 22:35:06 +0800326int arch_misc_init(void)
327{
Bin Meng4c2af8b2015-10-12 01:30:42 -0700328#ifdef CONFIG_ENABLE_MRC_CACHE
329 /*
330 * We intend not to check any return value here, as even MRC cache
331 * is not saved successfully, it is not a severe error that will
332 * prevent system from continuing to boot.
333 */
334 mrccache_save();
335#endif
336
Bin Meng330be032016-05-22 01:45:34 -0700337 /* Assign a unique I/O APIC ID */
338 io_apic_set_id(1);
339
Simon Glass754f55e2016-01-19 21:32:26 -0700340 return 0;
Bin Mengef9e9f92015-05-25 22:35:06 +0800341}
Bin Meng4e19d7c2015-09-11 03:24:37 -0700342
343void board_final_cleanup(void)
344{
345 struct quark_rcba *rcba;
346 u32 base, val;
347
348 qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, &base);
349 base &= ~MEM_BAR_EN;
350 rcba = (struct quark_rcba *)base;
351
352 /* Initialize 'Component ID' to zero */
353 val = readl(&rcba->esd);
354 val &= ~0xff0000;
355 writel(val, &rcba->esd);
356
Bin Meng619c90a2015-09-09 23:20:26 -0700357 /* Lock HMBOUND for security */
358 msg_port_setbits(MSG_PORT_HOST_BRIDGE, HM_BOUND, HM_BOUND_LOCK);
359
Bin Meng4e19d7c2015-09-11 03:24:37 -0700360 return;
361}