Bin Meng | 96c05fc | 2015-02-02 22:35:24 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 5 | */ |
| 6 | |
| 7 | #include <common.h> |
Bin Meng | 96c05fc | 2015-02-02 22:35:24 +0800 | [diff] [blame] | 8 | #include <asm/arch/device.h> |
| 9 | #include <asm/arch/msg_port.h> |
Bin Meng | 7ba52a0 | 2015-09-03 05:37:23 -0700 | [diff] [blame] | 10 | #include <asm/arch/quark.h> |
Bin Meng | 96c05fc | 2015-02-02 22:35:24 +0800 | [diff] [blame] | 11 | |
| 12 | void msg_port_setup(int op, int port, int reg) |
| 13 | { |
Bin Meng | 7ba52a0 | 2015-09-03 05:37:23 -0700 | [diff] [blame] | 14 | qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_REG, |
| 15 | (((op) << 24) | ((port) << 16) | |
| 16 | (((reg) << 8) & 0xff00) | MSG_BYTE_ENABLE)); |
Bin Meng | 96c05fc | 2015-02-02 22:35:24 +0800 | [diff] [blame] | 17 | } |
| 18 | |
| 19 | u32 msg_port_read(u8 port, u32 reg) |
| 20 | { |
| 21 | u32 value; |
| 22 | |
Bin Meng | 7ba52a0 | 2015-09-03 05:37:23 -0700 | [diff] [blame] | 23 | qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG, |
| 24 | reg & 0xffffff00); |
Bin Meng | 96c05fc | 2015-02-02 22:35:24 +0800 | [diff] [blame] | 25 | msg_port_setup(MSG_OP_READ, port, reg); |
Bin Meng | 7ba52a0 | 2015-09-03 05:37:23 -0700 | [diff] [blame] | 26 | qrk_pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value); |
Bin Meng | 96c05fc | 2015-02-02 22:35:24 +0800 | [diff] [blame] | 27 | |
| 28 | return value; |
| 29 | } |
| 30 | |
| 31 | void msg_port_write(u8 port, u32 reg, u32 value) |
| 32 | { |
Bin Meng | 7ba52a0 | 2015-09-03 05:37:23 -0700 | [diff] [blame] | 33 | qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value); |
| 34 | qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG, |
| 35 | reg & 0xffffff00); |
Bin Meng | 96c05fc | 2015-02-02 22:35:24 +0800 | [diff] [blame] | 36 | msg_port_setup(MSG_OP_WRITE, port, reg); |
| 37 | } |
| 38 | |
| 39 | u32 msg_port_alt_read(u8 port, u32 reg) |
| 40 | { |
| 41 | u32 value; |
| 42 | |
Bin Meng | 7ba52a0 | 2015-09-03 05:37:23 -0700 | [diff] [blame] | 43 | qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG, |
| 44 | reg & 0xffffff00); |
Bin Meng | 96c05fc | 2015-02-02 22:35:24 +0800 | [diff] [blame] | 45 | msg_port_setup(MSG_OP_ALT_READ, port, reg); |
Bin Meng | 7ba52a0 | 2015-09-03 05:37:23 -0700 | [diff] [blame] | 46 | qrk_pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value); |
Bin Meng | 96c05fc | 2015-02-02 22:35:24 +0800 | [diff] [blame] | 47 | |
| 48 | return value; |
| 49 | } |
| 50 | |
| 51 | void msg_port_alt_write(u8 port, u32 reg, u32 value) |
| 52 | { |
Bin Meng | 7ba52a0 | 2015-09-03 05:37:23 -0700 | [diff] [blame] | 53 | qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value); |
| 54 | qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG, |
| 55 | reg & 0xffffff00); |
Bin Meng | 96c05fc | 2015-02-02 22:35:24 +0800 | [diff] [blame] | 56 | msg_port_setup(MSG_OP_ALT_WRITE, port, reg); |
| 57 | } |
| 58 | |
| 59 | u32 msg_port_io_read(u8 port, u32 reg) |
| 60 | { |
| 61 | u32 value; |
| 62 | |
Bin Meng | 7ba52a0 | 2015-09-03 05:37:23 -0700 | [diff] [blame] | 63 | qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG, |
| 64 | reg & 0xffffff00); |
Bin Meng | 96c05fc | 2015-02-02 22:35:24 +0800 | [diff] [blame] | 65 | msg_port_setup(MSG_OP_IO_READ, port, reg); |
Bin Meng | 7ba52a0 | 2015-09-03 05:37:23 -0700 | [diff] [blame] | 66 | qrk_pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value); |
Bin Meng | 96c05fc | 2015-02-02 22:35:24 +0800 | [diff] [blame] | 67 | |
| 68 | return value; |
| 69 | } |
| 70 | |
| 71 | void msg_port_io_write(u8 port, u32 reg, u32 value) |
| 72 | { |
Bin Meng | 7ba52a0 | 2015-09-03 05:37:23 -0700 | [diff] [blame] | 73 | qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value); |
| 74 | qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG, |
| 75 | reg & 0xffffff00); |
Bin Meng | 96c05fc | 2015-02-02 22:35:24 +0800 | [diff] [blame] | 76 | msg_port_setup(MSG_OP_IO_WRITE, port, reg); |
| 77 | } |