blob: cf828f21c0104f9acf8fbb6cdbe3c11c54c23bde [file] [log] [blame]
Bin Meng96c05fc2015-02-02 22:35:24 +08001/*
2 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
Bin Meng96c05fc2015-02-02 22:35:24 +08008#include <asm/arch/device.h>
9#include <asm/arch/msg_port.h>
Bin Meng7ba52a02015-09-03 05:37:23 -070010#include <asm/arch/quark.h>
Bin Meng96c05fc2015-02-02 22:35:24 +080011
12void msg_port_setup(int op, int port, int reg)
13{
Bin Meng7ba52a02015-09-03 05:37:23 -070014 qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_REG,
15 (((op) << 24) | ((port) << 16) |
16 (((reg) << 8) & 0xff00) | MSG_BYTE_ENABLE));
Bin Meng96c05fc2015-02-02 22:35:24 +080017}
18
19u32 msg_port_read(u8 port, u32 reg)
20{
21 u32 value;
22
Bin Meng7ba52a02015-09-03 05:37:23 -070023 qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
24 reg & 0xffffff00);
Bin Meng96c05fc2015-02-02 22:35:24 +080025 msg_port_setup(MSG_OP_READ, port, reg);
Bin Meng7ba52a02015-09-03 05:37:23 -070026 qrk_pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value);
Bin Meng96c05fc2015-02-02 22:35:24 +080027
28 return value;
29}
30
31void msg_port_write(u8 port, u32 reg, u32 value)
32{
Bin Meng7ba52a02015-09-03 05:37:23 -070033 qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value);
34 qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
35 reg & 0xffffff00);
Bin Meng96c05fc2015-02-02 22:35:24 +080036 msg_port_setup(MSG_OP_WRITE, port, reg);
37}
38
39u32 msg_port_alt_read(u8 port, u32 reg)
40{
41 u32 value;
42
Bin Meng7ba52a02015-09-03 05:37:23 -070043 qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
44 reg & 0xffffff00);
Bin Meng96c05fc2015-02-02 22:35:24 +080045 msg_port_setup(MSG_OP_ALT_READ, port, reg);
Bin Meng7ba52a02015-09-03 05:37:23 -070046 qrk_pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value);
Bin Meng96c05fc2015-02-02 22:35:24 +080047
48 return value;
49}
50
51void msg_port_alt_write(u8 port, u32 reg, u32 value)
52{
Bin Meng7ba52a02015-09-03 05:37:23 -070053 qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value);
54 qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
55 reg & 0xffffff00);
Bin Meng96c05fc2015-02-02 22:35:24 +080056 msg_port_setup(MSG_OP_ALT_WRITE, port, reg);
57}
58
59u32 msg_port_io_read(u8 port, u32 reg)
60{
61 u32 value;
62
Bin Meng7ba52a02015-09-03 05:37:23 -070063 qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
64 reg & 0xffffff00);
Bin Meng96c05fc2015-02-02 22:35:24 +080065 msg_port_setup(MSG_OP_IO_READ, port, reg);
Bin Meng7ba52a02015-09-03 05:37:23 -070066 qrk_pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value);
Bin Meng96c05fc2015-02-02 22:35:24 +080067
68 return value;
69}
70
71void msg_port_io_write(u8 port, u32 reg, u32 value)
72{
Bin Meng7ba52a02015-09-03 05:37:23 -070073 qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value);
74 qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
75 reg & 0xffffff00);
Bin Meng96c05fc2015-02-02 22:35:24 +080076 msg_port_setup(MSG_OP_IO_WRITE, port, reg);
77}