Peng Fan | 5c2218a | 2021-08-07 16:00:31 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Copyright 2021 NXP |
| 4 | */ |
| 5 | |
Peng Fan | 7253016 | 2021-08-07 16:00:33 +0800 | [diff] [blame] | 6 | #include <asm/io.h> |
| 7 | #include <asm/arch/clock.h> |
| 8 | #include <asm/arch/imx-regs.h> |
Peng Fan | 5c2218a | 2021-08-07 16:00:31 +0800 | [diff] [blame] | 9 | #include <asm/arch/sys_proto.h> |
Peng Fan | b15705a | 2021-08-07 16:00:35 +0800 | [diff] [blame] | 10 | #include <asm/armv8/mmu.h> |
Peng Fan | 7253016 | 2021-08-07 16:00:33 +0800 | [diff] [blame] | 11 | #include <asm/mach-imx/boot_mode.h> |
Ye Li | 88044c7 | 2021-08-07 16:01:01 +0800 | [diff] [blame] | 12 | #include <asm/global_data.h> |
Ye Li | 6dd4302 | 2021-08-07 16:00:48 +0800 | [diff] [blame] | 13 | #include <efi_loader.h> |
Simon Glass | fc55736 | 2022-03-04 08:43:05 -0700 | [diff] [blame] | 14 | #include <event.h> |
Ye Li | 6dd4302 | 2021-08-07 16:00:48 +0800 | [diff] [blame] | 15 | #include <spl.h> |
Peng Fan | 9c87e46 | 2021-08-07 16:00:59 +0800 | [diff] [blame] | 16 | #include <asm/arch/rdc.h> |
Ye Li | c408ed3 | 2022-07-26 16:40:49 +0800 | [diff] [blame] | 17 | #include <asm/mach-imx/s400_api.h> |
| 18 | #include <asm/mach-imx/mu_hal.h> |
Ye Li | 853cc9d | 2021-08-07 16:00:55 +0800 | [diff] [blame] | 19 | #include <cpu_func.h> |
| 20 | #include <asm/setup.h> |
Ye Li | 7bea5b0 | 2021-08-07 16:01:00 +0800 | [diff] [blame] | 21 | #include <dm.h> |
| 22 | #include <dm/device-internal.h> |
| 23 | #include <dm/lists.h> |
| 24 | #include <dm/uclass.h> |
| 25 | #include <dm/device.h> |
| 26 | #include <dm/uclass-internal.h> |
Ye Li | 7201262 | 2021-10-29 09:46:15 +0800 | [diff] [blame] | 27 | #include <fuse.h> |
Alice Guo | f2c4a39 | 2021-10-29 09:46:32 +0800 | [diff] [blame] | 28 | #include <thermal.h> |
Ye Li | 2e9f15c | 2022-04-06 14:30:08 +0800 | [diff] [blame] | 29 | #include <linux/iopoll.h> |
Ye Li | 48836ae | 2022-04-06 14:30:30 +0800 | [diff] [blame] | 30 | #include <env.h> |
| 31 | #include <env_internal.h> |
Peng Fan | 5c2218a | 2021-08-07 16:00:31 +0800 | [diff] [blame] | 32 | |
Peng Fan | b15705a | 2021-08-07 16:00:35 +0800 | [diff] [blame] | 33 | DECLARE_GLOBAL_DATA_PTR; |
| 34 | |
Ye Li | 7a71c61 | 2021-08-07 16:00:39 +0800 | [diff] [blame] | 35 | struct rom_api *g_rom_api = (struct rom_api *)0x1980; |
| 36 | |
Ye Li | 88044c7 | 2021-08-07 16:01:01 +0800 | [diff] [blame] | 37 | bool is_usb_boot(void) |
| 38 | { |
| 39 | return get_boot_device() == USB_BOOT; |
| 40 | } |
| 41 | |
| 42 | #ifdef CONFIG_ENV_IS_IN_MMC |
| 43 | __weak int board_mmc_get_env_dev(int devno) |
| 44 | { |
| 45 | return devno; |
| 46 | } |
| 47 | |
| 48 | int mmc_get_env_dev(void) |
| 49 | { |
Ye Li | 88044c7 | 2021-08-07 16:01:01 +0800 | [diff] [blame] | 50 | int ret; |
| 51 | u32 boot; |
| 52 | u16 boot_type; |
| 53 | u8 boot_instance; |
| 54 | |
Rasmus Villemoes | b06f5a4 | 2022-06-20 10:53:22 +0200 | [diff] [blame] | 55 | ret = rom_api_query_boot_infor(QUERY_BT_DEV, &boot); |
Ye Li | 88044c7 | 2021-08-07 16:01:01 +0800 | [diff] [blame] | 56 | |
| 57 | if (ret != ROM_API_OKAY) { |
| 58 | puts("ROMAPI: failure at query_boot_info\n"); |
| 59 | return CONFIG_SYS_MMC_ENV_DEV; |
| 60 | } |
| 61 | |
| 62 | boot_type = boot >> 16; |
| 63 | boot_instance = (boot >> 8) & 0xff; |
| 64 | |
| 65 | /* If not boot from sd/mmc, use default value */ |
| 66 | if (boot_type != BOOT_TYPE_SD && boot_type != BOOT_TYPE_MMC) |
| 67 | return env_get_ulong("mmcdev", 10, CONFIG_SYS_MMC_ENV_DEV); |
| 68 | |
| 69 | return board_mmc_get_env_dev(boot_instance); |
| 70 | } |
| 71 | #endif |
| 72 | |
Peng Fan | 5c2218a | 2021-08-07 16:00:31 +0800 | [diff] [blame] | 73 | u32 get_cpu_rev(void) |
| 74 | { |
| 75 | return (MXC_CPU_IMX8ULP << 12) | CHIP_REV_1_0; |
| 76 | } |
Peng Fan | 7253016 | 2021-08-07 16:00:33 +0800 | [diff] [blame] | 77 | |
| 78 | enum bt_mode get_boot_mode(void) |
| 79 | { |
| 80 | u32 bt0_cfg = 0; |
| 81 | |
Ye Li | 0e35805 | 2021-08-07 16:01:07 +0800 | [diff] [blame] | 82 | bt0_cfg = readl(SIM_SEC_BASE_ADDR + 0x24); |
Peng Fan | 7253016 | 2021-08-07 16:00:33 +0800 | [diff] [blame] | 83 | bt0_cfg &= (BT0CFG_LPBOOT_MASK | BT0CFG_DUALBOOT_MASK); |
| 84 | |
| 85 | if (!(bt0_cfg & BT0CFG_LPBOOT_MASK)) { |
| 86 | /* No low power boot */ |
| 87 | if (bt0_cfg & BT0CFG_DUALBOOT_MASK) |
| 88 | return DUAL_BOOT; |
| 89 | else |
| 90 | return SINGLE_BOOT; |
| 91 | } |
| 92 | |
| 93 | return LOW_POWER_BOOT; |
| 94 | } |
| 95 | |
Ye Li | 2e9f15c | 2022-04-06 14:30:08 +0800 | [diff] [blame] | 96 | bool m33_image_booted(void) |
| 97 | { |
| 98 | u32 gp6; |
| 99 | |
| 100 | /* DGO_GP6 */ |
| 101 | gp6 = readl(SIM_SEC_BASE_ADDR + 0x28); |
| 102 | if (gp6 & BIT(5)) |
| 103 | return true; |
| 104 | |
| 105 | return false; |
| 106 | } |
| 107 | |
| 108 | int m33_image_handshake(ulong timeout_ms) |
| 109 | { |
| 110 | u32 fsr; |
| 111 | int ret; |
| 112 | ulong timeout_us = timeout_ms * 1000; |
| 113 | |
Ye Li | 2e9f15c | 2022-04-06 14:30:08 +0800 | [diff] [blame] | 114 | /* Notify m33 that it's ready to do init srtm(enable mu receive interrupt and so on) */ |
| 115 | setbits_le32(MU0_B_BASE_ADDR + 0x100, BIT(0)); /* set FCR F0 flag of MU0_MUB */ |
| 116 | |
| 117 | /* |
| 118 | * Wait m33 to set FCR F0 flag of MU0_MUA |
| 119 | * Clear FCR F0 flag of MU0_MUB after m33 has set FCR F0 flag of MU0_MUA |
| 120 | */ |
| 121 | ret = readl_poll_sleep_timeout(MU0_B_BASE_ADDR + 0x104, fsr, fsr & BIT(0), 10, timeout_us); |
| 122 | if (!ret) |
| 123 | clrbits_le32(MU0_B_BASE_ADDR + 0x100, BIT(0)); |
| 124 | |
| 125 | return ret; |
| 126 | } |
| 127 | |
Peng Fan | af4f3b3 | 2021-08-07 16:00:34 +0800 | [diff] [blame] | 128 | #define CMC_SRS_TAMPER BIT(31) |
| 129 | #define CMC_SRS_SECURITY BIT(30) |
| 130 | #define CMC_SRS_TZWDG BIT(29) |
| 131 | #define CMC_SRS_JTAG_RST BIT(28) |
| 132 | #define CMC_SRS_CORE1 BIT(16) |
| 133 | #define CMC_SRS_LOCKUP BIT(15) |
| 134 | #define CMC_SRS_SW BIT(14) |
| 135 | #define CMC_SRS_WDG BIT(13) |
| 136 | #define CMC_SRS_PIN_RESET BIT(8) |
| 137 | #define CMC_SRS_WARM BIT(4) |
| 138 | #define CMC_SRS_HVD BIT(3) |
| 139 | #define CMC_SRS_LVD BIT(2) |
| 140 | #define CMC_SRS_POR BIT(1) |
| 141 | #define CMC_SRS_WUP BIT(0) |
| 142 | |
Peng Fan | af4f3b3 | 2021-08-07 16:00:34 +0800 | [diff] [blame] | 143 | static char *get_reset_cause(char *ret) |
| 144 | { |
| 145 | u32 cause1, cause = 0, srs = 0; |
Peng Fan | b15705a | 2021-08-07 16:00:35 +0800 | [diff] [blame] | 146 | void __iomem *reg_ssrs = (void __iomem *)(CMC1_BASE_ADDR + 0x88); |
| 147 | void __iomem *reg_srs = (void __iomem *)(CMC1_BASE_ADDR + 0x80); |
Peng Fan | af4f3b3 | 2021-08-07 16:00:34 +0800 | [diff] [blame] | 148 | |
| 149 | if (!ret) |
| 150 | return "null"; |
| 151 | |
| 152 | srs = readl(reg_srs); |
| 153 | cause1 = readl(reg_ssrs); |
| 154 | |
Peng Fan | 0d720e2 | 2021-08-07 16:01:06 +0800 | [diff] [blame] | 155 | cause = srs & (CMC_SRS_POR | CMC_SRS_WUP | CMC_SRS_WARM); |
Peng Fan | af4f3b3 | 2021-08-07 16:00:34 +0800 | [diff] [blame] | 156 | |
| 157 | switch (cause) { |
| 158 | case CMC_SRS_POR: |
| 159 | sprintf(ret, "%s", "POR"); |
| 160 | break; |
| 161 | case CMC_SRS_WUP: |
| 162 | sprintf(ret, "%s", "WUP"); |
| 163 | break; |
| 164 | case CMC_SRS_WARM: |
Peng Fan | 0d720e2 | 2021-08-07 16:01:06 +0800 | [diff] [blame] | 165 | cause = srs & (CMC_SRS_WDG | CMC_SRS_SW | |
Peng Fan | af4f3b3 | 2021-08-07 16:00:34 +0800 | [diff] [blame] | 166 | CMC_SRS_JTAG_RST); |
| 167 | switch (cause) { |
| 168 | case CMC_SRS_WDG: |
| 169 | sprintf(ret, "%s", "WARM-WDG"); |
| 170 | break; |
| 171 | case CMC_SRS_SW: |
| 172 | sprintf(ret, "%s", "WARM-SW"); |
| 173 | break; |
| 174 | case CMC_SRS_JTAG_RST: |
| 175 | sprintf(ret, "%s", "WARM-JTAG"); |
| 176 | break; |
| 177 | default: |
| 178 | sprintf(ret, "%s", "WARM-UNKN"); |
| 179 | break; |
| 180 | } |
| 181 | break; |
| 182 | default: |
Peng Fan | 0d720e2 | 2021-08-07 16:01:06 +0800 | [diff] [blame] | 183 | sprintf(ret, "%s-%X", "UNKN", srs); |
Peng Fan | af4f3b3 | 2021-08-07 16:00:34 +0800 | [diff] [blame] | 184 | break; |
| 185 | } |
| 186 | |
| 187 | debug("[%X] SRS[%X] %X - ", cause1, srs, srs ^ cause1); |
| 188 | return ret; |
| 189 | } |
| 190 | |
Peng Fan | 7253016 | 2021-08-07 16:00:33 +0800 | [diff] [blame] | 191 | #if defined(CONFIG_DISPLAY_CPUINFO) |
| 192 | const char *get_imx_type(u32 imxtype) |
| 193 | { |
| 194 | return "8ULP"; |
| 195 | } |
| 196 | |
| 197 | int print_cpuinfo(void) |
| 198 | { |
| 199 | u32 cpurev; |
| 200 | char cause[18]; |
| 201 | |
| 202 | cpurev = get_cpu_rev(); |
| 203 | |
Ye Li | f012ceb | 2021-10-29 09:46:24 +0800 | [diff] [blame] | 204 | printf("CPU: i.MX%s rev%d.%d at %d MHz\n", |
Peng Fan | 7253016 | 2021-08-07 16:00:33 +0800 | [diff] [blame] | 205 | get_imx_type((cpurev & 0xFF000) >> 12), |
| 206 | (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0, |
| 207 | mxc_get_clock(MXC_ARM_CLK) / 1000000); |
| 208 | |
Alice Guo | f2c4a39 | 2021-10-29 09:46:32 +0800 | [diff] [blame] | 209 | #if defined(CONFIG_IMX_PMC_TEMPERATURE) |
| 210 | struct udevice *udev; |
| 211 | int ret, temp; |
| 212 | |
| 213 | ret = uclass_get_device(UCLASS_THERMAL, 0, &udev); |
| 214 | if (!ret) { |
| 215 | ret = thermal_get_temp(udev, &temp); |
| 216 | if (!ret) |
| 217 | printf("CPU current temperature: %d\n", temp); |
| 218 | else |
| 219 | debug(" - failed to get CPU current temperature\n"); |
| 220 | } else { |
| 221 | debug(" - failed to get CPU current temperature\n"); |
| 222 | } |
| 223 | #endif |
| 224 | |
Peng Fan | af4f3b3 | 2021-08-07 16:00:34 +0800 | [diff] [blame] | 225 | printf("Reset cause: %s\n", get_reset_cause(cause)); |
| 226 | |
Peng Fan | 7253016 | 2021-08-07 16:00:33 +0800 | [diff] [blame] | 227 | printf("Boot mode: "); |
| 228 | switch (get_boot_mode()) { |
| 229 | case LOW_POWER_BOOT: |
| 230 | printf("Low power boot\n"); |
| 231 | break; |
| 232 | case DUAL_BOOT: |
| 233 | printf("Dual boot\n"); |
| 234 | break; |
| 235 | case SINGLE_BOOT: |
| 236 | default: |
| 237 | printf("Single boot\n"); |
| 238 | break; |
| 239 | } |
| 240 | |
| 241 | return 0; |
| 242 | } |
| 243 | #endif |
Peng Fan | b15705a | 2021-08-07 16:00:35 +0800 | [diff] [blame] | 244 | |
Peng Fan | c84bc10 | 2021-08-07 16:00:49 +0800 | [diff] [blame] | 245 | #define UNLOCK_WORD0 0xC520 /* 1st unlock word */ |
| 246 | #define UNLOCK_WORD1 0xD928 /* 2nd unlock word */ |
| 247 | #define REFRESH_WORD0 0xA602 /* 1st refresh word */ |
| 248 | #define REFRESH_WORD1 0xB480 /* 2nd refresh word */ |
| 249 | |
| 250 | static void disable_wdog(void __iomem *wdog_base) |
| 251 | { |
| 252 | u32 val_cs = readl(wdog_base + 0x00); |
| 253 | |
| 254 | if (!(val_cs & 0x80)) |
| 255 | return; |
| 256 | |
| 257 | dmb(); |
| 258 | __raw_writel(REFRESH_WORD0, (wdog_base + 0x04)); /* Refresh the CNT */ |
| 259 | __raw_writel(REFRESH_WORD1, (wdog_base + 0x04)); |
| 260 | dmb(); |
| 261 | |
| 262 | if (!(val_cs & 800)) { |
| 263 | dmb(); |
| 264 | __raw_writel(UNLOCK_WORD0, (wdog_base + 0x04)); |
| 265 | __raw_writel(UNLOCK_WORD1, (wdog_base + 0x04)); |
| 266 | dmb(); |
| 267 | |
| 268 | while (!(readl(wdog_base + 0x00) & 0x800)) |
| 269 | ; |
| 270 | } |
| 271 | writel(0x0, (wdog_base + 0x0C)); /* Set WIN to 0 */ |
| 272 | writel(0x400, (wdog_base + 0x08)); /* Set timeout to default 0x400 */ |
| 273 | writel(0x120, (wdog_base + 0x00)); /* Disable it and set update */ |
| 274 | |
| 275 | while (!(readl(wdog_base + 0x00) & 0x400)) |
| 276 | ; |
| 277 | } |
| 278 | |
Peng Fan | b15705a | 2021-08-07 16:00:35 +0800 | [diff] [blame] | 279 | void init_wdog(void) |
| 280 | { |
Peng Fan | c84bc10 | 2021-08-07 16:00:49 +0800 | [diff] [blame] | 281 | disable_wdog((void __iomem *)WDG3_RBASE); |
Peng Fan | b15705a | 2021-08-07 16:00:35 +0800 | [diff] [blame] | 282 | } |
| 283 | |
| 284 | static struct mm_region imx8ulp_arm64_mem_map[] = { |
| 285 | { |
| 286 | /* ROM */ |
| 287 | .virt = 0x0, |
| 288 | .phys = 0x0, |
| 289 | .size = 0x40000UL, |
| 290 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 291 | PTE_BLOCK_OUTER_SHARE |
| 292 | }, |
| 293 | { |
| 294 | /* FLEXSPI0 */ |
| 295 | .virt = 0x04000000, |
| 296 | .phys = 0x04000000, |
| 297 | .size = 0x08000000UL, |
| 298 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| 299 | PTE_BLOCK_NON_SHARE | |
| 300 | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
| 301 | }, |
| 302 | { |
| 303 | /* SSRAM (align with 2M) */ |
| 304 | .virt = 0x1FE00000UL, |
| 305 | .phys = 0x1FE00000UL, |
| 306 | .size = 0x400000UL, |
| 307 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 308 | PTE_BLOCK_OUTER_SHARE | |
| 309 | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
| 310 | }, { |
| 311 | /* SRAM1 (align with 2M) */ |
| 312 | .virt = 0x21000000UL, |
| 313 | .phys = 0x21000000UL, |
| 314 | .size = 0x200000UL, |
| 315 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 316 | PTE_BLOCK_OUTER_SHARE | |
| 317 | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
| 318 | }, { |
| 319 | /* SRAM0 (align with 2M) */ |
| 320 | .virt = 0x22000000UL, |
| 321 | .phys = 0x22000000UL, |
| 322 | .size = 0x200000UL, |
| 323 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 324 | PTE_BLOCK_OUTER_SHARE | |
| 325 | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
| 326 | }, { |
| 327 | /* Peripherals */ |
| 328 | .virt = 0x27000000UL, |
| 329 | .phys = 0x27000000UL, |
| 330 | .size = 0x3000000UL, |
| 331 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| 332 | PTE_BLOCK_NON_SHARE | |
| 333 | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
| 334 | }, { |
| 335 | /* Peripherals */ |
| 336 | .virt = 0x2D000000UL, |
| 337 | .phys = 0x2D000000UL, |
| 338 | .size = 0x1600000UL, |
| 339 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| 340 | PTE_BLOCK_NON_SHARE | |
| 341 | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
| 342 | }, { |
| 343 | /* FLEXSPI1-2 */ |
| 344 | .virt = 0x40000000UL, |
| 345 | .phys = 0x40000000UL, |
| 346 | .size = 0x40000000UL, |
| 347 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| 348 | PTE_BLOCK_NON_SHARE | |
| 349 | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
| 350 | }, { |
| 351 | /* DRAM1 */ |
| 352 | .virt = 0x80000000UL, |
| 353 | .phys = 0x80000000UL, |
| 354 | .size = PHYS_SDRAM_SIZE, |
| 355 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 356 | PTE_BLOCK_OUTER_SHARE |
| 357 | }, { |
| 358 | /* |
| 359 | * empty entrie to split table entry 5 |
| 360 | * if needed when TEEs are used |
| 361 | */ |
| 362 | 0, |
| 363 | }, { |
| 364 | /* List terminator */ |
| 365 | 0, |
| 366 | } |
| 367 | }; |
| 368 | |
| 369 | struct mm_region *mem_map = imx8ulp_arm64_mem_map; |
| 370 | |
Ji Luo | 2fd258c | 2022-04-06 14:30:28 +0800 | [diff] [blame] | 371 | static unsigned int imx8ulp_find_dram_entry_in_mem_map(void) |
| 372 | { |
| 373 | int i; |
| 374 | |
| 375 | for (i = 0; i < ARRAY_SIZE(imx8ulp_arm64_mem_map); i++) |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 376 | if (imx8ulp_arm64_mem_map[i].phys == CFG_SYS_SDRAM_BASE) |
Ji Luo | 2fd258c | 2022-04-06 14:30:28 +0800 | [diff] [blame] | 377 | return i; |
| 378 | |
| 379 | hang(); /* Entry not found, this must never happen. */ |
| 380 | } |
| 381 | |
Peng Fan | b15705a | 2021-08-07 16:00:35 +0800 | [diff] [blame] | 382 | /* simplify the page table size to enhance boot speed */ |
| 383 | #define MAX_PTE_ENTRIES 512 |
| 384 | #define MAX_MEM_MAP_REGIONS 16 |
| 385 | u64 get_page_table_size(void) |
| 386 | { |
| 387 | u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64); |
| 388 | u64 size = 0; |
| 389 | |
| 390 | /* |
| 391 | * For each memory region, the max table size: |
| 392 | * 2 level 3 tables + 2 level 2 tables + 1 level 1 table |
| 393 | */ |
| 394 | size = (2 + 2 + 1) * one_pt * MAX_MEM_MAP_REGIONS + one_pt; |
| 395 | |
| 396 | /* |
| 397 | * We need to duplicate our page table once to have an emergency pt to |
| 398 | * resort to when splitting page tables later on |
| 399 | */ |
| 400 | size *= 2; |
| 401 | |
| 402 | /* |
| 403 | * We may need to split page tables later on if dcache settings change, |
| 404 | * so reserve up to 4 (random pick) page tables for that. |
| 405 | */ |
| 406 | size += one_pt * 4; |
| 407 | |
| 408 | return size; |
| 409 | } |
| 410 | |
| 411 | void enable_caches(void) |
| 412 | { |
Ji Luo | 2fd258c | 2022-04-06 14:30:28 +0800 | [diff] [blame] | 413 | /* If OPTEE runs, remove OPTEE memory from MMU table to avoid speculative prefetch */ |
| 414 | if (rom_pointer[1]) { |
| 415 | /* |
| 416 | * TEE are loaded, So the ddr bank structures |
| 417 | * have been modified update mmu table accordingly |
| 418 | */ |
| 419 | int i = 0; |
| 420 | int entry = imx8ulp_find_dram_entry_in_mem_map(); |
| 421 | u64 attrs = imx8ulp_arm64_mem_map[entry].attrs; |
| 422 | |
| 423 | while (i < CONFIG_NR_DRAM_BANKS && |
| 424 | entry < ARRAY_SIZE(imx8ulp_arm64_mem_map)) { |
| 425 | if (gd->bd->bi_dram[i].start == 0) |
| 426 | break; |
| 427 | imx8ulp_arm64_mem_map[entry].phys = gd->bd->bi_dram[i].start; |
| 428 | imx8ulp_arm64_mem_map[entry].virt = gd->bd->bi_dram[i].start; |
| 429 | imx8ulp_arm64_mem_map[entry].size = gd->bd->bi_dram[i].size; |
| 430 | imx8ulp_arm64_mem_map[entry].attrs = attrs; |
| 431 | debug("Added memory mapping (%d): %llx %llx\n", entry, |
| 432 | imx8ulp_arm64_mem_map[entry].phys, imx8ulp_arm64_mem_map[entry].size); |
| 433 | i++; entry++; |
| 434 | } |
| 435 | } |
Peng Fan | b15705a | 2021-08-07 16:00:35 +0800 | [diff] [blame] | 436 | |
| 437 | icache_enable(); |
| 438 | dcache_enable(); |
| 439 | } |
| 440 | |
Ji Luo | 2fd258c | 2022-04-06 14:30:28 +0800 | [diff] [blame] | 441 | __weak int board_phys_sdram_size(phys_size_t *size) |
| 442 | { |
| 443 | if (!size) |
| 444 | return -EINVAL; |
| 445 | |
| 446 | *size = PHYS_SDRAM_SIZE; |
| 447 | return 0; |
| 448 | } |
| 449 | |
Peng Fan | b15705a | 2021-08-07 16:00:35 +0800 | [diff] [blame] | 450 | int dram_init(void) |
| 451 | { |
Ji Luo | 2fd258c | 2022-04-06 14:30:28 +0800 | [diff] [blame] | 452 | unsigned int entry = imx8ulp_find_dram_entry_in_mem_map(); |
| 453 | phys_size_t sdram_size; |
| 454 | int ret; |
| 455 | |
| 456 | ret = board_phys_sdram_size(&sdram_size); |
| 457 | if (ret) |
| 458 | return ret; |
| 459 | |
| 460 | /* rom_pointer[1] contains the size of TEE occupies */ |
| 461 | if (rom_pointer[1]) |
| 462 | gd->ram_size = sdram_size - rom_pointer[1]; |
| 463 | else |
| 464 | gd->ram_size = sdram_size; |
| 465 | |
| 466 | /* also update the SDRAM size in the mem_map used externally */ |
| 467 | imx8ulp_arm64_mem_map[entry].size = sdram_size; |
| 468 | return 0; |
| 469 | } |
| 470 | |
| 471 | int dram_init_banksize(void) |
| 472 | { |
| 473 | int bank = 0; |
| 474 | int ret; |
| 475 | phys_size_t sdram_size; |
| 476 | |
| 477 | ret = board_phys_sdram_size(&sdram_size); |
| 478 | if (ret) |
| 479 | return ret; |
| 480 | |
| 481 | gd->bd->bi_dram[bank].start = PHYS_SDRAM; |
| 482 | if (rom_pointer[1]) { |
| 483 | phys_addr_t optee_start = (phys_addr_t)rom_pointer[0]; |
| 484 | phys_size_t optee_size = (size_t)rom_pointer[1]; |
| 485 | |
| 486 | gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start; |
| 487 | if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_size)) { |
| 488 | if (++bank >= CONFIG_NR_DRAM_BANKS) { |
| 489 | puts("CONFIG_NR_DRAM_BANKS is not enough\n"); |
| 490 | return -1; |
| 491 | } |
| 492 | |
| 493 | gd->bd->bi_dram[bank].start = optee_start + optee_size; |
| 494 | gd->bd->bi_dram[bank].size = PHYS_SDRAM + |
| 495 | sdram_size - gd->bd->bi_dram[bank].start; |
| 496 | } |
| 497 | } else { |
| 498 | gd->bd->bi_dram[bank].size = sdram_size; |
| 499 | } |
Peng Fan | b15705a | 2021-08-07 16:00:35 +0800 | [diff] [blame] | 500 | |
| 501 | return 0; |
| 502 | } |
| 503 | |
Ji Luo | 2fd258c | 2022-04-06 14:30:28 +0800 | [diff] [blame] | 504 | phys_size_t get_effective_memsize(void) |
| 505 | { |
| 506 | /* return the first bank as effective memory */ |
| 507 | if (rom_pointer[1]) |
| 508 | return ((phys_addr_t)rom_pointer[0] - PHYS_SDRAM); |
| 509 | |
| 510 | return gd->ram_size; |
| 511 | } |
| 512 | |
Tom Rini | ae21e7f | 2021-08-30 09:16:29 -0400 | [diff] [blame] | 513 | #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG |
Peng Fan | b15705a | 2021-08-07 16:00:35 +0800 | [diff] [blame] | 514 | void get_board_serial(struct tag_serialnr *serialnr) |
| 515 | { |
Ye Li | 7bea5b0 | 2021-08-07 16:01:00 +0800 | [diff] [blame] | 516 | u32 uid[4]; |
| 517 | u32 res; |
| 518 | int ret; |
| 519 | |
| 520 | ret = ahab_read_common_fuse(1, uid, 4, &res); |
| 521 | if (ret) |
| 522 | printf("ahab read fuse failed %d, 0x%x\n", ret, res); |
| 523 | else |
| 524 | printf("UID 0x%x,0x%x,0x%x,0x%x\n", uid[0], uid[1], uid[2], uid[3]); |
| 525 | |
| 526 | serialnr->low = uid[0]; |
| 527 | serialnr->high = uid[3]; |
Peng Fan | b15705a | 2021-08-07 16:00:35 +0800 | [diff] [blame] | 528 | } |
| 529 | #endif |
| 530 | |
Ye Li | 6ee435eb | 2021-08-07 16:00:50 +0800 | [diff] [blame] | 531 | static void set_core0_reset_vector(u32 entry) |
Peng Fan | b15705a | 2021-08-07 16:00:35 +0800 | [diff] [blame] | 532 | { |
Ye Li | 6dd4302 | 2021-08-07 16:00:48 +0800 | [diff] [blame] | 533 | /* Update SIM1 DGO8 for reset vector base */ |
Ye Li | 6ee435eb | 2021-08-07 16:00:50 +0800 | [diff] [blame] | 534 | writel(entry, SIM1_BASE_ADDR + 0x5c); |
Ye Li | 6dd4302 | 2021-08-07 16:00:48 +0800 | [diff] [blame] | 535 | |
| 536 | /* set update bit */ |
| 537 | setbits_le32(SIM1_BASE_ADDR + 0x8, 0x1 << 24); |
| 538 | |
| 539 | /* polling the ack */ |
| 540 | while ((readl(SIM1_BASE_ADDR + 0x8) & (0x1 << 26)) == 0) |
| 541 | ; |
| 542 | |
| 543 | /* clear the update */ |
| 544 | clrbits_le32(SIM1_BASE_ADDR + 0x8, (0x1 << 24)); |
| 545 | |
| 546 | /* clear the ack by set 1 */ |
| 547 | setbits_le32(SIM1_BASE_ADDR + 0x8, (0x1 << 26)); |
Ye Li | 6ee435eb | 2021-08-07 16:00:50 +0800 | [diff] [blame] | 548 | } |
| 549 | |
Peng Fan | 9c87e46 | 2021-08-07 16:00:59 +0800 | [diff] [blame] | 550 | static int trdc_set_access(void) |
Peng Fan | b5c41b1 | 2021-08-07 16:00:58 +0800 | [diff] [blame] | 551 | { |
| 552 | /* |
Peng Fan | 9c87e46 | 2021-08-07 16:00:59 +0800 | [diff] [blame] | 553 | * TRDC mgr + 4 MBC + 2 MRC. |
| 554 | * S400 should already configure when release RDC |
| 555 | * A35 only map non-secure region for pbridge0 and 1, set sec_access to false |
Peng Fan | b5c41b1 | 2021-08-07 16:00:58 +0800 | [diff] [blame] | 556 | */ |
Peng Fan | 9c87e46 | 2021-08-07 16:00:59 +0800 | [diff] [blame] | 557 | trdc_mbc_set_access(2, 7, 0, 49, false); |
| 558 | trdc_mbc_set_access(2, 7, 0, 50, false); |
| 559 | trdc_mbc_set_access(2, 7, 0, 51, false); |
| 560 | trdc_mbc_set_access(2, 7, 0, 52, false); |
| 561 | trdc_mbc_set_access(2, 7, 0, 53, false); |
| 562 | trdc_mbc_set_access(2, 7, 0, 54, false); |
Peng Fan | b5c41b1 | 2021-08-07 16:00:58 +0800 | [diff] [blame] | 563 | |
Peng Fan | 9c87e46 | 2021-08-07 16:00:59 +0800 | [diff] [blame] | 564 | /* CGC0: PBridge0 slot 47 */ |
| 565 | trdc_mbc_set_access(2, 7, 0, 47, false); |
Peng Fan | b5c41b1 | 2021-08-07 16:00:58 +0800 | [diff] [blame] | 566 | |
Peng Fan | 9c87e46 | 2021-08-07 16:00:59 +0800 | [diff] [blame] | 567 | /* Iomuxc0: : PBridge1 slot 33 */ |
| 568 | trdc_mbc_set_access(2, 7, 1, 33, false); |
Peng Fan | b5c41b1 | 2021-08-07 16:00:58 +0800 | [diff] [blame] | 569 | |
Ye Li | d325d37 | 2021-10-29 09:46:20 +0800 | [diff] [blame] | 570 | /* flexspi0 */ |
| 571 | trdc_mrc_region_set_access(0, 7, 0x04000000, 0x0c000000, false); |
Ye Li | 27666ca | 2021-10-29 09:46:21 +0800 | [diff] [blame] | 572 | |
| 573 | /* tpm0: PBridge1 slot 21 */ |
| 574 | trdc_mbc_set_access(2, 7, 1, 21, false); |
| 575 | /* lpi2c0: PBridge1 slot 24 */ |
| 576 | trdc_mbc_set_access(2, 7, 1, 24, false); |
Peng Fan | b5c41b1 | 2021-08-07 16:00:58 +0800 | [diff] [blame] | 577 | return 0; |
| 578 | } |
| 579 | |
Ye Li | ec10a80 | 2022-04-06 14:30:17 +0800 | [diff] [blame] | 580 | void lpav_configure(bool lpav_to_m33) |
Ye Li | 43819eb | 2021-10-29 09:46:16 +0800 | [diff] [blame] | 581 | { |
Ye Li | ec10a80 | 2022-04-06 14:30:17 +0800 | [diff] [blame] | 582 | if (!lpav_to_m33) |
| 583 | setbits_le32(SIM_SEC_BASE_ADDR + 0x44, BIT(7)); /* LPAV to APD */ |
Ye Li | 43819eb | 2021-10-29 09:46:16 +0800 | [diff] [blame] | 584 | |
Peng Fan | fa609b4 | 2021-10-29 09:46:17 +0800 | [diff] [blame] | 585 | /* PXP/GPU 2D/3D/DCNANO/MIPI_DSI/EPDC/HIFI4 to APD */ |
| 586 | setbits_le32(SIM_SEC_BASE_ADDR + 0x4c, 0x7F); |
Ye Li | 43819eb | 2021-10-29 09:46:16 +0800 | [diff] [blame] | 587 | |
| 588 | /* LPAV slave/dma2 ch allocation and request allocation to APD */ |
| 589 | writel(0x1f, SIM_SEC_BASE_ADDR + 0x50); |
| 590 | writel(0xffffffff, SIM_SEC_BASE_ADDR + 0x54); |
| 591 | writel(0x003fffff, SIM_SEC_BASE_ADDR + 0x58); |
Ye Li | 715cfa0 | 2021-10-29 09:46:23 +0800 | [diff] [blame] | 592 | } |
Ye Li | a031155 | 2021-10-29 09:46:22 +0800 | [diff] [blame] | 593 | |
Ye Li | 133f8b8 | 2021-10-29 09:46:25 +0800 | [diff] [blame] | 594 | void load_lposc_fuse(void) |
| 595 | { |
| 596 | int ret; |
| 597 | u32 val = 0, val2 = 0, reg; |
| 598 | |
| 599 | ret = fuse_read(25, 0, &val); |
| 600 | if (ret) |
| 601 | return; /* failed */ |
| 602 | |
| 603 | ret = fuse_read(25, 1, &val2); |
| 604 | if (ret) |
| 605 | return; /* failed */ |
| 606 | |
| 607 | /* LPOSCCTRL */ |
| 608 | reg = readl(0x2802f304); |
| 609 | reg &= ~0xff; |
| 610 | reg |= (val & 0xff); |
| 611 | writel(reg, 0x2802f304); |
| 612 | } |
| 613 | |
Ye Li | 715cfa0 | 2021-10-29 09:46:23 +0800 | [diff] [blame] | 614 | void set_lpav_qos(void) |
| 615 | { |
Ye Li | a031155 | 2021-10-29 09:46:22 +0800 | [diff] [blame] | 616 | /* Set read QoS of dcnano on LPAV NIC */ |
| 617 | writel(0xf, 0x2e447100); |
Ye Li | 43819eb | 2021-10-29 09:46:16 +0800 | [diff] [blame] | 618 | } |
| 619 | |
Ye Li | 6ee435eb | 2021-08-07 16:00:50 +0800 | [diff] [blame] | 620 | int arch_cpu_init(void) |
| 621 | { |
| 622 | if (IS_ENABLED(CONFIG_SPL_BUILD)) { |
Ye Li | 7201262 | 2021-10-29 09:46:15 +0800 | [diff] [blame] | 623 | u32 val = 0; |
| 624 | int ret; |
| 625 | bool rdc_en = true; /* Default assume DBD_EN is set */ |
| 626 | |
Peng Fan | 21bda43 | 2022-04-06 14:30:27 +0800 | [diff] [blame] | 627 | /* Enable System Reset Interrupt using WDOG_AD */ |
| 628 | setbits_le32(CMC1_BASE_ADDR + 0x8C, BIT(13)); |
| 629 | /* Clear AD_PERIPH Power switch domain out of reset interrupt flag */ |
| 630 | setbits_le32(CMC1_BASE_ADDR + 0x70, BIT(4)); |
| 631 | |
| 632 | if (readl(CMC1_BASE_ADDR + 0x90) & BIT(13)) { |
| 633 | /* Clear System Reset Interrupt Flag Register of WDOG_AD */ |
| 634 | setbits_le32(CMC1_BASE_ADDR + 0x90, BIT(13)); |
| 635 | /* Reset WDOG to clear reset request */ |
| 636 | pcc_reset_peripheral(3, WDOG3_PCC3_SLOT, true); |
| 637 | pcc_reset_peripheral(3, WDOG3_PCC3_SLOT, false); |
| 638 | } |
| 639 | |
Ye Li | 853cc9d | 2021-08-07 16:00:55 +0800 | [diff] [blame] | 640 | /* Disable wdog */ |
| 641 | init_wdog(); |
| 642 | |
Ye Li | 7201262 | 2021-10-29 09:46:15 +0800 | [diff] [blame] | 643 | /* Read DBD_EN fuse */ |
| 644 | ret = fuse_read(8, 1, &val); |
| 645 | if (!ret) |
| 646 | rdc_en = !!(val & 0x4000); |
| 647 | |
Peng Fan | b5c41b1 | 2021-08-07 16:00:58 +0800 | [diff] [blame] | 648 | if (get_boot_mode() == SINGLE_BOOT) { |
Ye Li | 7201262 | 2021-10-29 09:46:15 +0800 | [diff] [blame] | 649 | if (rdc_en) |
| 650 | release_rdc(RDC_TRDC); |
| 651 | |
Peng Fan | b5c41b1 | 2021-08-07 16:00:58 +0800 | [diff] [blame] | 652 | trdc_set_access(); |
Ye Li | ec10a80 | 2022-04-06 14:30:17 +0800 | [diff] [blame] | 653 | lpav_configure(false); |
| 654 | } else { |
| 655 | lpav_configure(true); |
Peng Fan | b5c41b1 | 2021-08-07 16:00:58 +0800 | [diff] [blame] | 656 | } |
Peng Fan | fa55b21 | 2021-08-07 16:00:57 +0800 | [diff] [blame] | 657 | |
Ye Li | 7201262 | 2021-10-29 09:46:15 +0800 | [diff] [blame] | 658 | /* Release xrdc, then allow A35 to write SRAM2 */ |
| 659 | if (rdc_en) |
| 660 | release_rdc(RDC_XRDC); |
| 661 | |
Ye Li | 853cc9d | 2021-08-07 16:00:55 +0800 | [diff] [blame] | 662 | xrdc_mrc_region_set_access(2, CONFIG_SPL_TEXT_BASE, 0xE00); |
| 663 | |
Peng Fan | 4cdb3a3 | 2022-04-06 14:30:12 +0800 | [diff] [blame] | 664 | clock_init_early(); |
Ye Li | 6ee435eb | 2021-08-07 16:00:50 +0800 | [diff] [blame] | 665 | } else { |
| 666 | /* reconfigure core0 reset vector to ROM */ |
| 667 | set_core0_reset_vector(0x1000); |
| 668 | } |
| 669 | |
| 670 | return 0; |
| 671 | } |
| 672 | |
Simon Glass | fc55736 | 2022-03-04 08:43:05 -0700 | [diff] [blame] | 673 | static int imx8ulp_check_mu(void *ctx, struct event *event) |
Ye Li | 7bea5b0 | 2021-08-07 16:01:00 +0800 | [diff] [blame] | 674 | { |
| 675 | struct udevice *devp; |
| 676 | int node, ret; |
| 677 | |
| 678 | node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx8ulp-mu"); |
| 679 | |
| 680 | ret = uclass_get_device_by_of_offset(UCLASS_MISC, node, &devp); |
| 681 | if (ret) { |
| 682 | printf("could not get S400 mu %d\n", ret); |
| 683 | return ret; |
| 684 | } |
| 685 | |
| 686 | return 0; |
| 687 | } |
Simon Glass | fc55736 | 2022-03-04 08:43:05 -0700 | [diff] [blame] | 688 | EVENT_SPY(EVT_DM_POST_INIT, imx8ulp_check_mu); |
Ye Li | 7bea5b0 | 2021-08-07 16:01:00 +0800 | [diff] [blame] | 689 | |
Ye Li | 6ee435eb | 2021-08-07 16:00:50 +0800 | [diff] [blame] | 690 | #if defined(CONFIG_SPL_BUILD) |
| 691 | __weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) |
| 692 | { |
| 693 | debug("image entry point: 0x%lx\n", spl_image->entry_point); |
| 694 | |
| 695 | set_core0_reset_vector((u32)spl_image->entry_point); |
Ye Li | 6dd4302 | 2021-08-07 16:00:48 +0800 | [diff] [blame] | 696 | |
| 697 | /* Enable the 512KB cache */ |
| 698 | setbits_le32(SIM1_BASE_ADDR + 0x30, (0x1 << 4)); |
| 699 | |
| 700 | /* reset core */ |
| 701 | setbits_le32(SIM1_BASE_ADDR + 0x30, (0x1 << 16)); |
| 702 | |
| 703 | while (1) |
| 704 | ; |
| 705 | } |
| 706 | #endif |
Peng Fan | fa6ae05 | 2021-08-07 16:01:03 +0800 | [diff] [blame] | 707 | |
| 708 | void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) |
| 709 | { |
Ye Li | 992b0ae | 2021-10-29 09:46:28 +0800 | [diff] [blame] | 710 | u32 val[2] = {}; |
| 711 | int ret; |
| 712 | |
| 713 | ret = fuse_read(5, 3, &val[0]); |
| 714 | if (ret) |
| 715 | goto err; |
| 716 | |
| 717 | ret = fuse_read(5, 4, &val[1]); |
| 718 | if (ret) |
| 719 | goto err; |
| 720 | |
| 721 | mac[0] = val[0]; |
| 722 | mac[1] = val[0] >> 8; |
| 723 | mac[2] = val[0] >> 16; |
| 724 | mac[3] = val[0] >> 24; |
| 725 | mac[4] = val[1]; |
| 726 | mac[5] = val[1] >> 8; |
| 727 | |
| 728 | debug("%s: MAC%d: %02x.%02x.%02x.%02x.%02x.%02x\n", |
| 729 | __func__, dev_id, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); |
| 730 | return; |
| 731 | err: |
Peng Fan | fa6ae05 | 2021-08-07 16:01:03 +0800 | [diff] [blame] | 732 | memset(mac, 0, 6); |
Ye Li | 992b0ae | 2021-10-29 09:46:28 +0800 | [diff] [blame] | 733 | printf("%s: fuse read err: %d\n", __func__, ret); |
Peng Fan | fa6ae05 | 2021-08-07 16:01:03 +0800 | [diff] [blame] | 734 | } |
Ye Li | 479fd4a | 2021-08-07 16:01:08 +0800 | [diff] [blame] | 735 | |
| 736 | int (*card_emmc_is_boot_part_en)(void) = (void *)0x67cc; |
| 737 | u32 spl_arch_boot_image_offset(u32 image_offset, u32 rom_bt_dev) |
| 738 | { |
| 739 | /* Hard code for eMMC image_offset on 8ULP ROM, need fix by ROM, temp workaround */ |
| 740 | if (((rom_bt_dev >> 16) & 0xff) == BT_DEV_TYPE_MMC && card_emmc_is_boot_part_en()) |
| 741 | image_offset = 0; |
| 742 | |
| 743 | return image_offset; |
| 744 | } |
Ye Li | 48836ae | 2022-04-06 14:30:30 +0800 | [diff] [blame] | 745 | |
| 746 | enum env_location env_get_location(enum env_operation op, int prio) |
| 747 | { |
| 748 | enum boot_device dev = get_boot_device(); |
| 749 | enum env_location env_loc = ENVL_UNKNOWN; |
| 750 | |
| 751 | if (prio) |
| 752 | return env_loc; |
| 753 | |
| 754 | switch (dev) { |
| 755 | #ifdef CONFIG_ENV_IS_IN_SPI_FLASH |
| 756 | case QSPI_BOOT: |
| 757 | env_loc = ENVL_SPI_FLASH; |
| 758 | break; |
| 759 | #endif |
| 760 | #ifdef CONFIG_ENV_IS_IN_MMC |
| 761 | case SD1_BOOT: |
| 762 | case SD2_BOOT: |
| 763 | case SD3_BOOT: |
| 764 | case MMC1_BOOT: |
| 765 | case MMC2_BOOT: |
| 766 | case MMC3_BOOT: |
| 767 | env_loc = ENVL_MMC; |
| 768 | break; |
| 769 | #endif |
| 770 | default: |
| 771 | #if defined(CONFIG_ENV_IS_NOWHERE) |
| 772 | env_loc = ENVL_NOWHERE; |
| 773 | #endif |
| 774 | break; |
| 775 | } |
| 776 | |
| 777 | return env_loc; |
| 778 | } |