| Shengzhou Liu | 8b033cf | 2011-08-31 17:48:18 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2011 Freescale Semiconductor, Inc. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or |
| 5 | * modify it under the terms of the GNU General Public License as |
| 6 | * published by the Free Software Foundation; either version 2 of |
| 7 | * the License, or (at your option) any later version. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License |
| 15 | * along with this program; if not, write to the Free Software |
| 16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 17 | * MA 02111-1307 USA |
| 18 | */ |
| 19 | #include <common.h> |
| 20 | #include <phy.h> |
| 21 | #include <fm_eth.h> |
| 22 | #include <asm/io.h> |
| 23 | #include <asm/immap_85xx.h> |
| 24 | #include <asm/fsl_serdes.h> |
| 25 | |
| 26 | u32 port_to_devdisr[] = { |
| 27 | [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1, |
| 28 | [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2, |
| 29 | [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3, |
| 30 | [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4, |
| 31 | [FM2_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC2_1, |
| 32 | [FM2_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC2_2, |
| 33 | [FM2_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC2_3, |
| 34 | [FM2_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC2_4, |
| 35 | }; |
| 36 | |
| 37 | static int is_device_disabled(enum fm_port port) |
| 38 | { |
| 39 | ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
| 40 | u32 devdisr2 = in_be32(&gur->devdisr2); |
| 41 | |
| 42 | return port_to_devdisr[port] & devdisr2; |
| 43 | } |
| 44 | |
| 45 | void fman_disable_port(enum fm_port port) |
| 46 | { |
| 47 | ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
| Kumar Gala | 213c7b1 | 2011-10-14 03:17:56 -0500 | [diff] [blame] | 48 | |
| 49 | /* don't allow disabling of DTSEC1 as its needed for MDIO */ |
| 50 | if (port == FM1_DTSEC1) |
| 51 | return; |
| 52 | |
| Shengzhou Liu | 8b033cf | 2011-08-31 17:48:18 +0800 | [diff] [blame] | 53 | setbits_be32(&gur->devdisr2, port_to_devdisr[port]); |
| 54 | } |
| 55 | |
| 56 | phy_interface_t fman_port_enet_if(enum fm_port port) |
| 57 | { |
| 58 | ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
| 59 | u32 rcwsr11 = in_be32(&gur->rcwsr[11]); |
| Shengzhou Liu | 8b033cf | 2011-08-31 17:48:18 +0800 | [diff] [blame] | 60 | |
| 61 | if (is_device_disabled(port)) |
| 62 | return PHY_INTERFACE_MODE_NONE; |
| 63 | |
| 64 | /* handle RGMII/MII first */ |
| 65 | if ((port == FM1_DTSEC1) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) == |
| 66 | FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1)) |
| 67 | return PHY_INTERFACE_MODE_RGMII; |
| 68 | |
| 69 | if ((port == FM1_DTSEC2) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) == |
| 70 | FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2)) |
| 71 | return PHY_INTERFACE_MODE_RGMII; |
| 72 | |
| 73 | if ((port == FM2_DTSEC1) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) == |
| 74 | FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1)) |
| 75 | return PHY_INTERFACE_MODE_RGMII; |
| 76 | |
| Shengzhou Liu | 8b033cf | 2011-08-31 17:48:18 +0800 | [diff] [blame] | 77 | switch (port) { |
| 78 | case FM1_DTSEC1: |
| 79 | case FM1_DTSEC2: |
| 80 | case FM1_DTSEC3: |
| 81 | case FM1_DTSEC4: |
| 82 | if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1)) |
| 83 | return PHY_INTERFACE_MODE_SGMII; |
| 84 | break; |
| 85 | case FM2_DTSEC1: |
| 86 | case FM2_DTSEC2: |
| 87 | case FM2_DTSEC3: |
| 88 | case FM2_DTSEC4: |
| 89 | if (is_serdes_configured(SGMII_FM2_DTSEC1 + port - FM2_DTSEC1)) |
| 90 | return PHY_INTERFACE_MODE_SGMII; |
| 91 | break; |
| 92 | default: |
| 93 | return PHY_INTERFACE_MODE_NONE; |
| 94 | } |
| 95 | |
| 96 | return PHY_INTERFACE_MODE_NONE; |
| 97 | } |