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Dipen Dudhat9eae0832011-03-22 09:27:39 +05301/* Integrated Flash Controller NAND Machine Driver
2 *
Prabhakar Kushwahacdd045d2012-01-20 18:38:14 +05303 * Copyright (c) 2012 Freescale Semiconductor, Inc
Dipen Dudhat9eae0832011-03-22 09:27:39 +05304 *
5 * Authors: Dipen Dudhat <Dipen.Dudhat@freescale.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include <common.h>
23#include <malloc.h>
24
25#include <linux/mtd/mtd.h>
26#include <linux/mtd/nand.h>
27#include <linux/mtd/nand_ecc.h>
28
29#include <asm/io.h>
30#include <asm/errno.h>
31#include <asm/fsl_ifc.h>
32
33#define MAX_BANKS 4
34#define ERR_BYTE 0xFF /* Value returned for read bytes
35 when read failed */
36#define IFC_TIMEOUT_MSECS 10 /* Maximum number of mSecs to wait for IFC
37 NAND Machine */
38
39struct fsl_ifc_ctrl;
40
41/* mtd information per set */
42struct fsl_ifc_mtd {
43 struct mtd_info mtd;
44 struct nand_chip chip;
45 struct fsl_ifc_ctrl *ctrl;
46
47 struct device *dev;
48 int bank; /* Chip select bank number */
49 unsigned int bufnum_mask; /* bufnum = page & bufnum_mask */
50 u8 __iomem *vbase; /* Chip select base virtual address */
51};
52
53/* overview of the fsl ifc controller */
54struct fsl_ifc_ctrl {
55 struct nand_hw_control controller;
56 struct fsl_ifc_mtd *chips[MAX_BANKS];
57
58 /* device info */
59 struct fsl_ifc *regs;
60 uint8_t __iomem *addr; /* Address of assigned IFC buffer */
61 unsigned int cs_nand; /* On which chipsel NAND is connected */
62 unsigned int page; /* Last page written to / read from */
63 unsigned int read_bytes; /* Number of bytes read during command */
64 unsigned int column; /* Saved column from SEQIN */
65 unsigned int index; /* Pointer to next byte to 'read' */
66 unsigned int status; /* status read from NEESR after last op */
67 unsigned int oob; /* Non zero if operating on OOB data */
68 unsigned int eccread; /* Non zero for a full-page ECC read */
69};
70
71static struct fsl_ifc_ctrl *ifc_ctrl;
72
73/* 512-byte page with 4-bit ECC, 8-bit */
74static struct nand_ecclayout oob_512_8bit_ecc4 = {
75 .eccbytes = 8,
76 .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
77 .oobfree = { {0, 5}, {6, 2} },
78};
79
80/* 512-byte page with 4-bit ECC, 16-bit */
81static struct nand_ecclayout oob_512_16bit_ecc4 = {
82 .eccbytes = 8,
83 .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
84 .oobfree = { {2, 6}, },
85};
86
87/* 2048-byte page size with 4-bit ECC */
88static struct nand_ecclayout oob_2048_ecc4 = {
89 .eccbytes = 32,
90 .eccpos = {
91 8, 9, 10, 11, 12, 13, 14, 15,
92 16, 17, 18, 19, 20, 21, 22, 23,
93 24, 25, 26, 27, 28, 29, 30, 31,
94 32, 33, 34, 35, 36, 37, 38, 39,
95 },
96 .oobfree = { {2, 6}, {40, 24} },
97};
98
99/* 4096-byte page size with 4-bit ECC */
100static struct nand_ecclayout oob_4096_ecc4 = {
101 .eccbytes = 64,
102 .eccpos = {
103 8, 9, 10, 11, 12, 13, 14, 15,
104 16, 17, 18, 19, 20, 21, 22, 23,
105 24, 25, 26, 27, 28, 29, 30, 31,
106 32, 33, 34, 35, 36, 37, 38, 39,
107 40, 41, 42, 43, 44, 45, 46, 47,
108 48, 49, 50, 51, 52, 53, 54, 55,
109 56, 57, 58, 59, 60, 61, 62, 63,
110 64, 65, 66, 67, 68, 69, 70, 71,
111 },
112 .oobfree = { {2, 6}, {72, 56} },
113};
114
115/* 4096-byte page size with 8-bit ECC -- requires 218-byte OOB */
116static struct nand_ecclayout oob_4096_ecc8 = {
117 .eccbytes = 128,
118 .eccpos = {
119 8, 9, 10, 11, 12, 13, 14, 15,
120 16, 17, 18, 19, 20, 21, 22, 23,
121 24, 25, 26, 27, 28, 29, 30, 31,
122 32, 33, 34, 35, 36, 37, 38, 39,
123 40, 41, 42, 43, 44, 45, 46, 47,
124 48, 49, 50, 51, 52, 53, 54, 55,
125 56, 57, 58, 59, 60, 61, 62, 63,
126 64, 65, 66, 67, 68, 69, 70, 71,
127 72, 73, 74, 75, 76, 77, 78, 79,
128 80, 81, 82, 83, 84, 85, 86, 87,
129 88, 89, 90, 91, 92, 93, 94, 95,
130 96, 97, 98, 99, 100, 101, 102, 103,
131 104, 105, 106, 107, 108, 109, 110, 111,
132 112, 113, 114, 115, 116, 117, 118, 119,
133 120, 121, 122, 123, 124, 125, 126, 127,
134 128, 129, 130, 131, 132, 133, 134, 135,
135 },
136 .oobfree = { {2, 6}, {136, 82} },
137};
138
139
140/*
141 * Generic flash bbt descriptors
142 */
143static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
144static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
145
146static struct nand_bbt_descr bbt_main_descr = {
147 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
148 NAND_BBT_2BIT | NAND_BBT_VERSION,
149 .offs = 2, /* 0 on 8-bit small page */
150 .len = 4,
151 .veroffs = 6,
152 .maxblocks = 4,
153 .pattern = bbt_pattern,
154};
155
156static struct nand_bbt_descr bbt_mirror_descr = {
157 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
158 NAND_BBT_2BIT | NAND_BBT_VERSION,
159 .offs = 2, /* 0 on 8-bit small page */
160 .len = 4,
161 .veroffs = 6,
162 .maxblocks = 4,
163 .pattern = mirror_pattern,
164};
165
166/*
167 * Set up the IFC hardware block and page address fields, and the ifc nand
168 * structure addr field to point to the correct IFC buffer in memory
169 */
170static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
171{
172 struct nand_chip *chip = mtd->priv;
173 struct fsl_ifc_mtd *priv = chip->priv;
174 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
175 struct fsl_ifc *ifc = ctrl->regs;
176 int buf_num;
177
178 ctrl->page = page_addr;
179
180 /* Program ROW0/COL0 */
181 out_be32(&ifc->ifc_nand.row0, page_addr);
182 out_be32(&ifc->ifc_nand.col0, (oob ? IFC_NAND_COL_MS : 0) | column);
183
184 buf_num = page_addr & priv->bufnum_mask;
185
186 ctrl->addr = priv->vbase + buf_num * (mtd->writesize * 2);
187 ctrl->index = column;
188
189 /* for OOB data point to the second half of the buffer */
190 if (oob)
191 ctrl->index += mtd->writesize;
192}
193
194static int is_blank(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
195 unsigned int bufnum)
196{
197 struct nand_chip *chip = mtd->priv;
198 struct fsl_ifc_mtd *priv = chip->priv;
199 u8 __iomem *addr = priv->vbase + bufnum * (mtd->writesize * 2);
200 u32 __iomem *main = (u32 *)addr;
201 u8 __iomem *oob = addr + mtd->writesize;
202 int i;
203
204 for (i = 0; i < mtd->writesize / 4; i++) {
205 if (__raw_readl(&main[i]) != 0xffffffff)
206 return 0;
207 }
208
209 for (i = 0; i < chip->ecc.layout->eccbytes; i++) {
210 int pos = chip->ecc.layout->eccpos[i];
211
212 if (__raw_readb(&oob[pos]) != 0xff)
213 return 0;
214 }
215
216 return 1;
217}
218
219/* returns nonzero if entire page is blank */
220static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
221 u32 *eccstat, unsigned int bufnum)
222{
223 u32 reg = eccstat[bufnum / 4];
Prabhakar Kushwahacdd045d2012-01-20 18:38:14 +0530224 int errors;
Dipen Dudhat9eae0832011-03-22 09:27:39 +0530225
Prabhakar Kushwahacdd045d2012-01-20 18:38:14 +0530226 errors = (reg >> ((3 - bufnum % 4) * 8)) & 15;
Dipen Dudhat9eae0832011-03-22 09:27:39 +0530227
Prabhakar Kushwahacdd045d2012-01-20 18:38:14 +0530228 return errors;
Dipen Dudhat9eae0832011-03-22 09:27:39 +0530229}
230
231/*
232 * execute IFC NAND command and wait for it to complete
233 */
234static int fsl_ifc_run_command(struct mtd_info *mtd)
235{
236 struct nand_chip *chip = mtd->priv;
237 struct fsl_ifc_mtd *priv = chip->priv;
238 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
239 struct fsl_ifc *ifc = ctrl->regs;
240 long long end_tick;
241 u32 eccstat[4];
242 int i;
243
244 /* set the chip select for NAND Transaction */
245 out_be32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand);
246
247 /* start read/write seq */
248 out_be32(&ifc->ifc_nand.nandseq_strt,
249 IFC_NAND_SEQ_STRT_FIR_STRT);
250
251 /* wait for NAND Machine complete flag or timeout */
252 end_tick = usec2ticks(IFC_TIMEOUT_MSECS * 1000) + get_ticks();
253
254 while (end_tick > get_ticks()) {
255 ctrl->status = in_be32(&ifc->ifc_nand.nand_evter_stat);
256
257 if (ctrl->status & IFC_NAND_EVTER_STAT_OPC)
258 break;
259 }
260
261 out_be32(&ifc->ifc_nand.nand_evter_stat, ctrl->status);
262
263 if (ctrl->status & IFC_NAND_EVTER_STAT_FTOER)
264 printf("%s: Flash Time Out Error\n", __func__);
265 if (ctrl->status & IFC_NAND_EVTER_STAT_WPER)
266 printf("%s: Write Protect Error\n", __func__);
267
268 if (ctrl->eccread) {
Prabhakar Kushwahacdd045d2012-01-20 18:38:14 +0530269 int errors;
270 int bufnum = ctrl->page & priv->bufnum_mask;
271 int sector = bufnum * chip->ecc.steps;
272 int sector_end = sector + chip->ecc.steps - 1;
Dipen Dudhat9eae0832011-03-22 09:27:39 +0530273
Prabhakar Kushwahacdd045d2012-01-20 18:38:14 +0530274 for (i = sector / 4; i <= sector_end / 4; i++)
Dipen Dudhat9eae0832011-03-22 09:27:39 +0530275 eccstat[i] = in_be32(&ifc->ifc_nand.nand_eccstat[i]);
276
Prabhakar Kushwahacdd045d2012-01-20 18:38:14 +0530277 for (i = sector; i <= sector_end; i++) {
278 errors = check_read_ecc(mtd, ctrl, eccstat, i);
279
280 if (errors == 15) {
281 /*
282 * Uncorrectable error.
283 * OK only if the whole page is blank.
284 *
285 * We disable ECCER reporting due to erratum
286 * IFC-A002770 -- so report it now if we
287 * see an uncorrectable error in ECCSTAT.
288 */
289 if (!is_blank(mtd, ctrl, bufnum))
290 ctrl->status |=
291 IFC_NAND_EVTER_STAT_ECCER;
Dipen Dudhat9eae0832011-03-22 09:27:39 +0530292 break;
Prabhakar Kushwahacdd045d2012-01-20 18:38:14 +0530293 }
294
295 mtd->ecc_stats.corrected += errors;
Dipen Dudhat9eae0832011-03-22 09:27:39 +0530296 }
297
298 ctrl->eccread = 0;
299 }
300
301 /* returns 0 on success otherwise non-zero) */
302 return ctrl->status == IFC_NAND_EVTER_STAT_OPC ? 0 : -EIO;
303}
304
305static void fsl_ifc_do_read(struct nand_chip *chip,
306 int oob,
307 struct mtd_info *mtd)
308{
309 struct fsl_ifc_mtd *priv = chip->priv;
310 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
311 struct fsl_ifc *ifc = ctrl->regs;
312
313 /* Program FIR/IFC_NAND_FCR0 for Small/Large page */
314 if (mtd->writesize > 512) {
315 out_be32(&ifc->ifc_nand.nand_fir0,
316 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
317 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
318 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
319 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
320 (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT));
321 out_be32(&ifc->ifc_nand.nand_fir1, 0x0);
322
323 out_be32(&ifc->ifc_nand.nand_fcr0,
324 (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
325 (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
326 } else {
327 out_be32(&ifc->ifc_nand.nand_fir0,
328 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
329 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
330 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
331 (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT));
332
333 if (oob)
334 out_be32(&ifc->ifc_nand.nand_fcr0,
335 NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT);
336 else
337 out_be32(&ifc->ifc_nand.nand_fcr0,
338 NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
339 }
340}
341
342/* cmdfunc send commands to the IFC NAND Machine */
343static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
344 int column, int page_addr)
345{
346 struct nand_chip *chip = mtd->priv;
347 struct fsl_ifc_mtd *priv = chip->priv;
348 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
349 struct fsl_ifc *ifc = ctrl->regs;
350
351 /* clear the read buffer */
352 ctrl->read_bytes = 0;
353 if (command != NAND_CMD_PAGEPROG)
354 ctrl->index = 0;
355
356 switch (command) {
357 /* READ0 read the entire buffer to use hardware ECC. */
358 case NAND_CMD_READ0: {
359 out_be32(&ifc->ifc_nand.nand_fbcr, 0);
360 set_addr(mtd, 0, page_addr, 0);
361
362 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
363 ctrl->index += column;
364
365 if (chip->ecc.mode == NAND_ECC_HW)
366 ctrl->eccread = 1;
367
368 fsl_ifc_do_read(chip, 0, mtd);
369 fsl_ifc_run_command(mtd);
370 return;
371 }
372
373 /* READOOB reads only the OOB because no ECC is performed. */
374 case NAND_CMD_READOOB:
375 out_be32(&ifc->ifc_nand.nand_fbcr, mtd->oobsize - column);
376 set_addr(mtd, column, page_addr, 1);
377
378 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
379
380 fsl_ifc_do_read(chip, 1, mtd);
381 fsl_ifc_run_command(mtd);
382
383 return;
384
385 /* READID must read all possible bytes while CEB is active */
386 case NAND_CMD_READID:
387 out_be32(&ifc->ifc_nand.nand_fir0,
388 (IFC_FIR_OP_CMD0 << IFC_NAND_FIR0_OP0_SHIFT) |
389 (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
390 (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT));
391 out_be32(&ifc->ifc_nand.nand_fcr0,
392 NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT);
393 /* 4 bytes for manuf, device and exts */
394 out_be32(&ifc->ifc_nand.nand_fbcr, 4);
395 ctrl->read_bytes = 4;
396
397 set_addr(mtd, 0, 0, 0);
398 fsl_ifc_run_command(mtd);
399 return;
400
401 /* ERASE1 stores the block and page address */
402 case NAND_CMD_ERASE1:
403 set_addr(mtd, 0, page_addr, 0);
404 return;
405
406 /* ERASE2 uses the block and page address from ERASE1 */
407 case NAND_CMD_ERASE2:
408 out_be32(&ifc->ifc_nand.nand_fir0,
409 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
410 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) |
411 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT));
412
413 out_be32(&ifc->ifc_nand.nand_fcr0,
414 (NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) |
415 (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT));
416
417 out_be32(&ifc->ifc_nand.nand_fbcr, 0);
418 ctrl->read_bytes = 0;
419 fsl_ifc_run_command(mtd);
420 return;
421
422 /* SEQIN sets up the addr buffer and all registers except the length */
423 case NAND_CMD_SEQIN: {
424 u32 nand_fcr0;
425 ctrl->column = column;
426 ctrl->oob = 0;
427
428 if (mtd->writesize > 512) {
429 nand_fcr0 =
430 (NAND_CMD_SEQIN << IFC_NAND_FCR0_CMD0_SHIFT) |
431 (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD1_SHIFT);
432
433 out_be32(&ifc->ifc_nand.nand_fir0,
434 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
435 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
436 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
437 (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP3_SHIFT) |
438 (IFC_FIR_OP_CW1 << IFC_NAND_FIR0_OP4_SHIFT));
439 out_be32(&ifc->ifc_nand.nand_fir1, 0);
440 } else {
441 nand_fcr0 = ((NAND_CMD_PAGEPROG <<
442 IFC_NAND_FCR0_CMD1_SHIFT) |
443 (NAND_CMD_SEQIN <<
444 IFC_NAND_FCR0_CMD2_SHIFT));
445
446 out_be32(&ifc->ifc_nand.nand_fir0,
447 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
448 (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) |
449 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) |
450 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) |
451 (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT));
452 out_be32(&ifc->ifc_nand.nand_fir1,
453 (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT));
454
Prabhakar Kushwaha0ed5e772012-01-20 18:39:05 +0530455 if (column >= mtd->writesize)
456 nand_fcr0 |=
457 NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT;
458 else
459 nand_fcr0 |=
460 NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT;
Dipen Dudhat9eae0832011-03-22 09:27:39 +0530461 }
462
Prabhakar Kushwaha0ed5e772012-01-20 18:39:05 +0530463 if (column >= mtd->writesize) {
464 /* OOB area --> READOOB */
465 column -= mtd->writesize;
466 ctrl->oob = 1;
467 }
Dipen Dudhat9eae0832011-03-22 09:27:39 +0530468 out_be32(&ifc->ifc_nand.nand_fcr0, nand_fcr0);
469 set_addr(mtd, column, page_addr, ctrl->oob);
470 return;
471 }
472
473 /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
474 case NAND_CMD_PAGEPROG:
475 if (ctrl->oob)
Prabhakar Kushwaha0ed5e772012-01-20 18:39:05 +0530476 out_be32(&ifc->ifc_nand.nand_fbcr,
477 ctrl->index - ctrl->column);
Dipen Dudhat9eae0832011-03-22 09:27:39 +0530478 else
479 out_be32(&ifc->ifc_nand.nand_fbcr, 0);
480
481 fsl_ifc_run_command(mtd);
482 return;
483
484 case NAND_CMD_STATUS:
485 out_be32(&ifc->ifc_nand.nand_fir0,
486 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
487 (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT));
488 out_be32(&ifc->ifc_nand.nand_fcr0,
489 NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT);
490 out_be32(&ifc->ifc_nand.nand_fbcr, 1);
491 set_addr(mtd, 0, 0, 0);
492 ctrl->read_bytes = 1;
493
494 fsl_ifc_run_command(mtd);
495
496 /* Chip sometimes reporting write protect even when it's not */
497 out_8(ctrl->addr, in_8(ctrl->addr) | NAND_STATUS_WP);
498 return;
499
500 case NAND_CMD_RESET:
501 out_be32(&ifc->ifc_nand.nand_fir0,
502 IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT);
503 out_be32(&ifc->ifc_nand.nand_fcr0,
504 NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT);
505 fsl_ifc_run_command(mtd);
506 return;
507
508 default:
509 printf("%s: error, unsupported command 0x%x.\n",
510 __func__, command);
511 }
512}
513
514/*
515 * Write buf to the IFC NAND Controller Data Buffer
516 */
517static void fsl_ifc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
518{
519 struct nand_chip *chip = mtd->priv;
520 struct fsl_ifc_mtd *priv = chip->priv;
521 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
522 unsigned int bufsize = mtd->writesize + mtd->oobsize;
523
524 if (len <= 0) {
525 printf("%s of %d bytes", __func__, len);
526 ctrl->status = 0;
527 return;
528 }
529
530 if ((unsigned int)len > bufsize - ctrl->index) {
531 printf("%s beyond end of buffer "
532 "(%d requested, %u available)\n",
533 __func__, len, bufsize - ctrl->index);
534 len = bufsize - ctrl->index;
535 }
536
537 memcpy_toio(&ctrl->addr[ctrl->index], buf, len);
538 ctrl->index += len;
539}
540
541/*
542 * read a byte from either the IFC hardware buffer if it has any data left
543 * otherwise issue a command to read a single byte.
544 */
545static u8 fsl_ifc_read_byte(struct mtd_info *mtd)
546{
547 struct nand_chip *chip = mtd->priv;
548 struct fsl_ifc_mtd *priv = chip->priv;
549 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
550
551 /* If there are still bytes in the IFC buffer, then use the
552 * next byte. */
553 if (ctrl->index < ctrl->read_bytes)
554 return in_8(&ctrl->addr[ctrl->index++]);
555
556 printf("%s beyond end of buffer\n", __func__);
557 return ERR_BYTE;
558}
559
560/*
561 * Read two bytes from the IFC hardware buffer
562 * read function for 16-bit buswith
563 */
564static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd)
565{
566 struct nand_chip *chip = mtd->priv;
567 struct fsl_ifc_mtd *priv = chip->priv;
568 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
569 uint16_t data;
570
571 /*
572 * If there are still bytes in the IFC buffer, then use the
573 * next byte.
574 */
575 if (ctrl->index < ctrl->read_bytes) {
576 data = in_be16((uint16_t *)&ctrl->
577 addr[ctrl->index]);
578 ctrl->index += 2;
579 return (uint8_t)data;
580 }
581
582 printf("%s beyond end of buffer\n", __func__);
583 return ERR_BYTE;
584}
585
586/*
587 * Read from the IFC Controller Data Buffer
588 */
589static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
590{
591 struct nand_chip *chip = mtd->priv;
592 struct fsl_ifc_mtd *priv = chip->priv;
593 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
594 int avail;
595
596 if (len < 0)
597 return;
598
599 avail = min((unsigned int)len, ctrl->read_bytes - ctrl->index);
600 memcpy_fromio(buf, &ctrl->addr[ctrl->index], avail);
601 ctrl->index += avail;
602
603 if (len > avail)
604 printf("%s beyond end of buffer "
605 "(%d requested, %d available)\n",
606 __func__, len, avail);
607}
608
609/*
610 * Verify buffer against the IFC Controller Data Buffer
611 */
612static int fsl_ifc_verify_buf(struct mtd_info *mtd,
613 const u_char *buf, int len)
614{
615 struct nand_chip *chip = mtd->priv;
616 struct fsl_ifc_mtd *priv = chip->priv;
617 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
618 int i;
619
620 if (len < 0) {
621 printf("%s of %d bytes", __func__, len);
622 return -EINVAL;
623 }
624
625 if ((unsigned int)len > ctrl->read_bytes - ctrl->index) {
626 printf("%s beyond end of buffer "
627 "(%d requested, %u available)\n",
628 __func__, len, ctrl->read_bytes - ctrl->index);
629
630 ctrl->index = ctrl->read_bytes;
631 return -EINVAL;
632 }
633
634 for (i = 0; i < len; i++)
635 if (in_8(&ctrl->addr[ctrl->index + i]) != buf[i])
636 break;
637
638 ctrl->index += len;
639 return i == len && ctrl->status == IFC_NAND_EVTER_STAT_OPC ? 0 : -EIO;
640}
641
642/* This function is called after Program and Erase Operations to
643 * check for success or failure.
644 */
645static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
646{
647 struct fsl_ifc_mtd *priv = chip->priv;
648 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
649 struct fsl_ifc *ifc = ctrl->regs;
650 u32 nand_fsr;
651
652 if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
653 return NAND_STATUS_FAIL;
654
655 /* Use READ_STATUS command, but wait for the device to be ready */
656 out_be32(&ifc->ifc_nand.nand_fir0,
657 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
658 (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT));
659 out_be32(&ifc->ifc_nand.nand_fcr0, NAND_CMD_STATUS <<
660 IFC_NAND_FCR0_CMD0_SHIFT);
661 out_be32(&ifc->ifc_nand.nand_fbcr, 1);
662 set_addr(mtd, 0, 0, 0);
663 ctrl->read_bytes = 1;
664
665 fsl_ifc_run_command(mtd);
666
667 if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
668 return NAND_STATUS_FAIL;
669
670 nand_fsr = in_be32(&ifc->ifc_nand.nand_fsr);
671
672 /* Chip sometimes reporting write protect even when it's not */
673 nand_fsr = nand_fsr | NAND_STATUS_WP;
674 return nand_fsr;
675}
676
677static int fsl_ifc_read_page(struct mtd_info *mtd,
678 struct nand_chip *chip,
679 uint8_t *buf, int page)
680{
681 struct fsl_ifc_mtd *priv = chip->priv;
682 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
683
684 fsl_ifc_read_buf(mtd, buf, mtd->writesize);
685 fsl_ifc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
686
687 if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
688 mtd->ecc_stats.failed++;
689
690 return 0;
691}
692
693/* ECC will be calculated automatically, and errors will be detected in
694 * waitfunc.
695 */
696static void fsl_ifc_write_page(struct mtd_info *mtd,
697 struct nand_chip *chip,
698 const uint8_t *buf)
699{
700 fsl_ifc_write_buf(mtd, buf, mtd->writesize);
701 fsl_ifc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
702}
703
704static void fsl_ifc_ctrl_init(void)
705{
706 ifc_ctrl = kzalloc(sizeof(*ifc_ctrl), GFP_KERNEL);
707 if (!ifc_ctrl)
708 return;
709
710 ifc_ctrl->regs = IFC_BASE_ADDR;
711
712 /* clear event registers */
713 out_be32(&ifc_ctrl->regs->ifc_nand.nand_evter_stat, ~0U);
714 out_be32(&ifc_ctrl->regs->ifc_nand.pgrdcmpl_evt_stat, ~0U);
715
716 /* Enable error and event for any detected errors */
717 out_be32(&ifc_ctrl->regs->ifc_nand.nand_evter_en,
718 IFC_NAND_EVTER_EN_OPC_EN |
719 IFC_NAND_EVTER_EN_PGRDCMPL_EN |
720 IFC_NAND_EVTER_EN_FTOER_EN |
721 IFC_NAND_EVTER_EN_WPER_EN);
722
723 out_be32(&ifc_ctrl->regs->ifc_nand.ncfgr, 0x0);
724}
725
726static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip)
727{
728}
729
730int board_nand_init(struct nand_chip *nand)
731{
732 struct fsl_ifc_mtd *priv;
733 struct nand_ecclayout *layout;
734 uint32_t cspr = 0, csor = 0;
735
736 if (!ifc_ctrl) {
737 fsl_ifc_ctrl_init();
738 if (!ifc_ctrl)
739 return -1;
740 }
741
742 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
743 if (!priv)
744 return -ENOMEM;
745
746 priv->ctrl = ifc_ctrl;
747 priv->vbase = nand->IO_ADDR_R;
748
749 /* Find which chip select it is connected to.
750 */
751 for (priv->bank = 0; priv->bank < MAX_BANKS; priv->bank++) {
752 phys_addr_t base_addr = virt_to_phys(nand->IO_ADDR_R);
753
754 cspr = in_be32(&ifc_ctrl->regs->cspr_cs[priv->bank].cspr);
755 csor = in_be32(&ifc_ctrl->regs->csor_cs[priv->bank].csor);
756
757 if ((cspr & CSPR_V) && (cspr & CSPR_MSEL) == CSPR_MSEL_NAND &&
758 (cspr & CSPR_BA) == CSPR_PHYS_ADDR(base_addr)) {
759 ifc_ctrl->cs_nand = priv->bank << IFC_NAND_CSEL_SHIFT;
760 break;
761 }
762 }
763
764 if (priv->bank >= MAX_BANKS) {
765 printf("%s: address did not match any "
766 "chip selects\n", __func__);
767 return -ENODEV;
768 }
769
770 ifc_ctrl->chips[priv->bank] = priv;
771
772 /* fill in nand_chip structure */
773 /* set up function call table */
774
775 nand->write_buf = fsl_ifc_write_buf;
776 nand->read_buf = fsl_ifc_read_buf;
777 nand->verify_buf = fsl_ifc_verify_buf;
778 nand->select_chip = fsl_ifc_select_chip;
779 nand->cmdfunc = fsl_ifc_cmdfunc;
780 nand->waitfunc = fsl_ifc_wait;
781
782 /* set up nand options */
783 nand->bbt_td = &bbt_main_descr;
784 nand->bbt_md = &bbt_mirror_descr;
785
786 /* set up nand options */
787 nand->options = NAND_NO_READRDY | NAND_NO_AUTOINCR |
788 NAND_USE_FLASH_BBT;
789
790 if (cspr & CSPR_PORT_SIZE_16) {
791 nand->read_byte = fsl_ifc_read_byte16;
792 nand->options |= NAND_BUSWIDTH_16;
793 } else {
794 nand->read_byte = fsl_ifc_read_byte;
795 }
796
797 nand->controller = &ifc_ctrl->controller;
798 nand->priv = priv;
799
800 nand->ecc.read_page = fsl_ifc_read_page;
801 nand->ecc.write_page = fsl_ifc_write_page;
802
803 /* Hardware generates ECC per 512 Bytes */
804 nand->ecc.size = 512;
805 nand->ecc.bytes = 8;
806
807 switch (csor & CSOR_NAND_PGS_MASK) {
808 case CSOR_NAND_PGS_512:
809 if (nand->options & NAND_BUSWIDTH_16) {
810 layout = &oob_512_16bit_ecc4;
811 } else {
812 layout = &oob_512_8bit_ecc4;
813
814 /* Avoid conflict with bad block marker */
815 bbt_main_descr.offs = 0;
816 bbt_mirror_descr.offs = 0;
817 }
818
819 priv->bufnum_mask = 15;
820 break;
821
822 case CSOR_NAND_PGS_2K:
823 layout = &oob_2048_ecc4;
824 priv->bufnum_mask = 3;
825 break;
826
827 case CSOR_NAND_PGS_4K:
828 if ((csor & CSOR_NAND_ECC_MODE_MASK) ==
829 CSOR_NAND_ECC_MODE_4) {
830 layout = &oob_4096_ecc4;
831 } else {
832 layout = &oob_4096_ecc8;
833 nand->ecc.bytes = 16;
834 }
835
836 priv->bufnum_mask = 1;
837 break;
838
839 default:
840 printf("ifc nand: bad csor %#x: bad page size\n", csor);
841 return -ENODEV;
842 }
843
844 /* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */
845 if (csor & CSOR_NAND_ECC_DEC_EN) {
846 nand->ecc.mode = NAND_ECC_HW;
847 nand->ecc.layout = layout;
848 } else {
849 nand->ecc.mode = NAND_ECC_SOFT;
850 }
851
852 return 0;
853}