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git01.mediatek.com / filogic / uboot / 31cf6f9cfcc6429d5fd88f3ab2b8f620733d2730 / . / board / renesas / ecovec / lowlevel_init.S
blob: 9fc63e0ff39452101ba7193246a7aece0aafa303 [file] [log] [blame]
Nobuhiro Iwamatsu45befad2011-11-15 12:29:06 +0900[diff] [blame]1/*
2 * Copyright (C) 2011 Renesas Solutions Corp.
3 * Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.Iwamatsu.yj@renesas.com>
4 *
5 * board/renesas/ecovec/lowlevel_init.S
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#include <config.h>
24#include <version.h>
25#include <asm/processor.h>
26#include <asm/macro.h>
27#include <configs/ecovec.h>
28
29 .global lowlevel_init
30
31 .text
32 .align 2
33
34lowlevel_init:
35
36 /* jump to 0xA0020000 if bit 1 of PVDR_A */
37 mov.l PVDR_A, r1
38 mov.l PVDR_D, r2
39 mov.b @r1, r0
40 tst r0, r2
41 bt 1f
42 mov.l JUMP_A, r1
43 jmp @r1
44 nop
45
461:
47 /* Disable watchdog */
48 write16 RWTCSR_A, RWTCSR_D
49
50 /* MMU Disable */
51 write32 MMUCR_A, MMUCR_D
52
53 /* Setup clocks */
54 write32 PLLCR_A, PLLCR_D
55 write32 FRQCRA_A, FRQCRA_D
56 write32 FRQCRB_A, FRQCRB_D
57
58 wait_timer TIMER_D
59
60 write32 MMSELR_A, MMSELR_D
61
62 /* Srtup BSC */
63 write32 CMNCR_A, CMNCR_D
64 write32 CS0BCR_A, CS0BCR_D
65 write32 CS0WCR_A, CS0WCR_D
66
67 wait_timer TIMER_D
68
69 /* Setup SDRAM */
70 write32 DBPDCNT0_A, DBPDCNT0_D0
71 write32 DBCONF_A, DBCONF_D
72 write32 DBTR0_A, DBTR0_D
73 write32 DBTR1_A, DBTR1_D
74 write32 DBTR2_A, DBTR2_D
75 write32 DBTR3_A, DBTR3_D
76 write32 DBKIND_A, DBKIND_D
77 write32 DBCKECNT_A, DBCKECNT_D
78
79 wait_timer TIMER_D
80
81 write32 DBCMDCNT_A, DBCMDCNT_D0
82 write32 DBMRCNT_A, DBMRCNT_D0
83 write32 DBMRCNT_A, DBMRCNT_D1
84 write32 DBMRCNT_A, DBMRCNT_D2
85 write32 DBMRCNT_A, DBMRCNT_D3
86 write32 DBCMDCNT_A, DBCMDCNT_D0
87 write32 DBCMDCNT_A, DBCMDCNT_D1
88 write32 DBCMDCNT_A, DBCMDCNT_D1
89 write32 DBMRCNT_A, DBMRCNT_D4
90 write32 DBMRCNT_A, DBMRCNT_D5
91 write32 DBMRCNT_A, DBMRCNT_D6
92
93 wait_timer TIMER_D
94
95 write32 DBEN_A, DBEN_D
96 write32 DBRFPDN1_A, DBRFPDN1_D
97 write32 DBRFPDN2_A, DBRFPDN2_D
98 write32 DBCMDCNT_A, DBCMDCNT_D0
99
100
101 /* Dummy read */
102 mov.l DUMMY_A ,r1
103 synco
104 mov.l @r1, r0
105 synco
106
107 mov.l SDRAM_A ,r1
108 synco
109 mov.l @r1, r0
110 synco
111 wait_timer TIMER_D
112
113 add #4, r1
114 synco
115 mov.l @r1, r0
116 synco
117 wait_timer TIMER_D
118
119 add #4, r1
120 synco
121 mov.l @r1, r0
122 synco
123 wait_timer TIMER_D
124
125 add #4, r1
126 synco
127 mov.l @r1, r0
128 synco
129 wait_timer TIMER_D
130
131 write32 DBCMDCNT_A, DBCMDCNT_D0
132 write32 DBCMDCNT_A, DBCMDCNT_D1
133 write32 DBPDCNT0_A, DBPDCNT0_D1
134 write32 DBRFPDN0_A, DBRFPDN0_D
135
136 wait_timer TIMER_D
137
138 write32 CCR_A, CCR_D
139
140 stc sr, r0
141 mov.l SR_MASK_D, r1
142 and r1, r0
143 ldc r0, sr
144
145 rts
146
147 .align 2
148
149PVDR_A: .long PVDR
150PVDR_D: .long 0x00000001
151JUMP_A: .long CONFIG_ECOVEC_ROMIMAGE_ADDR
152TIMER_D: .long 64
153RWTCSR_A: .long RWTCSR
154RWTCSR_D: .long 0x0000A507
155MMUCR_A: .long MMUCR
156MMUCR_D: .long 0x00000004
157PLLCR_A: .long PLLCR
158PLLCR_D: .long 0x00004000
159FRQCRA_A: .long FRQCRA
160FRQCRA_D: .long 0x8E003508
161FRQCRB_A: .long FRQCRB
162FRQCRB_D: .long 0x0
163MMSELR_A: .long MMSELR
164MMSELR_D: .long 0xA5A50000
165CMNCR_A: .long CMNCR
166CMNCR_D: .long 0x00000013
167CS0BCR_A: .long CS0BCR
168CS0BCR_D: .long 0x11110400
169CS0WCR_A: .long CS0WCR
170CS0WCR_D: .long 0x00000440
171DBPDCNT0_A: .long DBPDCNT0
172DBPDCNT0_D0: .long 0x00000181
173DBPDCNT0_D1: .long 0x00000080
174DBCONF_A: .long DBCONF
175DBCONF_D: .long 0x015B0002
176DBTR0_A: .long DBTR0
177DBTR0_D: .long 0x03061502
178DBTR1_A: .long DBTR1
179DBTR1_D: .long 0x02020102
180DBTR2_A: .long DBTR2
181DBTR2_D: .long 0x01090305
182DBTR3_A: .long DBTR3
183DBTR3_D: .long 0x00000002
184DBKIND_A: .long DBKIND
185DBKIND_D: .long 0x00000005
186DBCKECNT_A: .long DBCKECNT
187DBCKECNT_D: .long 0x00000001
188DBCMDCNT_A: .long DBCMDCNT
189DBCMDCNT_D0:.long 0x2
190DBCMDCNT_D1:.long 0x4
191DBMRCNT_A: .long DBMRCNT
192DBMRCNT_D0: .long 0x00020000
193DBMRCNT_D1: .long 0x00030000
194DBMRCNT_D2: .long 0x00010040
195DBMRCNT_D3: .long 0x00000532
196DBMRCNT_D4: .long 0x00000432
197DBMRCNT_D5: .long 0x000103C0
198DBMRCNT_D6: .long 0x00010040
199DBEN_A: .long DBEN
200DBEN_D: .long 0x01
201DBRFPDN0_A: .long DBRFPDN0
202DBRFPDN1_A: .long DBRFPDN1
203DBRFPDN2_A: .long DBRFPDN2
204DBRFPDN0_D: .long 0x00010000
205DBRFPDN1_D: .long 0x00000613
206DBRFPDN2_D: .long 0x238C003A
207SDRAM_A: .long 0xa8000000
208DUMMY_A: .long 0x0c400000
209CCR_A: .long CCR
210CCR_D: .long 0x0000090B
211SR_MASK_D: .long 0xEFFFFF0F