blob: d69d61396bcb6142fd96e28f1b41f6bfdfd140f6 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Wolfgang Denkb38e0df2007-03-06 18:08:43 +01002/*
3 * (C) Copyright 2002
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
Wolfgang Denkb38e0df2007-03-06 18:08:43 +01005 */
6
7#include <common.h>
Simon Glass8f3f7612019-11-14 12:57:42 -07008#include <irq_func.h>
Wolfgang Denkb38e0df2007-03-06 18:08:43 +01009
10/*
11 * CPU test
12 * Logic instructions: andi., andis.
13 *
14 * The test contains a pre-built table of instructions, operands and
15 * expected results. For each table entry, the test will cyclically use
16 * different sets of operand registers and result registers.
17 */
18
Wolfgang Denkb38e0df2007-03-06 18:08:43 +010019#include <post.h>
20#include "cpu_asm.h"
21
Tom Rini8eaa3c72022-11-19 18:45:44 -050022#if CFG_POST & CONFIG_SYS_POST_CPU
Wolfgang Denkb38e0df2007-03-06 18:08:43 +010023
24extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op);
25extern ulong cpu_post_makecr (long v);
26
27static struct cpu_post_andi_s
28{
29 ulong cmd;
30 ulong op1;
31 ushort op2;
32 ulong res;
33} cpu_post_andi_table[] =
34{
35 {
Wolfgang Denka1be4762008-05-20 16:00:29 +020036 OP_ANDI_,
Wolfgang Denkb38e0df2007-03-06 18:08:43 +010037 0x80008000,
38 0xffff,
39 0x00008000
40 },
41 {
Wolfgang Denka1be4762008-05-20 16:00:29 +020042 OP_ANDIS_,
Wolfgang Denkb38e0df2007-03-06 18:08:43 +010043 0x80008000,
44 0xffff,
45 0x80000000
46 },
47};
Mike Frysinger83a687b2011-05-10 07:28:35 +000048static unsigned int cpu_post_andi_size = ARRAY_SIZE(cpu_post_andi_table);
Wolfgang Denkb38e0df2007-03-06 18:08:43 +010049
50int cpu_post_test_andi (void)
51{
52 int ret = 0;
53 unsigned int i, reg;
54 int flag = disable_interrupts();
55
56 for (i = 0; i < cpu_post_andi_size && ret == 0; i++)
57 {
58 struct cpu_post_andi_s *test = cpu_post_andi_table + i;
59
60 for (reg = 0; reg < 32 && ret == 0; reg++)
61 {
62 unsigned int reg0 = (reg + 0) % 32;
63 unsigned int reg1 = (reg + 1) % 32;
64 unsigned int stk = reg < 16 ? 31 : 15;
Wolfgang Denka1be4762008-05-20 16:00:29 +020065 unsigned long codecr[] =
Wolfgang Denkb38e0df2007-03-06 18:08:43 +010066 {
67 ASM_STW(stk, 1, -4),
68 ASM_ADDI(stk, 1, -16),
69 ASM_STW(3, stk, 8),
70 ASM_STW(reg0, stk, 4),
71 ASM_STW(reg1, stk, 0),
72 ASM_LWZ(reg0, stk, 8),
73 ASM_11IX(test->cmd, reg1, reg0, test->op2),
74 ASM_STW(reg1, stk, 8),
75 ASM_LWZ(reg1, stk, 0),
76 ASM_LWZ(reg0, stk, 4),
77 ASM_LWZ(3, stk, 8),
78 ASM_ADDI(1, stk, 16),
79 ASM_LWZ(stk, 1, -4),
80 ASM_BLR,
81 };
82 ulong res;
83 ulong cr;
84
85 cpu_post_exec_21 (codecr, & cr, & res, test->op1);
86
87 ret = res == test->res &&
88 (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
89
90 if (ret != 0)
91 {
Wolfgang Denkec7fbf52013-10-04 17:43:24 +020092 post_log ("Error at andi test %d !\n", i);
Wolfgang Denkb38e0df2007-03-06 18:08:43 +010093 }
94 }
95 }
96
97 if (flag)
Wolfgang Denka1be4762008-05-20 16:00:29 +020098 enable_interrupts();
Wolfgang Denkb38e0df2007-03-06 18:08:43 +010099
100 return ret;
101}
102
103#endif