| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| Simon Glass | 71606de | 2016-03-11 22:07:18 -0700 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (c) 2016 Google, Inc |
| Simon Glass | 71606de | 2016-03-11 22:07:18 -0700 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #ifndef __asm_arch_rcba_h |
| 7 | #define __asm_arch_rcba_h |
| 8 | |
| Simon Glass | 398336e | 2019-02-16 20:25:01 -0700 | [diff] [blame] | 9 | #define ACPIIRQEN 0x31e0 /* 32bit */ |
| 10 | |
| Simon Glass | 71606de | 2016-03-11 22:07:18 -0700 | [diff] [blame] | 11 | #define PMSYNC_CONFIG 0x33c4 /* 32bit */ |
| 12 | #define PMSYNC_CONFIG2 0x33cc /* 32bit */ |
| 13 | |
| 14 | #define DEEP_S3_POL 0x3328 /* 32bit */ |
| 15 | #define DEEP_S3_EN_AC (1 << 0) |
| 16 | #define DEEP_S3_EN_DC (1 << 1) |
| 17 | #define DEEP_S5_POL 0x3330 /* 32bit */ |
| 18 | #define DEEP_S5_EN_AC (1 << 14) |
| 19 | #define DEEP_S5_EN_DC (1 << 15) |
| 20 | #define DEEP_SX_CONFIG 0x3334 /* 32bit */ |
| 21 | #define DEEP_SX_WAKE_PIN_EN (1 << 2) |
| 22 | #define DEEP_SX_ACPRESENT_PD (1 << 1) |
| 23 | #define DEEP_SX_GP27_PIN_EN (1 << 0) |
| 24 | #define PMSYNC_CONFIG 0x33c4 /* 32bit */ |
| 25 | #define PMSYNC_CONFIG2 0x33cc /* 32bit */ |
| 26 | |
| 27 | #define RC 0x3400 /* 32bit */ |
| 28 | #define HPTC 0x3404 /* 32bit */ |
| 29 | #define GCS 0x3410 /* 32bit */ |
| 30 | #define BUC 0x3414 /* 32bit */ |
| 31 | #define PCH_DISABLE_GBE (1 << 5) |
| 32 | #define FD 0x3418 /* 32bit */ |
| 33 | #define FDSW 0x3420 /* 8bit */ |
| 34 | #define DISPBDF 0x3424 /* 16bit */ |
| 35 | #define FD2 0x3428 /* 32bit */ |
| 36 | #define CG 0x341c /* 32bit */ |
| 37 | |
| 38 | /* Function Disable 1 RCBA 0x3418 */ |
| 39 | #define PCH_DISABLE_ALWAYS (1 << 0) |
| 40 | #define PCH_DISABLE_ADSPD (1 << 1) |
| 41 | #define PCH_DISABLE_SATA1 (1 << 2) |
| 42 | #define PCH_DISABLE_SMBUS (1 << 3) |
| 43 | #define PCH_DISABLE_HD_AUDIO (1 << 4) |
| 44 | #define PCH_DISABLE_EHCI2 (1 << 13) |
| 45 | #define PCH_DISABLE_LPC (1 << 14) |
| 46 | #define PCH_DISABLE_EHCI1 (1 << 15) |
| 47 | #define PCH_DISABLE_PCIE(x) (1 << (16 + x)) |
| 48 | #define PCH_DISABLE_THERMAL (1 << 24) |
| 49 | #define PCH_DISABLE_SATA2 (1 << 25) |
| 50 | #define PCH_DISABLE_XHCI (1 << 27) |
| 51 | |
| 52 | /* Function Disable 2 RCBA 0x3428 */ |
| 53 | #define PCH_DISABLE_KT (1 << 4) |
| 54 | #define PCH_DISABLE_IDER (1 << 3) |
| 55 | #define PCH_DISABLE_MEI2 (1 << 2) |
| 56 | #define PCH_DISABLE_MEI1 (1 << 1) |
| 57 | #define PCH_ENABLE_DBDF (1 << 0) |
| 58 | |
| 59 | #endif |