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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Joe Hershberger911c6062011-11-11 15:55:37 -06002
3#ifndef _MPC83XX_GPIO_H_
4#define _MPC83XX_GPIO_H_
5
6/*
7 * The MCP83xx's 1-2 GPIO controllers each with 32 bits.
8 */
Tom Rinid9e6ef52021-05-14 21:34:27 -04009#if defined(CONFIG_ARCH_MPC8313) || defined(CONFIG_ARCH_MPC8308)
Joe Hershberger911c6062011-11-11 15:55:37 -060010#define MPC83XX_GPIO_CTRLRS 1
Holger Brunck5c13bd12022-08-19 16:55:06 +020011#elif defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
Joe Hershberger911c6062011-11-11 15:55:37 -060012#define MPC83XX_GPIO_CTRLRS 2
13#else
14#define MPC83XX_GPIO_CTRLRS 0
15#endif
16
17#define MAX_NUM_GPIOS (32 * MPC83XX_GPIO_CTRLRS)
18
Mario Six5dec9e62019-01-21 09:18:08 +010019struct mpc8xxx_gpio_plat {
20 ulong addr;
21 unsigned long size;
22 uint ngpios;
23};
24
Christophe Leroyd4f79cb2023-02-21 19:31:11 +010025struct qe_gpio_plat {
26 ulong addr;
27 unsigned long size;
28};
29
Mario Six5dec9e62019-01-21 09:18:08 +010030#ifndef DM_GPIO
Joe Hershberger911c6062011-11-11 15:55:37 -060031void mpc83xx_gpio_init_f(void);
32void mpc83xx_gpio_init_r(void);
Mario Six5dec9e62019-01-21 09:18:08 +010033#endif /* DM_GPIO */
Joe Hershberger911c6062011-11-11 15:55:37 -060034
35#endif /* MPC83XX_GPIO_H_ */