blob: 6550e5016328d9163eaf8b2489021fe05a270ac3 [file] [log] [blame]
Ian Campbell6efe3692014-05-05 11:52:26 +01001/*
2 * (C) Copyright 2007-2011
3 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
4 * Tom Cubie <tangliang@allwinnertech.com>
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#ifndef _SUNXI_CPU_H
10#define _SUNXI_CPU_H
11
12#define SUNXI_SRAM_A1_BASE 0x00000000
13#define SUNXI_SRAM_A1_SIZE (16 * 1024) /* 16 kiB */
14
15#define SUNXI_SRAM_A2_BASE 0x00004000 /* 16 kiB */
16#define SUNXI_SRAM_A3_BASE 0x00008000 /* 13 kiB */
17#define SUNXI_SRAM_A4_BASE 0x0000b400 /* 3 kiB */
18#define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */
19#define SUNXI_SRAM_B_BASE 0x00020000 /* 64 kiB (secure) */
20
21#define SUNXI_SRAMC_BASE 0x01c00000
22#define SUNXI_DRAMC_BASE 0x01c01000
23#define SUNXI_DMA_BASE 0x01c02000
24#define SUNXI_NFC_BASE 0x01c03000
25#define SUNXI_TS_BASE 0x01c04000
26#define SUNXI_SPI0_BASE 0x01c05000
27#define SUNXI_SPI1_BASE 0x01c06000
28#define SUNXI_MS_BASE 0x01c07000
29#define SUNXI_TVD_BASE 0x01c08000
30#define SUNXI_CSI0_BASE 0x01c09000
31#define SUNXI_TVE0_BASE 0x01c0a000
32#define SUNXI_EMAC_BASE 0x01c0b000
33#define SUNXI_LCD0_BASE 0x01c0C000
34#define SUNXI_LCD1_BASE 0x01c0d000
35#define SUNXI_VE_BASE 0x01c0e000
36#define SUNXI_MMC0_BASE 0x01c0f000
37#define SUNXI_MMC1_BASE 0x01c10000
38#define SUNXI_MMC2_BASE 0x01c11000
39#define SUNXI_MMC3_BASE 0x01c12000
40#define SUNXI_USB0_BASE 0x01c13000
41#define SUNXI_USB1_BASE 0x01c14000
42#define SUNXI_SS_BASE 0x01c15000
43#define SUNXI_HDMI_BASE 0x01c16000
44#define SUNXI_SPI2_BASE 0x01c17000
45#define SUNXI_SATA_BASE 0x01c18000
46#define SUNXI_PATA_BASE 0x01c19000
47#define SUNXI_ACE_BASE 0x01c1a000
48#define SUNXI_TVE1_BASE 0x01c1b000
49#define SUNXI_USB2_BASE 0x01c1c000
50#define SUNXI_CSI1_BASE 0x01c1d000
51#define SUNXI_TZASC_BASE 0x01c1e000
52#define SUNXI_SPI3_BASE 0x01c1f000
53
54#define SUNXI_CCM_BASE 0x01c20000
55#define SUNXI_INTC_BASE 0x01c20400
56#define SUNXI_PIO_BASE 0x01c20800
57#define SUNXI_TIMER_BASE 0x01c20c00
58#define SUNXI_SPDIF_BASE 0x01c21000
59#define SUNXI_AC97_BASE 0x01c21400
60#define SUNXI_IR0_BASE 0x01c21800
61#define SUNXI_IR1_BASE 0x01c21c00
62
63#define SUNXI_IIS_BASE 0x01c22400
64#define SUNXI_LRADC_BASE 0x01c22800
65#define SUNXI_AD_DA_BASE 0x01c22c00
66#define SUNXI_KEYPAD_BASE 0x01c23000
67#define SUNXI_TZPC_BASE 0x01c23400
68#define SUNXI_SID_BASE 0x01c23800
69#define SUNXI_SJTAG_BASE 0x01c23c00
70
71#define SUNXI_TP_BASE 0x01c25000
72#define SUNXI_PMU_BASE 0x01c25400
Hans de Goede316e29b2014-10-27 23:59:27 +010073#define SUN7I_CPUCFG_BASE 0x01c25c00
Ian Campbell6efe3692014-05-05 11:52:26 +010074
75#define SUNXI_UART0_BASE 0x01c28000
76#define SUNXI_UART1_BASE 0x01c28400
77#define SUNXI_UART2_BASE 0x01c28800
78#define SUNXI_UART3_BASE 0x01c28c00
79#define SUNXI_UART4_BASE 0x01c29000
80#define SUNXI_UART5_BASE 0x01c29400
81#define SUNXI_UART6_BASE 0x01c29800
82#define SUNXI_UART7_BASE 0x01c29c00
83#define SUNXI_PS2_0_BASE 0x01c2a000
84#define SUNXI_PS2_1_BASE 0x01c2a400
85
86#define SUNXI_TWI0_BASE 0x01c2ac00
87#define SUNXI_TWI1_BASE 0x01c2b000
88#define SUNXI_TWI2_BASE 0x01c2b400
89
90#define SUNXI_CAN_BASE 0x01c2bc00
91
92#define SUNXI_SCR_BASE 0x01c2c400
93
94#define SUNXI_GPS_BASE 0x01c30000
95#define SUNXI_MALI400_BASE 0x01c40000
96#define SUNXI_GMAC_BASE 0x01c50000
97
Oliver Schinagl66a231a2014-10-03 20:16:23 +080098#define SUNXI_DRAM_COM_BASE 0x01c62000
Hans de Goede31521222014-10-25 20:27:23 +020099#define SUNXI_DRAM_CTL0_BASE 0x01c63000
100#define SUNXI_DRAM_CTL1_BASE 0x01c64000
101#define SUNXI_DRAM_PHY0_BASE 0x01c65000
102#define SUNXI_DRAM_PHY1_BASE 0x01c66000
Oliver Schinagl66a231a2014-10-03 20:16:23 +0800103
Ian Campbell6efe3692014-05-05 11:52:26 +0100104/* module sram */
105#define SUNXI_SRAM_C_BASE 0x01d00000
106
107#define SUNXI_DE_FE0_BASE 0x01e00000
108#define SUNXI_DE_FE1_BASE 0x01e20000
109#define SUNXI_DE_BE0_BASE 0x01e60000
110#define SUNXI_DE_BE1_BASE 0x01e40000
111#define SUNXI_MP_BASE 0x01e80000
112#define SUNXI_AVG_BASE 0x01ea0000
113
Hans de Goede31521222014-10-25 20:27:23 +0200114#define SUNXI_RTC_BASE 0x01f00000
Oliver Schinagl66a231a2014-10-03 20:16:23 +0800115#define SUNXI_PRCM_BASE 0x01f01400
Hans de Goede316e29b2014-10-27 23:59:27 +0100116#define SUN6I_CPUCFG_BASE 0x01f01c00
Chen-Yu Tsai6ee63882014-10-22 16:47:47 +0800117#define SUNXI_R_UART_BASE 0x01f02800
Oliver Schinagl66a231a2014-10-03 20:16:23 +0800118#define SUNXI_R_PIO_BASE 0x01f02c00
119#define SUNXI_P2WI_BASE 0x01f03400
120
Ian Campbell6efe3692014-05-05 11:52:26 +0100121/* CoreSight Debug Module */
122#define SUNXI_CSDM_BASE 0x3f500000
123
124#define SUNXI_DDRII_DDRIII_BASE 0x40000000 /* 2 GiB */
125
126#define SUNXI_BROM_BASE 0xffff0000 /* 32 kiB */
127
128#define SUNXI_CPU_CFG (SUNXI_TIMER_BASE + 0x13c)
129
130#ifndef __ASSEMBLY__
131void sunxi_board_init(void);
132void sunxi_reset(void);
133#endif /* __ASSEMBLY__ */
134
135#endif /* _CPU_H */