| Jens Scharsig | 9bbaae3 | 2010-02-03 22:47:35 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de) |
| 3 | * |
| 4 | * See file CREDITS for list of people who contributed to this |
| 5 | * project. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; either version 2 of |
| 10 | * the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 20 | * MA 02111-1307 USA |
| 21 | */ |
| 22 | |
| 23 | #ifndef AT91_TC_H |
| 24 | #define AT91_TC_H |
| 25 | |
| 26 | typedef struct at91_tcc { |
| 27 | u32 ccr; /* 0x00 Channel Control Register */ |
| 28 | u32 cmr; /* 0x04 Channel Mode Register */ |
| 29 | u32 reserved1[2]; |
| 30 | u32 cv; /* 0x10 Counter Value */ |
| 31 | u32 ra; /* 0x14 Register A */ |
| 32 | u32 rb; /* 0x18 Register B */ |
| 33 | u32 rc; /* 0x1C Register C */ |
| 34 | u32 sr; /* 0x20 Status Register */ |
| 35 | u32 ier; /* 0x24 Interrupt Enable Register */ |
| 36 | u32 idr; /* 0x28 Interrupt Disable Register */ |
| 37 | u32 imr; /* 0x2C Interrupt Mask Register */ |
| 38 | u32 reserved3[4]; |
| 39 | } __attribute__ ((packed)) at91_tcc_t; |
| 40 | |
| 41 | #define AT91_TC_CCR_CLKEN 0x00000001 |
| 42 | #define AT91_TC_CCR_CLKDIS 0x00000002 |
| 43 | #define AT91_TC_CCR_SWTRG 0x00000004 |
| 44 | |
| 45 | #define AT91_TC_CMR_CPCTRG 0x00004000 |
| 46 | |
| 47 | #define AT91_TC_CMR_TCCLKS_CLOCK1 0x00000000 |
| 48 | #define AT91_TC_CMR_TCCLKS_CLOCK2 0x00000001 |
| 49 | #define AT91_TC_CMR_TCCLKS_CLOCK3 0x00000002 |
| 50 | #define AT91_TC_CMR_TCCLKS_CLOCK4 0x00000003 |
| 51 | #define AT91_TC_CMR_TCCLKS_CLOCK5 0x00000004 |
| 52 | #define AT91_TC_CMR_TCCLKS_XC0 0x00000005 |
| 53 | #define AT91_TC_CMR_TCCLKS_XC1 0x00000006 |
| 54 | #define AT91_TC_CMR_TCCLKS_XC2 0x00000007 |
| 55 | |
| 56 | typedef struct at91_tc { |
| 57 | at91_tcc_t tc[3]; /* 0x00 TC Channel 0-2 */ |
| 58 | u32 bcr; /* 0xC0 TC Block Control Register */ |
| 59 | u32 bmr; /* 0xC4 TC Block Mode Register */ |
| 60 | } __attribute__ ((packed)) at91_tc_t; |
| 61 | |
| 62 | #define AT91_TC_BMR_TC0XC0S_TCLK0 0x00000000 |
| 63 | #define AT91_TC_BMR_TC0XC0S_NONE 0x00000001 |
| 64 | #define AT91_TC_BMR_TC0XC0S_TIOA1 0x00000002 |
| 65 | #define AT91_TC_BMR_TC0XC0S_TIOA2 0x00000003 |
| 66 | |
| 67 | #define AT91_TC_BMR_TC1XC1S_TCLK1 0x00000000 |
| 68 | #define AT91_TC_BMR_TC1XC1S_NONE 0x00000004 |
| 69 | #define AT91_TC_BMR_TC1XC1S_TIOA0 0x00000008 |
| 70 | #define AT91_TC_BMR_TC1XC1S_TIOA2 0x0000000C |
| 71 | |
| 72 | #define AT91_TC_BMR_TC2XC2S_TCLK2 0x00000000 |
| 73 | #define AT91_TC_BMR_TC2XC2S_NONE 0x00000010 |
| 74 | #define AT91_TC_BMR_TC2XC2S_TIOA0 0x00000020 |
| 75 | #define AT91_TC_BMR_TC2XC2S_TIOA1 0x00000030 |
| 76 | |
| 77 | #endif |