Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Shaohui Xie | 085ac1c | 2016-09-07 17:56:14 +0800 | [diff] [blame] | 2 | /* |
| 3 | * Copyright 2016 Freescale Semiconductor, Inc. |
Gaurav Jain | 476c639 | 2022-03-24 11:50:35 +0530 | [diff] [blame] | 4 | * Copyright 2019-2021 NXP |
Shaohui Xie | 085ac1c | 2016-09-07 17:56:14 +0800 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <common.h> |
Tom Rini | 8c70baa | 2021-12-14 13:36:40 -0500 | [diff] [blame] | 8 | #include <clock_legacy.h> |
Shaohui Xie | 085ac1c | 2016-09-07 17:56:14 +0800 | [diff] [blame] | 9 | #include <i2c.h> |
| 10 | #include <fdt_support.h> |
Simon Glass | 0e0ac20 | 2017-04-06 12:47:04 -0600 | [diff] [blame] | 11 | #include <fsl_ddr_sdram.h> |
Simon Glass | 9758973 | 2020-05-10 11:40:02 -0600 | [diff] [blame] | 12 | #include <init.h> |
Simon Glass | 3ba929a | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 13 | #include <asm/global_data.h> |
Shaohui Xie | 085ac1c | 2016-09-07 17:56:14 +0800 | [diff] [blame] | 14 | #include <asm/io.h> |
| 15 | #include <asm/arch/clock.h> |
| 16 | #include <asm/arch/fsl_serdes.h> |
| 17 | #include <asm/arch/fdt.h> |
York Sun | 729f2d1 | 2017-03-06 09:02:34 -0800 | [diff] [blame] | 18 | #include <asm/arch/mmu.h> |
Rajesh Bhagat | 9af0a0b | 2018-11-05 18:02:40 +0000 | [diff] [blame] | 19 | #include <asm/arch/cpu.h> |
Shaohui Xie | 085ac1c | 2016-09-07 17:56:14 +0800 | [diff] [blame] | 20 | #include <asm/arch/soc.h> |
Laurentiu Tudor | 512d13e | 2018-08-09 15:19:46 +0300 | [diff] [blame] | 21 | #include <asm/arch-fsl-layerscape/fsl_icid.h> |
Shaohui Xie | 085ac1c | 2016-09-07 17:56:14 +0800 | [diff] [blame] | 22 | #include <ahci.h> |
| 23 | #include <hwconfig.h> |
| 24 | #include <mmc.h> |
| 25 | #include <scsi.h> |
| 26 | #include <fm_eth.h> |
| 27 | #include <fsl_csu.h> |
| 28 | #include <fsl_esdhc.h> |
| 29 | #include <fsl_ifc.h> |
| 30 | #include <spl.h> |
Stephen Carlson | 6fa0388 | 2021-06-22 16:40:27 -0700 | [diff] [blame] | 31 | #include "../common/i2c_mux.h" |
Shaohui Xie | 085ac1c | 2016-09-07 17:56:14 +0800 | [diff] [blame] | 32 | |
| 33 | #include "../common/vid.h" |
| 34 | #include "../common/qixis.h" |
| 35 | #include "ls1046aqds_qixis.h" |
| 36 | |
| 37 | DECLARE_GLOBAL_DATA_PTR; |
| 38 | |
Rajesh Bhagat | 9af0a0b | 2018-11-05 18:02:40 +0000 | [diff] [blame] | 39 | #ifdef CONFIG_TFABOOT |
| 40 | struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { |
| 41 | { |
| 42 | "nor0", |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 43 | CFG_SYS_NOR0_CSPR, |
| 44 | CFG_SYS_NOR0_CSPR_EXT, |
Tom Rini | 7b577ba | 2022-11-16 13:10:25 -0500 | [diff] [blame] | 45 | CFG_SYS_NOR_AMASK, |
| 46 | CFG_SYS_NOR_CSOR, |
Rajesh Bhagat | 9af0a0b | 2018-11-05 18:02:40 +0000 | [diff] [blame] | 47 | { |
Tom Rini | 7b577ba | 2022-11-16 13:10:25 -0500 | [diff] [blame] | 48 | CFG_SYS_NOR_FTIM0, |
| 49 | CFG_SYS_NOR_FTIM1, |
| 50 | CFG_SYS_NOR_FTIM2, |
| 51 | CFG_SYS_NOR_FTIM3 |
Rajesh Bhagat | 9af0a0b | 2018-11-05 18:02:40 +0000 | [diff] [blame] | 52 | }, |
| 53 | |
| 54 | }, |
| 55 | { |
| 56 | "nor1", |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 57 | CFG_SYS_NOR1_CSPR, |
| 58 | CFG_SYS_NOR1_CSPR_EXT, |
Tom Rini | 7b577ba | 2022-11-16 13:10:25 -0500 | [diff] [blame] | 59 | CFG_SYS_NOR_AMASK, |
| 60 | CFG_SYS_NOR_CSOR, |
Rajesh Bhagat | 9af0a0b | 2018-11-05 18:02:40 +0000 | [diff] [blame] | 61 | { |
Tom Rini | 7b577ba | 2022-11-16 13:10:25 -0500 | [diff] [blame] | 62 | CFG_SYS_NOR_FTIM0, |
| 63 | CFG_SYS_NOR_FTIM1, |
| 64 | CFG_SYS_NOR_FTIM2, |
| 65 | CFG_SYS_NOR_FTIM3 |
Rajesh Bhagat | 9af0a0b | 2018-11-05 18:02:40 +0000 | [diff] [blame] | 66 | }, |
| 67 | }, |
| 68 | { |
| 69 | "nand", |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 70 | CFG_SYS_NAND_CSPR, |
| 71 | CFG_SYS_NAND_CSPR_EXT, |
| 72 | CFG_SYS_NAND_AMASK, |
| 73 | CFG_SYS_NAND_CSOR, |
Rajesh Bhagat | 9af0a0b | 2018-11-05 18:02:40 +0000 | [diff] [blame] | 74 | { |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 75 | CFG_SYS_NAND_FTIM0, |
| 76 | CFG_SYS_NAND_FTIM1, |
| 77 | CFG_SYS_NAND_FTIM2, |
| 78 | CFG_SYS_NAND_FTIM3 |
Rajesh Bhagat | 9af0a0b | 2018-11-05 18:02:40 +0000 | [diff] [blame] | 79 | }, |
| 80 | }, |
| 81 | { |
| 82 | "fpga", |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 83 | CFG_SYS_FPGA_CSPR, |
| 84 | CFG_SYS_FPGA_CSPR_EXT, |
| 85 | CFG_SYS_FPGA_AMASK, |
| 86 | CFG_SYS_FPGA_CSOR, |
Rajesh Bhagat | 9af0a0b | 2018-11-05 18:02:40 +0000 | [diff] [blame] | 87 | { |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 88 | CFG_SYS_FPGA_FTIM0, |
| 89 | CFG_SYS_FPGA_FTIM1, |
| 90 | CFG_SYS_FPGA_FTIM2, |
| 91 | CFG_SYS_FPGA_FTIM3 |
Rajesh Bhagat | 9af0a0b | 2018-11-05 18:02:40 +0000 | [diff] [blame] | 92 | }, |
| 93 | } |
| 94 | }; |
| 95 | |
| 96 | struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { |
| 97 | { |
| 98 | "nand", |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 99 | CFG_SYS_NAND_CSPR, |
| 100 | CFG_SYS_NAND_CSPR_EXT, |
| 101 | CFG_SYS_NAND_AMASK, |
| 102 | CFG_SYS_NAND_CSOR, |
Rajesh Bhagat | 9af0a0b | 2018-11-05 18:02:40 +0000 | [diff] [blame] | 103 | { |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 104 | CFG_SYS_NAND_FTIM0, |
| 105 | CFG_SYS_NAND_FTIM1, |
| 106 | CFG_SYS_NAND_FTIM2, |
| 107 | CFG_SYS_NAND_FTIM3 |
Rajesh Bhagat | 9af0a0b | 2018-11-05 18:02:40 +0000 | [diff] [blame] | 108 | }, |
| 109 | }, |
| 110 | { |
| 111 | "nor0", |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 112 | CFG_SYS_NOR0_CSPR, |
| 113 | CFG_SYS_NOR0_CSPR_EXT, |
Tom Rini | 7b577ba | 2022-11-16 13:10:25 -0500 | [diff] [blame] | 114 | CFG_SYS_NOR_AMASK, |
| 115 | CFG_SYS_NOR_CSOR, |
Rajesh Bhagat | 9af0a0b | 2018-11-05 18:02:40 +0000 | [diff] [blame] | 116 | { |
Tom Rini | 7b577ba | 2022-11-16 13:10:25 -0500 | [diff] [blame] | 117 | CFG_SYS_NOR_FTIM0, |
| 118 | CFG_SYS_NOR_FTIM1, |
| 119 | CFG_SYS_NOR_FTIM2, |
| 120 | CFG_SYS_NOR_FTIM3 |
Rajesh Bhagat | 9af0a0b | 2018-11-05 18:02:40 +0000 | [diff] [blame] | 121 | }, |
| 122 | }, |
| 123 | { |
| 124 | "nor1", |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 125 | CFG_SYS_NOR1_CSPR, |
| 126 | CFG_SYS_NOR1_CSPR_EXT, |
Tom Rini | 7b577ba | 2022-11-16 13:10:25 -0500 | [diff] [blame] | 127 | CFG_SYS_NOR_AMASK, |
| 128 | CFG_SYS_NOR_CSOR, |
Rajesh Bhagat | 9af0a0b | 2018-11-05 18:02:40 +0000 | [diff] [blame] | 129 | { |
Tom Rini | 7b577ba | 2022-11-16 13:10:25 -0500 | [diff] [blame] | 130 | CFG_SYS_NOR_FTIM0, |
| 131 | CFG_SYS_NOR_FTIM1, |
| 132 | CFG_SYS_NOR_FTIM2, |
| 133 | CFG_SYS_NOR_FTIM3 |
Rajesh Bhagat | 9af0a0b | 2018-11-05 18:02:40 +0000 | [diff] [blame] | 134 | }, |
| 135 | }, |
| 136 | { |
| 137 | "fpga", |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 138 | CFG_SYS_FPGA_CSPR, |
| 139 | CFG_SYS_FPGA_CSPR_EXT, |
| 140 | CFG_SYS_FPGA_AMASK, |
| 141 | CFG_SYS_FPGA_CSOR, |
Rajesh Bhagat | 9af0a0b | 2018-11-05 18:02:40 +0000 | [diff] [blame] | 142 | { |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 143 | CFG_SYS_FPGA_FTIM0, |
| 144 | CFG_SYS_FPGA_FTIM1, |
| 145 | CFG_SYS_FPGA_FTIM2, |
| 146 | CFG_SYS_FPGA_FTIM3 |
Rajesh Bhagat | 9af0a0b | 2018-11-05 18:02:40 +0000 | [diff] [blame] | 147 | }, |
| 148 | } |
| 149 | }; |
| 150 | |
| 151 | void ifc_cfg_boot_info(struct ifc_regs_info *regs_info) |
| 152 | { |
| 153 | enum boot_src src = get_boot_src(); |
| 154 | |
| 155 | if (src == BOOT_SOURCE_IFC_NAND) |
| 156 | regs_info->regs = ifc_cfg_nand_boot; |
| 157 | else |
| 158 | regs_info->regs = ifc_cfg_nor_boot; |
| 159 | regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT; |
| 160 | } |
| 161 | |
| 162 | #endif |
| 163 | |
Shaohui Xie | 085ac1c | 2016-09-07 17:56:14 +0800 | [diff] [blame] | 164 | enum { |
| 165 | MUX_TYPE_GPIO, |
| 166 | }; |
| 167 | |
| 168 | int checkboard(void) |
| 169 | { |
Rajesh Bhagat | 9af0a0b | 2018-11-05 18:02:40 +0000 | [diff] [blame] | 170 | #ifdef CONFIG_TFABOOT |
| 171 | enum boot_src src = get_boot_src(); |
| 172 | #endif |
Shaohui Xie | 085ac1c | 2016-09-07 17:56:14 +0800 | [diff] [blame] | 173 | char buf[64]; |
| 174 | #ifndef CONFIG_SD_BOOT |
| 175 | u8 sw; |
| 176 | #endif |
| 177 | |
| 178 | puts("Board: LS1046AQDS, boot from "); |
| 179 | |
Rajesh Bhagat | 9af0a0b | 2018-11-05 18:02:40 +0000 | [diff] [blame] | 180 | #ifdef CONFIG_TFABOOT |
| 181 | if (src == BOOT_SOURCE_SD_MMC) |
| 182 | puts("SD\n"); |
| 183 | else { |
| 184 | #endif |
| 185 | |
Shaohui Xie | 085ac1c | 2016-09-07 17:56:14 +0800 | [diff] [blame] | 186 | #ifdef CONFIG_SD_BOOT |
| 187 | puts("SD\n"); |
| 188 | #else |
| 189 | sw = QIXIS_READ(brdcfg[0]); |
| 190 | sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; |
| 191 | |
| 192 | if (sw < 0x8) |
| 193 | printf("vBank: %d\n", sw); |
| 194 | else if (sw == 0x8) |
| 195 | puts("PromJet\n"); |
| 196 | else if (sw == 0x9) |
| 197 | puts("NAND\n"); |
| 198 | else if (sw == 0xF) |
| 199 | printf("QSPI\n"); |
| 200 | else |
| 201 | printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); |
| 202 | #endif |
| 203 | |
Rajesh Bhagat | 9af0a0b | 2018-11-05 18:02:40 +0000 | [diff] [blame] | 204 | #ifdef CONFIG_TFABOOT |
| 205 | } |
| 206 | #endif |
Shaohui Xie | 085ac1c | 2016-09-07 17:56:14 +0800 | [diff] [blame] | 207 | printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n", |
| 208 | QIXIS_READ(id), QIXIS_READ(arch)); |
| 209 | |
| 210 | printf("FPGA: v%d (%s), build %d\n", |
| 211 | (int)QIXIS_READ(scver), qixis_read_tag(buf), |
| 212 | (int)qixis_read_minor()); |
| 213 | |
| 214 | return 0; |
| 215 | } |
| 216 | |
| 217 | bool if_board_diff_clk(void) |
| 218 | { |
| 219 | u8 diff_conf = QIXIS_READ(brdcfg[11]); |
| 220 | |
| 221 | return diff_conf & 0x40; |
| 222 | } |
| 223 | |
| 224 | unsigned long get_board_sys_clk(void) |
| 225 | { |
| 226 | u8 sysclk_conf = QIXIS_READ(brdcfg[1]); |
| 227 | |
| 228 | switch (sysclk_conf & 0x0f) { |
| 229 | case QIXIS_SYSCLK_64: |
| 230 | return 64000000; |
| 231 | case QIXIS_SYSCLK_83: |
| 232 | return 83333333; |
| 233 | case QIXIS_SYSCLK_100: |
| 234 | return 100000000; |
| 235 | case QIXIS_SYSCLK_125: |
| 236 | return 125000000; |
| 237 | case QIXIS_SYSCLK_133: |
| 238 | return 133333333; |
| 239 | case QIXIS_SYSCLK_150: |
| 240 | return 150000000; |
| 241 | case QIXIS_SYSCLK_160: |
| 242 | return 160000000; |
| 243 | case QIXIS_SYSCLK_166: |
| 244 | return 166666666; |
| 245 | } |
| 246 | |
| 247 | return 66666666; |
| 248 | } |
| 249 | |
| 250 | unsigned long get_board_ddr_clk(void) |
| 251 | { |
| 252 | u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); |
| 253 | |
| 254 | if (if_board_diff_clk()) |
| 255 | return get_board_sys_clk(); |
| 256 | switch ((ddrclk_conf & 0x30) >> 4) { |
| 257 | case QIXIS_DDRCLK_100: |
| 258 | return 100000000; |
| 259 | case QIXIS_DDRCLK_125: |
| 260 | return 125000000; |
| 261 | case QIXIS_DDRCLK_133: |
| 262 | return 133333333; |
| 263 | } |
| 264 | |
| 265 | return 66666666; |
| 266 | } |
| 267 | |
Shaohui Xie | 56007a0 | 2016-10-28 14:24:02 +0800 | [diff] [blame] | 268 | #ifdef CONFIG_LPUART |
| 269 | u32 get_lpuart_clk(void) |
| 270 | { |
| 271 | return gd->bus_clk; |
| 272 | } |
| 273 | #endif |
| 274 | |
Shaohui Xie | 085ac1c | 2016-09-07 17:56:14 +0800 | [diff] [blame] | 275 | int dram_init(void) |
| 276 | { |
| 277 | /* |
| 278 | * When resuming from deep sleep, the I2C channel may not be |
| 279 | * in the default channel. So, switch to the default channel |
| 280 | * before accessing DDR SPD. |
Biwen Li | f0018f5 | 2020-02-05 22:02:17 +0800 | [diff] [blame] | 281 | * |
| 282 | * PCA9547 mount on I2C1 bus |
Shaohui Xie | 085ac1c | 2016-09-07 17:56:14 +0800 | [diff] [blame] | 283 | */ |
Biwen Li | f0018f5 | 2020-02-05 22:02:17 +0800 | [diff] [blame] | 284 | select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); |
Simon Glass | 0e0ac20 | 2017-04-06 12:47:04 -0600 | [diff] [blame] | 285 | fsl_initdram(); |
Rajesh Bhagat | 9af0a0b | 2018-11-05 18:02:40 +0000 | [diff] [blame] | 286 | #if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \ |
| 287 | defined(CONFIG_SPL_BUILD) |
York Sun | 729f2d1 | 2017-03-06 09:02:34 -0800 | [diff] [blame] | 288 | /* This will break-before-make MMU for DDR */ |
| 289 | update_early_mmu_table(); |
| 290 | #endif |
Shaohui Xie | 085ac1c | 2016-09-07 17:56:14 +0800 | [diff] [blame] | 291 | |
| 292 | return 0; |
| 293 | } |
| 294 | |
| 295 | int i2c_multiplexer_select_vid_channel(u8 channel) |
| 296 | { |
Biwen Li | f0018f5 | 2020-02-05 22:02:17 +0800 | [diff] [blame] | 297 | return select_i2c_ch_pca9547(channel, 0); |
Shaohui Xie | 085ac1c | 2016-09-07 17:56:14 +0800 | [diff] [blame] | 298 | } |
| 299 | |
| 300 | int board_early_init_f(void) |
| 301 | { |
Tom Rini | 376b88a | 2022-10-28 20:27:13 -0400 | [diff] [blame] | 302 | u32 __iomem *cntcr = (u32 *)CFG_SYS_FSL_TIMER_ADDR; |
Shaohui Xie | 085ac1c | 2016-09-07 17:56:14 +0800 | [diff] [blame] | 303 | #ifdef CONFIG_HAS_FSL_XHCI_USB |
Tom Rini | 376b88a | 2022-10-28 20:27:13 -0400 | [diff] [blame] | 304 | struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR; |
Shaohui Xie | 085ac1c | 2016-09-07 17:56:14 +0800 | [diff] [blame] | 305 | u32 usb_pwrfault; |
| 306 | #endif |
Shaohui Xie | 56007a0 | 2016-10-28 14:24:02 +0800 | [diff] [blame] | 307 | #ifdef CONFIG_LPUART |
| 308 | u8 uart; |
| 309 | #endif |
Shaohui Xie | 085ac1c | 2016-09-07 17:56:14 +0800 | [diff] [blame] | 310 | |
Biwen Li | ffd5a3c | 2020-07-02 11:13:01 +0800 | [diff] [blame] | 311 | /* |
| 312 | * Enable secure system counter for timer |
| 313 | */ |
| 314 | out_le32(cntcr, 0x1); |
| 315 | |
Tom Rini | 714482a | 2021-08-18 23:12:25 -0400 | [diff] [blame] | 316 | #if defined(CONFIG_SYS_I2C_EARLY_INIT) |
Shaohui Xie | 085ac1c | 2016-09-07 17:56:14 +0800 | [diff] [blame] | 317 | i2c_early_init_f(); |
| 318 | #endif |
| 319 | fsl_lsch2_early_init_f(); |
| 320 | |
| 321 | #ifdef CONFIG_HAS_FSL_XHCI_USB |
| 322 | out_be32(&scfg->rcwpmuxcr0, 0x3333); |
| 323 | out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1); |
| 324 | usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED << |
| 325 | SCFG_USBPWRFAULT_USB3_SHIFT) | |
| 326 | (SCFG_USBPWRFAULT_DEDICATED << |
| 327 | SCFG_USBPWRFAULT_USB2_SHIFT) | |
| 328 | (SCFG_USBPWRFAULT_SHARED << |
| 329 | SCFG_USBPWRFAULT_USB1_SHIFT); |
| 330 | out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); |
| 331 | #endif |
| 332 | |
Shaohui Xie | 56007a0 | 2016-10-28 14:24:02 +0800 | [diff] [blame] | 333 | #ifdef CONFIG_LPUART |
| 334 | /* We use lpuart0 as system console */ |
| 335 | uart = QIXIS_READ(brdcfg[14]); |
| 336 | uart &= ~CFG_UART_MUX_MASK; |
| 337 | uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT; |
| 338 | QIXIS_WRITE(brdcfg[14], uart); |
| 339 | #endif |
| 340 | |
Shaohui Xie | 085ac1c | 2016-09-07 17:56:14 +0800 | [diff] [blame] | 341 | return 0; |
| 342 | } |
| 343 | |
| 344 | #ifdef CONFIG_FSL_DEEP_SLEEP |
| 345 | /* determine if it is a warm boot */ |
| 346 | bool is_warm_boot(void) |
| 347 | { |
| 348 | #define DCFG_CCSR_CRSTSR_WDRFR (1 << 3) |
Tom Rini | 376b88a | 2022-10-28 20:27:13 -0400 | [diff] [blame] | 349 | struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR; |
Shaohui Xie | 085ac1c | 2016-09-07 17:56:14 +0800 | [diff] [blame] | 350 | |
| 351 | if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR) |
| 352 | return 1; |
| 353 | |
| 354 | return 0; |
| 355 | } |
| 356 | #endif |
| 357 | |
| 358 | int config_board_mux(int ctrl_type) |
| 359 | { |
| 360 | u8 reg14; |
| 361 | |
| 362 | reg14 = QIXIS_READ(brdcfg[14]); |
| 363 | |
| 364 | switch (ctrl_type) { |
| 365 | case MUX_TYPE_GPIO: |
| 366 | reg14 = (reg14 & (~0x6)) | 0x2; |
| 367 | break; |
| 368 | default: |
| 369 | puts("Unsupported mux interface type\n"); |
| 370 | return -1; |
| 371 | } |
| 372 | |
| 373 | QIXIS_WRITE(brdcfg[14], reg14); |
| 374 | |
| 375 | return 0; |
| 376 | } |
| 377 | |
| 378 | int config_serdes_mux(void) |
| 379 | { |
| 380 | return 0; |
| 381 | } |
| 382 | |
| 383 | #ifdef CONFIG_MISC_INIT_R |
| 384 | int misc_init_r(void) |
| 385 | { |
| 386 | if (hwconfig("gpio")) |
| 387 | config_board_mux(MUX_TYPE_GPIO); |
| 388 | |
| 389 | return 0; |
| 390 | } |
| 391 | #endif |
| 392 | |
| 393 | int board_init(void) |
| 394 | { |
Biwen Li | f0018f5 | 2020-02-05 22:02:17 +0800 | [diff] [blame] | 395 | select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); |
Shaohui Xie | 085ac1c | 2016-09-07 17:56:14 +0800 | [diff] [blame] | 396 | |
Tom Rini | 376b88a | 2022-10-28 20:27:13 -0400 | [diff] [blame] | 397 | #ifdef CFG_SYS_FSL_SERDES |
Shaohui Xie | 085ac1c | 2016-09-07 17:56:14 +0800 | [diff] [blame] | 398 | config_serdes_mux(); |
| 399 | #endif |
| 400 | |
Shaohui Xie | 085ac1c | 2016-09-07 17:56:14 +0800 | [diff] [blame] | 401 | if (adjust_vdd(0)) |
| 402 | printf("Warning: Adjusting core voltage failed.\n"); |
| 403 | |
Udit Agarwal | 22ec238 | 2019-11-07 16:11:32 +0000 | [diff] [blame] | 404 | #ifdef CONFIG_NXP_ESBC |
Sumit Garg | ca69701 | 2017-03-23 13:48:17 +0530 | [diff] [blame] | 405 | /* |
| 406 | * In case of Secure Boot, the IBR configures the SMMU |
| 407 | * to allow only Secure transactions. |
| 408 | * SMMU must be reset in bypass mode. |
| 409 | * Set the ClientPD bit and Clear the USFCFG Bit |
| 410 | */ |
| 411 | u32 val; |
| 412 | val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); |
| 413 | out_le32(SMMU_SCR0, val); |
| 414 | val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); |
| 415 | out_le32(SMMU_NSCR0, val); |
| 416 | #endif |
| 417 | |
Shaohui Xie | 085ac1c | 2016-09-07 17:56:14 +0800 | [diff] [blame] | 418 | return 0; |
| 419 | } |
| 420 | |
| 421 | #ifdef CONFIG_OF_BOARD_SETUP |
Masahiro Yamada | f7ed78b | 2020-06-26 15:13:33 +0900 | [diff] [blame] | 422 | int ft_board_setup(void *blob, struct bd_info *bd) |
Shaohui Xie | 085ac1c | 2016-09-07 17:56:14 +0800 | [diff] [blame] | 423 | { |
| 424 | u64 base[CONFIG_NR_DRAM_BANKS]; |
| 425 | u64 size[CONFIG_NR_DRAM_BANKS]; |
| 426 | u8 reg; |
| 427 | |
| 428 | /* fixup DT for the two DDR banks */ |
| 429 | base[0] = gd->bd->bi_dram[0].start; |
| 430 | size[0] = gd->bd->bi_dram[0].size; |
| 431 | base[1] = gd->bd->bi_dram[1].start; |
| 432 | size[1] = gd->bd->bi_dram[1].size; |
| 433 | |
| 434 | fdt_fixup_memory_banks(blob, base, size, 2); |
| 435 | ft_cpu_setup(blob, bd); |
| 436 | |
Tom Rini | 7806407 | 2022-08-09 10:16:22 -0400 | [diff] [blame] | 437 | #ifdef CONFIG_FMAN_ENET |
Shaohui Xie | 085ac1c | 2016-09-07 17:56:14 +0800 | [diff] [blame] | 438 | fdt_fixup_board_enet(blob); |
| 439 | #endif |
| 440 | |
Laurentiu Tudor | 512d13e | 2018-08-09 15:19:46 +0300 | [diff] [blame] | 441 | fdt_fixup_icid(blob); |
| 442 | |
Shaohui Xie | 085ac1c | 2016-09-07 17:56:14 +0800 | [diff] [blame] | 443 | reg = QIXIS_READ(brdcfg[0]); |
| 444 | reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; |
| 445 | |
| 446 | /* Disable IFC if QSPI is enabled */ |
| 447 | if (reg == 0xF) |
| 448 | do_fixup_by_compat(blob, "fsl,ifc", |
| 449 | "status", "disabled", 8 + 1, 1); |
| 450 | |
| 451 | return 0; |
| 452 | } |
| 453 | #endif |
| 454 | |
| 455 | u8 flash_read8(void *addr) |
| 456 | { |
| 457 | return __raw_readb(addr + 1); |
| 458 | } |
| 459 | |
| 460 | void flash_write16(u16 val, void *addr) |
| 461 | { |
| 462 | u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); |
| 463 | |
| 464 | __raw_writew(shftval, addr); |
| 465 | } |
| 466 | |
| 467 | u16 flash_read16(void *addr) |
| 468 | { |
| 469 | u16 val = __raw_readw(addr); |
| 470 | |
| 471 | return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); |
| 472 | } |
Rajesh Bhagat | 9af0a0b | 2018-11-05 18:02:40 +0000 | [diff] [blame] | 473 | |
Tom Rini | 0543c43 | 2019-11-18 20:02:08 -0500 | [diff] [blame] | 474 | #if defined(CONFIG_TFABOOT) && defined(CONFIG_ENV_IS_IN_SPI_FLASH) |
Rajesh Bhagat | 9af0a0b | 2018-11-05 18:02:40 +0000 | [diff] [blame] | 475 | void *env_sf_get_env_addr(void) |
| 476 | { |
Tom Rini | 376b88a | 2022-10-28 20:27:13 -0400 | [diff] [blame] | 477 | return (void *)(CFG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET); |
Rajesh Bhagat | 9af0a0b | 2018-11-05 18:02:40 +0000 | [diff] [blame] | 478 | } |
| 479 | #endif |