wdenk | dd7d41f | 2002-09-18 20:04:01 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2001 |
| 3 | * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | /* |
| 25 | * MII Utilities |
| 26 | */ |
| 27 | |
| 28 | #include <common.h> |
| 29 | #include <command.h> |
wdenk | dd7d41f | 2002-09-18 20:04:01 +0000 | [diff] [blame] | 30 | |
| 31 | #if (CONFIG_COMMANDS & CFG_CMD_MII) |
wdenk | e44b911 | 2004-04-18 23:32:11 +0000 | [diff] [blame] | 32 | #include <miiphy.h> |
| 33 | |
wdenk | 61066ec | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 34 | #ifdef CONFIG_TERSE_MII |
wdenk | dd7d41f | 2002-09-18 20:04:01 +0000 | [diff] [blame] | 35 | /* |
| 36 | * Display values from last command. |
| 37 | */ |
| 38 | uint last_op; |
| 39 | uint last_addr; |
| 40 | uint last_data; |
| 41 | uint last_reg; |
| 42 | |
| 43 | /* |
| 44 | * MII read/write |
| 45 | * |
| 46 | * Syntax: |
| 47 | * mii read {addr} {reg} |
| 48 | * mii write {addr} {reg} {data} |
| 49 | */ |
| 50 | |
| 51 | int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) |
| 52 | { |
| 53 | char op; |
| 54 | unsigned char addr, reg; |
| 55 | unsigned short data; |
| 56 | int rcode = 0; |
| 57 | |
wdenk | e65527f | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 58 | #if defined(CONFIG_8xx) || defined(CONFIG_MCF52x2) |
wdenk | dd7d41f | 2002-09-18 20:04:01 +0000 | [diff] [blame] | 59 | mii_init (); |
| 60 | #endif |
| 61 | |
| 62 | /* |
| 63 | * We use the last specified parameters, unless new ones are |
| 64 | * entered. |
| 65 | */ |
| 66 | op = last_op; |
| 67 | addr = last_addr; |
| 68 | data = last_data; |
| 69 | reg = last_reg; |
| 70 | |
| 71 | if ((flag & CMD_FLAG_REPEAT) == 0) { |
| 72 | op = argv[1][0]; |
| 73 | if (argc >= 3) |
| 74 | addr = simple_strtoul (argv[2], NULL, 16); |
| 75 | if (argc >= 4) |
| 76 | reg = simple_strtoul (argv[3], NULL, 16); |
| 77 | if (argc >= 5) |
| 78 | data = simple_strtoul (argv[4], NULL, 16); |
| 79 | } |
| 80 | |
| 81 | /* |
| 82 | * check info/read/write. |
| 83 | */ |
| 84 | if (op == 'i') { |
wdenk | f4cec3f | 2003-12-06 23:20:41 +0000 | [diff] [blame] | 85 | unsigned char j, start, end; |
wdenk | dd7d41f | 2002-09-18 20:04:01 +0000 | [diff] [blame] | 86 | unsigned int oui; |
| 87 | unsigned char model; |
| 88 | unsigned char rev; |
| 89 | |
| 90 | /* |
| 91 | * Look for any and all PHYs. Valid addresses are 0..31. |
| 92 | */ |
wdenk | f4cec3f | 2003-12-06 23:20:41 +0000 | [diff] [blame] | 93 | if (argc >= 3) { |
| 94 | start = addr; end = addr + 1; |
| 95 | } else { |
| 96 | start = 0; end = 32; |
| 97 | } |
| 98 | |
| 99 | for (j = start; j < end; j++) { |
wdenk | dd7d41f | 2002-09-18 20:04:01 +0000 | [diff] [blame] | 100 | if (miiphy_info (j, &oui, &model, &rev) == 0) { |
| 101 | printf ("PHY 0x%02X: " |
| 102 | "OUI = 0x%04X, " |
| 103 | "Model = 0x%02X, " |
| 104 | "Rev = 0x%02X, " |
| 105 | "%3dbaseT, %s\n", |
| 106 | j, oui, model, rev, |
wdenk | ed2ac4b | 2004-03-14 18:23:55 +0000 | [diff] [blame] | 107 | miiphy_speed (j), |
wdenk | dd7d41f | 2002-09-18 20:04:01 +0000 | [diff] [blame] | 108 | miiphy_duplex (j) == FULL ? "FDX" : "HDX"); |
| 109 | } |
| 110 | } |
| 111 | } else if (op == 'r') { |
| 112 | if (miiphy_read (addr, reg, &data) != 0) { |
wdenk | 42c0547 | 2004-03-23 22:14:11 +0000 | [diff] [blame] | 113 | puts ("Error reading from the PHY\n"); |
wdenk | dd7d41f | 2002-09-18 20:04:01 +0000 | [diff] [blame] | 114 | rcode = 1; |
| 115 | } |
| 116 | printf ("%04X\n", data & 0x0000FFFF); |
| 117 | } else if (op == 'w') { |
| 118 | if (miiphy_write (addr, reg, data) != 0) { |
wdenk | 42c0547 | 2004-03-23 22:14:11 +0000 | [diff] [blame] | 119 | puts ("Error writing to the PHY\n"); |
wdenk | dd7d41f | 2002-09-18 20:04:01 +0000 | [diff] [blame] | 120 | rcode = 1; |
| 121 | } |
| 122 | } else { |
| 123 | printf ("Usage:\n%s\n", cmdtp->usage); |
| 124 | return 1; |
| 125 | } |
| 126 | |
| 127 | /* |
| 128 | * Save the parameters for repeats. |
| 129 | */ |
| 130 | last_op = op; |
| 131 | last_addr = addr; |
| 132 | last_data = data; |
wdenk | 5f49575 | 2004-02-26 23:46:20 +0000 | [diff] [blame] | 133 | last_reg = reg; |
wdenk | dd7d41f | 2002-09-18 20:04:01 +0000 | [diff] [blame] | 134 | |
| 135 | return rcode; |
| 136 | } |
| 137 | |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 138 | /***************************************************/ |
| 139 | |
wdenk | f287a24 | 2003-07-01 21:06:45 +0000 | [diff] [blame] | 140 | U_BOOT_CMD( |
| 141 | mii, 5, 1, do_mii, |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 142 | "mii - MII utility commands\n", |
| 143 | "info <addr> - display MII PHY info\n" |
| 144 | "mii read <addr> <reg> - read MII PHY <addr> register <reg>\n" |
| 145 | "mii write <addr> <reg> <data> - write MII PHY <addr> register <reg>\n" |
| 146 | ); |
wdenk | e44b911 | 2004-04-18 23:32:11 +0000 | [diff] [blame] | 147 | |
| 148 | #else /* ! CONFIG_TERSE_MII ================================================= */ |
| 149 | |
wdenk | 61066ec | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 150 | typedef struct _MII_reg_desc_t { |
| 151 | ushort regno; |
| 152 | char * name; |
| 153 | } MII_reg_desc_t; |
| 154 | |
| 155 | MII_reg_desc_t reg_0_5_desc_tbl[] = { |
| 156 | { 0, "PHY control register" }, |
| 157 | { 1, "PHY status register" }, |
| 158 | { 2, "PHY ID 1 register" }, |
| 159 | { 3, "PHY ID 2 register" }, |
| 160 | { 4, "Autonegotiation advertisement register" }, |
| 161 | { 5, "Autonegotiation partner abilities register" }, |
| 162 | }; |
| 163 | |
| 164 | typedef struct _MII_field_desc_t { |
| 165 | ushort hi; |
| 166 | ushort lo; |
| 167 | ushort mask; |
| 168 | char * name; |
| 169 | } MII_field_desc_t; |
| 170 | |
| 171 | MII_field_desc_t reg_0_desc_tbl[] = { |
| 172 | { 15, 15, 0x01, "reset" }, |
| 173 | { 14, 14, 0x01, "loopback" }, |
| 174 | { 13, 6, 0x81, "speed selection" }, /* special */ |
| 175 | { 12, 12, 0x01, "A/N enable" }, |
| 176 | { 11, 11, 0x01, "power-down" }, |
| 177 | { 10, 10, 0x01, "isolate" }, |
| 178 | { 9, 9, 0x01, "restart A/N" }, |
| 179 | { 8, 8, 0x01, "duplex" }, /* special */ |
| 180 | { 7, 7, 0x01, "collision test enable" }, |
| 181 | { 5, 0, 0x3f, "(reserved)" } |
| 182 | }; |
| 183 | |
| 184 | MII_field_desc_t reg_1_desc_tbl[] = { |
| 185 | { 15, 15, 0x01, "100BASE-T4 able" }, |
| 186 | { 14, 14, 0x01, "100BASE-X full duplex able" }, |
| 187 | { 13, 13, 0x01, "100BASE-X half duplex able" }, |
| 188 | { 12, 12, 0x01, "10 Mbps full duplex able" }, |
| 189 | { 11, 11, 0x01, "10 Mbps half duplex able" }, |
| 190 | { 10, 10, 0x01, "100BASE-T2 full duplex able" }, |
| 191 | { 9, 9, 0x01, "100BASE-T2 half duplex able" }, |
| 192 | { 8, 8, 0x01, "extended status" }, |
| 193 | { 7, 7, 0x01, "(reserved)" }, |
| 194 | { 6, 6, 0x01, "MF preamble suppression" }, |
| 195 | { 5, 5, 0x01, "A/N complete" }, |
| 196 | { 4, 4, 0x01, "remote fault" }, |
| 197 | { 3, 3, 0x01, "A/N able" }, |
| 198 | { 2, 2, 0x01, "link status" }, |
| 199 | { 1, 1, 0x01, "jabber detect" }, |
| 200 | { 0, 0, 0x01, "extended capabilities" }, |
| 201 | }; |
| 202 | |
| 203 | MII_field_desc_t reg_2_desc_tbl[] = { |
| 204 | { 15, 0, 0xffff, "OUI portion" }, |
| 205 | }; |
| 206 | |
| 207 | MII_field_desc_t reg_3_desc_tbl[] = { |
| 208 | { 15, 10, 0x3f, "OUI portion" }, |
| 209 | { 9, 4, 0x3f, "manufacturer part number" }, |
| 210 | { 3, 0, 0x0f, "manufacturer rev. number" }, |
| 211 | }; |
| 212 | |
| 213 | MII_field_desc_t reg_4_desc_tbl[] = { |
| 214 | { 15, 15, 0x01, "next page able" }, |
| 215 | { 14, 14, 0x01, "reserved" }, |
| 216 | { 13, 13, 0x01, "remote fault" }, |
| 217 | { 12, 12, 0x01, "reserved" }, |
| 218 | { 11, 11, 0x01, "asymmetric pause" }, |
| 219 | { 10, 10, 0x01, "pause enable" }, |
| 220 | { 9, 9, 0x01, "100BASE-T4 able" }, |
| 221 | { 8, 8, 0x01, "100BASE-TX full duplex able" }, |
| 222 | { 7, 7, 0x01, "100BASE-TX able" }, |
| 223 | { 6, 6, 0x01, "10BASE-T full duplex able" }, |
| 224 | { 5, 5, 0x01, "10BASE-T able" }, |
| 225 | { 4, 0, 0x1f, "xxx to do" }, |
| 226 | }; |
| 227 | |
| 228 | MII_field_desc_t reg_5_desc_tbl[] = { |
| 229 | { 15, 15, 0x01, "next page able" }, |
| 230 | { 14, 14, 0x01, "acknowledge" }, |
| 231 | { 13, 13, 0x01, "remote fault" }, |
| 232 | { 12, 12, 0x01, "(reserved)" }, |
| 233 | { 11, 11, 0x01, "asymmetric pause able" }, |
| 234 | { 10, 10, 0x01, "pause able" }, |
| 235 | { 9, 9, 0x01, "100BASE-T4 able" }, |
| 236 | { 8, 8, 0x01, "100BASE-X full duplex able" }, |
| 237 | { 7, 7, 0x01, "100BASE-TX able" }, |
| 238 | { 6, 6, 0x01, "10BASE-T full duplex able" }, |
| 239 | { 5, 5, 0x01, "10BASE-T able" }, |
| 240 | { 4, 0, 0x1f, "xxx to do" }, |
| 241 | }; |
| 242 | |
| 243 | #define DESC0LEN (sizeof(reg_0_desc_tbl)/sizeof(reg_0_desc_tbl[0])) |
| 244 | #define DESC1LEN (sizeof(reg_1_desc_tbl)/sizeof(reg_1_desc_tbl[0])) |
| 245 | #define DESC2LEN (sizeof(reg_2_desc_tbl)/sizeof(reg_2_desc_tbl[0])) |
| 246 | #define DESC3LEN (sizeof(reg_3_desc_tbl)/sizeof(reg_3_desc_tbl[0])) |
| 247 | #define DESC4LEN (sizeof(reg_4_desc_tbl)/sizeof(reg_4_desc_tbl[0])) |
| 248 | #define DESC5LEN (sizeof(reg_5_desc_tbl)/sizeof(reg_5_desc_tbl[0])) |
| 249 | |
| 250 | typedef struct _MII_field_desc_and_len_t { |
| 251 | MII_field_desc_t * pdesc; |
| 252 | ushort len; |
| 253 | } MII_field_desc_and_len_t; |
| 254 | |
| 255 | MII_field_desc_and_len_t desc_and_len_tbl[] = { |
| 256 | { reg_0_desc_tbl, DESC0LEN }, |
| 257 | { reg_1_desc_tbl, DESC1LEN }, |
| 258 | { reg_2_desc_tbl, DESC2LEN }, |
| 259 | { reg_3_desc_tbl, DESC3LEN }, |
| 260 | { reg_4_desc_tbl, DESC4LEN }, |
| 261 | { reg_5_desc_tbl, DESC5LEN }, |
| 262 | }; |
| 263 | |
| 264 | static void dump_reg( |
| 265 | ushort regval, |
| 266 | MII_reg_desc_t * prd, |
| 267 | MII_field_desc_and_len_t * pdl); |
| 268 | |
| 269 | static int special_field( |
| 270 | ushort regno, |
| 271 | MII_field_desc_t * pdesc, |
| 272 | ushort regval); |
| 273 | |
| 274 | void MII_dump_0_to_5( |
| 275 | ushort regvals[6], |
| 276 | uchar reglo, |
| 277 | uchar reghi) |
| 278 | { |
| 279 | ulong i; |
| 280 | |
| 281 | for (i = 0; i < 6; i++) { |
| 282 | if ((reglo <= i) && (i <= reghi)) |
| 283 | dump_reg(regvals[i], ®_0_5_desc_tbl[i], |
| 284 | &desc_and_len_tbl[i]); |
| 285 | } |
| 286 | } |
| 287 | |
| 288 | static void dump_reg( |
| 289 | ushort regval, |
| 290 | MII_reg_desc_t * prd, |
| 291 | MII_field_desc_and_len_t * pdl) |
| 292 | { |
| 293 | ulong i; |
| 294 | ushort mask_in_place; |
| 295 | MII_field_desc_t * pdesc; |
| 296 | |
| 297 | printf("%u. (%04hx) -- %s --\n", |
| 298 | prd->regno, regval, prd->name); |
| 299 | |
| 300 | for (i = 0; i < pdl->len; i++) { |
| 301 | pdesc = &pdl->pdesc[i]; |
| 302 | |
| 303 | mask_in_place = pdesc->mask << pdesc->lo; |
| 304 | |
| 305 | printf(" (%04hx:%04hx) %u.", |
| 306 | mask_in_place, |
| 307 | regval & mask_in_place, |
| 308 | prd->regno); |
| 309 | |
| 310 | if (special_field(prd->regno, pdesc, regval)) { |
| 311 | } |
| 312 | else { |
| 313 | if (pdesc->hi == pdesc->lo) |
| 314 | printf("%2u ", pdesc->lo); |
| 315 | else |
| 316 | printf("%2u-%2u", pdesc->hi, pdesc->lo); |
| 317 | printf(" = %5u %s", |
| 318 | (regval & mask_in_place) >> pdesc->lo, |
| 319 | pdesc->name); |
| 320 | } |
| 321 | printf("\n"); |
| 322 | |
| 323 | } |
| 324 | printf("\n"); |
| 325 | } |
| 326 | |
| 327 | /* Special fields: |
| 328 | ** 0.6,13 |
| 329 | ** 0.8 |
| 330 | ** 2.15-0 |
| 331 | ** 3.15-0 |
| 332 | ** 4.4-0 |
| 333 | ** 5.4-0 |
| 334 | */ |
| 335 | |
| 336 | static int special_field( |
| 337 | ushort regno, |
| 338 | MII_field_desc_t * pdesc, |
| 339 | ushort regval) |
| 340 | { |
| 341 | if ((regno == 0) && (pdesc->lo == 6)) { |
wdenk | 656140b | 2004-04-25 13:18:40 +0000 | [diff] [blame] | 342 | ushort speed_bits = regval & PHY_BMCR_SPEED_MASK; |
wdenk | 61066ec | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 343 | printf("%2u,%2u = b%u%u speed selection = %s Mbps", |
| 344 | 6, 13, |
| 345 | (regval >> 6) & 1, |
| 346 | (regval >> 13) & 1, |
wdenk | 656140b | 2004-04-25 13:18:40 +0000 | [diff] [blame] | 347 | speed_bits == PHY_BMCR_1000_MBPS ? "1000" : |
| 348 | speed_bits == PHY_BMCR_100_MBPS ? "100" : |
| 349 | speed_bits == PHY_BMCR_10_MBPS ? "10" : |
wdenk | 61066ec | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 350 | "???"); |
| 351 | return 1; |
| 352 | } |
| 353 | |
| 354 | else if ((regno == 0) && (pdesc->lo == 8)) { |
| 355 | printf("%2u = %5u duplex = %s", |
| 356 | pdesc->lo, |
| 357 | (regval >> pdesc->lo) & 1, |
| 358 | ((regval >> pdesc->lo) & 1) ? "full" : "half"); |
| 359 | return 1; |
| 360 | } |
| 361 | |
| 362 | else if ((regno == 4) && (pdesc->lo == 0)) { |
| 363 | ushort sel_bits = (regval >> pdesc->lo) & pdesc->mask; |
| 364 | printf("%2u-%2u = %5u selector = %s", |
| 365 | pdesc->hi, pdesc->lo, sel_bits, |
wdenk | 656140b | 2004-04-25 13:18:40 +0000 | [diff] [blame] | 366 | sel_bits == PHY_ANLPAR_PSB_802_3 ? |
wdenk | 61066ec | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 367 | "IEEE 802.3" : |
wdenk | 656140b | 2004-04-25 13:18:40 +0000 | [diff] [blame] | 368 | sel_bits == PHY_ANLPAR_PSB_802_9 ? |
wdenk | 61066ec | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 369 | "IEEE 802.9 ISLAN-16T" : |
| 370 | "???"); |
| 371 | return 1; |
| 372 | } |
| 373 | |
| 374 | else if ((regno == 5) && (pdesc->lo == 0)) { |
| 375 | ushort sel_bits = (regval >> pdesc->lo) & pdesc->mask; |
| 376 | printf("%2u-%2u = %u selector = %s", |
| 377 | pdesc->hi, pdesc->lo, sel_bits, |
wdenk | 656140b | 2004-04-25 13:18:40 +0000 | [diff] [blame] | 378 | sel_bits == PHY_ANLPAR_PSB_802_3 ? |
wdenk | 61066ec | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 379 | "IEEE 802.3" : |
wdenk | 656140b | 2004-04-25 13:18:40 +0000 | [diff] [blame] | 380 | sel_bits == PHY_ANLPAR_PSB_802_9 ? |
wdenk | 61066ec | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 381 | "IEEE 802.9 ISLAN-16T" : |
| 382 | "???"); |
| 383 | return 1; |
| 384 | } |
| 385 | |
| 386 | return 0; |
| 387 | } |
| 388 | |
| 389 | uint last_op; |
| 390 | uint last_data; |
| 391 | uint last_addr_lo; |
| 392 | uint last_addr_hi; |
| 393 | uint last_reg_lo; |
| 394 | uint last_reg_hi; |
| 395 | |
| 396 | static void extract_range( |
| 397 | char * input, |
| 398 | unsigned char * plo, |
| 399 | unsigned char * phi) |
| 400 | { |
| 401 | char * end; |
| 402 | *plo = simple_strtoul(input, &end, 16); |
| 403 | if (*end == '-') { |
| 404 | end++; |
| 405 | *phi = simple_strtoul(end, NULL, 16); |
| 406 | } |
| 407 | else { |
| 408 | *phi = *plo; |
| 409 | } |
| 410 | } |
| 411 | |
wdenk | 20c98a6 | 2004-04-23 20:32:05 +0000 | [diff] [blame] | 412 | /* ---------------------------------------------------------------- */ |
wdenk | 61066ec | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 413 | int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) |
| 414 | { |
| 415 | char op; |
| 416 | unsigned char addrlo, addrhi, reglo, reghi; |
wdenk | 656140b | 2004-04-25 13:18:40 +0000 | [diff] [blame] | 417 | unsigned char addr = 0, reg = 0; |
wdenk | 61066ec | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 418 | unsigned short data; |
| 419 | int rcode = 0; |
| 420 | |
| 421 | #ifdef CONFIG_8xx |
| 422 | mii_init (); |
| 423 | #endif |
| 424 | |
| 425 | /* |
| 426 | * We use the last specified parameters, unless new ones are |
| 427 | * entered. |
| 428 | */ |
| 429 | op = last_op; |
| 430 | addrlo = last_addr_lo; |
| 431 | addrhi = last_addr_hi; |
| 432 | reglo = last_reg_lo; |
| 433 | reghi = last_reg_hi; |
| 434 | data = last_data; |
| 435 | |
| 436 | if ((flag & CMD_FLAG_REPEAT) == 0) { |
| 437 | op = argv[1][0]; |
| 438 | if (argc >= 3) |
| 439 | extract_range(argv[2], &addrlo, &addrhi); |
| 440 | if (argc >= 4) |
| 441 | extract_range(argv[3], ®lo, ®hi); |
| 442 | if (argc >= 5) |
| 443 | data = simple_strtoul (argv[4], NULL, 16); |
| 444 | } |
| 445 | |
| 446 | /* |
| 447 | * check info/read/write. |
| 448 | */ |
| 449 | if (op == 'i') { |
| 450 | unsigned char j, start, end; |
| 451 | unsigned int oui; |
| 452 | unsigned char model; |
| 453 | unsigned char rev; |
| 454 | |
| 455 | /* |
| 456 | * Look for any and all PHYs. Valid addresses are 0..31. |
| 457 | */ |
| 458 | if (argc >= 3) { |
| 459 | start = addr; end = addr + 1; |
| 460 | } else { |
| 461 | start = 0; end = 32; |
| 462 | } |
| 463 | |
| 464 | for (j = start; j < end; j++) { |
| 465 | if (miiphy_info (j, &oui, &model, &rev) == 0) { |
| 466 | printf("PHY 0x%02X: " |
| 467 | "OUI = 0x%04X, " |
| 468 | "Model = 0x%02X, " |
| 469 | "Rev = 0x%02X, " |
| 470 | "%3dbaseT, %s\n", |
| 471 | j, oui, model, rev, |
| 472 | miiphy_speed (j), |
| 473 | miiphy_duplex (j) == FULL ? "FDX" : "HDX"); |
| 474 | } |
| 475 | } |
| 476 | } else if (op == 'r') { |
| 477 | for (addr = addrlo; addr <= addrhi; addr++) { |
| 478 | for (reg = reglo; reg <= reghi; reg++) { |
| 479 | data = 0xffff; |
| 480 | if (miiphy_read (addr, reg, &data) != 0) { |
| 481 | printf( |
| 482 | "Error reading from the PHY addr=%02x reg=%02x\n", |
| 483 | addr, reg); |
| 484 | rcode = 1; |
| 485 | } |
| 486 | else { |
| 487 | if ((addrlo != addrhi) || (reglo != reghi)) |
| 488 | printf("addr=%02x reg=%02x data=", |
| 489 | (uint)addr, (uint)reg); |
| 490 | printf("%04X\n", data & 0x0000FFFF); |
| 491 | } |
| 492 | } |
| 493 | if ((addrlo != addrhi) && (reglo != reghi)) |
| 494 | printf("\n"); |
| 495 | } |
| 496 | } else if (op == 'w') { |
| 497 | for (addr = addrlo; addr <= addrhi; addr++) { |
| 498 | for (reg = reglo; reg <= reghi; reg++) { |
| 499 | if (miiphy_write (addr, reg, data) != 0) { |
| 500 | printf("Error writing to the PHY addr=%02x reg=%02x\n", |
| 501 | addr, reg); |
| 502 | rcode = 1; |
| 503 | } |
| 504 | } |
| 505 | } |
| 506 | } else if (op == 'd') { |
| 507 | ushort regs[6]; |
| 508 | int ok = 1; |
| 509 | if ((reglo > 5) || (reghi > 5)) { |
| 510 | printf( |
| 511 | "The MII dump command only formats the " |
| 512 | "standard MII registers, 0-5.\n"); |
| 513 | return 1; |
| 514 | } |
| 515 | for (addr = addrlo; addr <= addrhi; addr++) { |
| 516 | for (reg = 0; reg < 6; reg++) { |
| 517 | if (miiphy_read(addr, reg, ®s[reg]) != 0) { |
| 518 | ok = 0; |
| 519 | printf( |
| 520 | "Error reading from the PHY addr=%02x reg=%02x\n", |
| 521 | addr, reg); |
| 522 | rcode = 1; |
| 523 | } |
| 524 | } |
| 525 | if (ok) |
| 526 | MII_dump_0_to_5(regs, reglo, reghi); |
| 527 | printf("\n"); |
| 528 | } |
| 529 | } else { |
| 530 | printf("Usage:\n%s\n", cmdtp->usage); |
| 531 | return 1; |
| 532 | } |
| 533 | |
| 534 | /* |
| 535 | * Save the parameters for repeats. |
| 536 | */ |
| 537 | last_op = op; |
| 538 | last_addr_lo = addrlo; |
| 539 | last_addr_hi = addrhi; |
| 540 | last_reg_lo = reglo; |
| 541 | last_reg_hi = reghi; |
| 542 | last_data = data; |
| 543 | |
| 544 | return rcode; |
| 545 | } |
| 546 | |
| 547 | /***************************************************/ |
| 548 | |
| 549 | U_BOOT_CMD( |
| 550 | mii, 5, 1, do_mii, |
| 551 | "mii - MII utility commands\n", |
Wolfgang Denk | 5582de6 | 2005-08-06 01:13:19 +0200 | [diff] [blame] | 552 | "info <addr> - display MII PHY info\n" |
wdenk | 61066ec | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 553 | "mii read <addr> <reg> - read MII PHY <addr> register <reg>\n" |
| 554 | "mii write <addr> <reg> <data> - write MII PHY <addr> register <reg>\n" |
| 555 | "mii dump <addr> <reg> - pretty-print <addr> <reg> (0-5 only)\n" |
| 556 | "Addr and/or reg may be ranges, e.g. 2-7.\n" |
| 557 | ); |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 558 | |
wdenk | 61066ec | 2004-04-18 22:57:51 +0000 | [diff] [blame] | 559 | #endif /* CONFIG_TERSE_MII */ |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 560 | |
wdenk | dd7d41f | 2002-09-18 20:04:01 +0000 | [diff] [blame] | 561 | #endif /* CFG_CMD_MII */ |