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git01.mediatek.com / filogic / uboot / 311c1f2f990af673b568b80a38f800dc25c717a5 / . / arch / arm / include / asm / arch-imx8ulp / pcc.h
blob: 091d0175ddd062349a931ad94e52d2126d49f182 [file] [log] [blame]
Peng Fan690eea12021-08-07 16:00:45 +0800[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright 2021 NXP
4 */
5
6#ifndef _ASM_ARCH_IMX8ULP_PCC_H
7#define _ASM_ARCH_IMX8ULP_PCC_H
8
9#include <asm/arch/cgc.h>
10
11enum pcc3_entry {
12 DMA1_MP_PCC3_SLOT = 1,
13 DMA1_CH0_PCC3_SLOT = 2,
14 DMA1_CH1_PCC3_SLOT = 3,
15 DMA1_CH2_PCC3_SLOT = 4,
16 DMA1_CH3_PCC3_SLOT = 5,
17 DMA1_CH4_PCC3_SLOT = 6,
18 DMA1_CH5_PCC3_SLOT = 7,
19 DMA1_CH6_PCC3_SLOT = 8,
20 DMA1_CH7_PCC3_SLOT = 9,
21 DMA1_CH8_PCC3_SLOT = 10,
22 DMA1_CH9_PCC3_SLOT = 11,
23 DMA1_CH10_PCC3_SLOT = 12,
24 DMA1_CH11_PCC3_SLOT = 13,
25 DMA1_CH12_PCC3_SLOT = 14,
26 DMA1_CH13_PCC3_SLOT = 15,
27 DMA1_CH14_PCC3_SLOT = 16,
28 DMA1_CH15_PCC3_SLOT = 17,
29 DMA1_CH16_PCC3_SLOT = 18,
30 DMA1_CH17_PCC3_SLOT = 19,
31 DMA1_CH18_PCC3_SLOT = 20,
32 DMA1_CH19_PCC3_SLOT = 21,
33 DMA1_CH20_PCC3_SLOT = 22,
34 DMA1_CH21_PCC3_SLOT = 23,
35 DMA1_CH22_PCC3_SLOT = 24,
36 DMA1_CH23_PCC3_SLOT = 25,
37 DMA1_CH24_PCC3_SLOT = 26,
38 DMA1_CH25_PCC3_SLOT = 27,
39 DMA1_CH26_PCC3_SLOT = 28,
40 DMA1_CH27_PCC3_SLOT = 29,
41 DMA1_CH28_PCC3_SLOT = 30,
42 DMA1_CH29_PCC3_SLOT = 31,
43 DMA1_CH30_PCC3_SLOT = 32,
44 DMA1_CH31_PCC3_SLOT = 33,
45 MU0_B_PCC3_SLOT = 34,
46 MU3_A_PCC3_SLOT = 35,
47 LLWU1_PCC3_SLOT = 38,
48 UPOWER_PCC3_SLOT = 40,
49 WDOG3_PCC3_SLOT = 42,
50 WDOG4_PCC3_SLOT = 43,
51 XRDC_MGR_PCC3_SLOT = 47,
52 SEMA42_1_PCC3_SLOT = 48,
53 ROMCP1_PCC3_SLOT = 49,
54 LPIT1_PCC3_SLOT = 50,
55 TPM4_PCC3_SLOT = 51,
56 TPM5_PCC3_SLOT = 52,
57 FLEXIO1_PCC3_SLOT = 53,
58 I3C2_PCC3_SLOT = 54,
59 LPI2C4_PCC3_SLOT = 55,
60 LPI2C5_PCC3_SLOT = 56,
61 LPUART4_PCC3_SLOT = 57,
62 LPUART5_PCC3_SLOT = 58,
63 LPSPI4_PCC3_SLOT = 59,
64 LPSPI5_PCC3_SLOT = 60,
65};
66
67enum pcc4_entry {
68 FLEXSPI2_PCC4_SLOT = 1,
69 TPM6_PCC4_SLOT = 2,
70 TPM7_PCC4_SLOT = 3,
71 LPI2C6_PCC4_SLOT = 4,
72 LPI2C7_PCC4_SLOT = 5,
73 LPUART6_PCC4_SLOT = 6,
74 LPUART7_PCC4_SLOT = 7,
75 SAI4_PCC4_SLOT = 8,
76 SAI5_PCC4_SLOT = 9,
77 PCTLE_PCC4_SLOT = 10,
78 PCTLF_PCC4_SLOT = 11,
79 SDHC0_PCC4_SLOT = 13,
80 SDHC1_PCC4_SLOT = 14,
81 SDHC2_PCC4_SLOT = 15,
82 USB0_PCC4_SLOT = 16,
83 USBPHY_PCC4_SLOT = 17,
84 USB1_PCC4_SLOT = 18,
85 USB1PHY_PCC4_SLOT = 19,
86 USB_XBAR_PCC4_SLOT = 20,
87 ENET_PCC4_SLOT = 21,
88 SFA1_PCC4_SLOT = 22,
89 RGPIOE_PCC4_SLOT = 30,
90 RGPIOF_PCC4_SLOT = 31,
91};
92
93/* PCC registers */
94#define PCC_PR_OFFSET 31
95#define PCC_PR_MASK (0x1 << PCC_PR_OFFSET)
96#define PCC_CGC_OFFSET 30
97#define PCC_CGC_MASK (0x1 << PCC_CGC_OFFSET)
98#define PCC_INUSE_OFFSET 29
99#define PCC_INUSE_MASK (0x1 << PCC_INUSE_OFFSET)
100#define PCC_PCS_OFFSET 24
101#define PCC_PCS_MASK (0x7 << PCC_PCS_OFFSET)
102#define PCC_FRAC_OFFSET 3
103#define PCC_FRAC_MASK (0x1 << PCC_FRAC_OFFSET)
104#define PCC_PCD_OFFSET 0
105#define PCC_PCD_MASK (0x7 << PCC_PCD_OFFSET)
106
107enum pcc_clksrc_type {
108 CLKSRC_PER_PLAT = 0,
109 CLKSRC_PER_BUS = 1,
110 CLKSRC_NO_PCS = 2,
111};
112
113enum pcc_div_type {
114 PCC_HAS_DIV,
115 PCC_NO_DIV,
116};
117
118enum pcc_rst_b {
119 PCC_HAS_RST_B,
120 PCC_NO_RST_B,
121};
122
123/* This structure keeps info for each pcc slot */
124struct pcc_entry {
125 u32 pcc_base;
126 u32 pcc_slot;
127 enum pcc_clksrc_type clksrc;
128 enum pcc_div_type div;
129 enum pcc_rst_b rst_b;
130};
131
132int pcc_clock_enable(int pcc_controller, int pcc_clk_slot, bool enable);
133int pcc_clock_sel(int pcc_controller, int pcc_clk_slot, enum cgc1_clk src);
134int pcc_clock_div_config(int pcc_controller, int pcc_clk_slot, bool frac, u8 div);
135bool pcc_clock_is_enable(int pcc_controller, int pcc_clk_slot);
136int pcc_clock_get_clksrc(int pcc_controller, int pcc_clk_slot, enum cgc1_clk *src);
137int pcc_reset_peripheral(int pcc_controller, int pcc_clk_slot, bool reset);
138u32 pcc_clock_get_rate(int pcc_controller, int pcc_clk_slot);
139#endif