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git01.mediatek.com / filogic / uboot / 310732a0a885b06a4ab0ee21440e437f08876e12 / . / arch / arm / dts / stm32mp15xx-dhcor-u-boot.dtsi
blob: ef730a83220cca7158a3c399e1c263f087f67afa [file] [log] [blame]
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
2/*
3 * Copyright : STMicroelectronics 2018
4 *
5 * Copyright (C) Linaro Ltd 2019 - All Rights Reserved
6 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Marek Vasut526c9512020-03-31 19:51:36 +0200[diff] [blame]7 * Copyright (C) 2020 Marek Vasut <marex@denx.de>
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]8 */
9
10#include <dt-bindings/clock/stm32mp1-clksrc.h>
Patrick Delaunay48c5e902020-03-06 17:54:41 +0100[diff] [blame]11#include "stm32mp15-u-boot.dtsi"
Marek Vasut272198e2020-04-29 15:08:38 +0200[diff] [blame]12#include "stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi"
13#include "stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi"
14#include "stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi"
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]15
Marek Vasut47b98ba2020-04-22 13:18:11 +0200[diff] [blame]16/ {
17 u-boot,dm-pre-reloc;
18 config {
Marek Vasut39221b52020-04-22 13:18:14 +0200[diff] [blame]19 dh,ddr3-coding-gpios = <&gpiog 0 0>, <&gpiog 1 0>;
Marek Vasut47b98ba2020-04-22 13:18:11 +0200[diff] [blame]20 dh,som-coding-gpios = <&gpioz 7 0>, <&gpiof 3 0>;
21 };
22};
23
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]24&i2c4 {
25 u-boot,dm-pre-reloc;
26};
27
28&i2c4_pins_a {
29 u-boot,dm-pre-reloc;
30 pins {
31 u-boot,dm-pre-reloc;
32 };
33};
34
35&pmic {
36 u-boot,dm-pre-reloc;
37};
38
Marek Vasut526c9512020-03-31 19:51:36 +0200[diff] [blame]39&qspi {
40 u-boot,dm-spl;
41};
42
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]43&rcc {
44 st,clksrc = <
45 CLK_MPU_PLL1P
46 CLK_AXI_PLL2P
47 CLK_MCU_PLL3P
48 CLK_PLL12_HSE
49 CLK_PLL3_HSE
50 CLK_PLL4_HSE
51 CLK_RTC_LSE
52 CLK_MCO1_DISABLED
53 CLK_MCO2_DISABLED
54 >;
55
56 st,clkdiv = <
57 1 /*MPU*/
58 0 /*AXI*/
59 0 /*MCU*/
60 1 /*APB1*/
61 1 /*APB2*/
62 1 /*APB3*/
63 1 /*APB4*/
64 2 /*APB5*/
65 23 /*RTC*/
66 0 /*MCO1*/
67 0 /*MCO2*/
68 >;
69
70 st,pkcs = <
71 CLK_CKPER_HSE
72 CLK_FMC_ACLK
73 CLK_QSPI_ACLK
74 CLK_ETH_DISABLED
75 CLK_SDMMC12_PLL4P
76 CLK_DSI_DSIPLL
77 CLK_STGEN_HSE
78 CLK_USBPHY_HSE
79 CLK_SPI2S1_PLL3Q
80 CLK_SPI2S23_PLL3Q
81 CLK_SPI45_HSI
82 CLK_SPI6_HSI
83 CLK_I2C46_HSI
84 CLK_SDMMC3_PLL4P
85 CLK_USBO_USBPHY
86 CLK_ADC_CKPER
87 CLK_CEC_LSE
88 CLK_I2C12_HSI
89 CLK_I2C35_HSI
90 CLK_UART1_HSI
91 CLK_UART24_HSI
92 CLK_UART35_HSI
93 CLK_UART6_HSI
94 CLK_UART78_HSI
95 CLK_SPDIF_PLL4P
Antonio Borneo84159e82020-01-28 10:11:01 +0100[diff] [blame]96 CLK_FDCAN_PLL4R
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]97 CLK_SAI1_PLL3Q
98 CLK_SAI2_PLL3Q
99 CLK_SAI3_PLL3Q
100 CLK_SAI4_PLL3Q
101 CLK_RNG1_LSI
102 CLK_RNG2_LSI
103 CLK_LPTIM1_PCLK1
104 CLK_LPTIM23_PCLK3
105 CLK_LPTIM45_LSE
106 >;
107
108 /* VCO = 1300.0 MHz => P = 650 (CPU) */
109 pll1: st,pll@0 {
Patrick Delaunayc22caac2020-01-28 10:11:03 +0100[diff] [blame]110 compatible = "st,stm32mp1-pll";
111 reg = <0>;
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]112 cfg = < 2 80 0 0 0 PQR(1,0,0) >;
113 frac = < 0x800 >;
114 u-boot,dm-pre-reloc;
115 };
116
117 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
118 pll2: st,pll@1 {
Patrick Delaunayc22caac2020-01-28 10:11:03 +0100[diff] [blame]119 compatible = "st,stm32mp1-pll";
120 reg = <1>;
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]121 cfg = < 2 65 1 0 0 PQR(1,1,1) >;
122 frac = < 0x1400 >;
123 u-boot,dm-pre-reloc;
124 };
125
126 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
127 pll3: st,pll@2 {
Patrick Delaunayc22caac2020-01-28 10:11:03 +0100[diff] [blame]128 compatible = "st,stm32mp1-pll";
129 reg = <2>;
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]130 cfg = < 1 33 1 16 36 PQR(1,1,1) >;
131 frac = < 0x1a04 >;
132 u-boot,dm-pre-reloc;
133 };
134
Marek Vasut787b17c2020-03-31 19:51:35 +0200[diff] [blame]135 /* VCO = 600.0 MHz => P = 100, Q = 50, R = 100 */
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]136 pll4: st,pll@3 {
Patrick Delaunayc22caac2020-01-28 10:11:03 +0100[diff] [blame]137 compatible = "st,stm32mp1-pll";
138 reg = <3>;
Marek Vasut787b17c2020-03-31 19:51:35 +0200[diff] [blame]139 cfg = < 1 49 5 11 5 PQR(1,1,1) >;
Manivannan Sadhasivamd1564072019-05-02 13:26:44 +0530[diff] [blame]140 u-boot,dm-pre-reloc;
141 };
142};