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git01.mediatek.com / filogic / uboot / 30f17ec05d2fcd653bd7f948dfb1b8fdb11bc4fe / . / arch / arm / include / asm / arch-imx8m / clock.h
blob: 45cfea301851f41fee00b454f2774c1dc629ff56 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Peng Fan88057bc2018-01-10 13:20:22 +0800[diff] [blame]2/*
3 * Copyright 2017 NXP
4 *
5 * Peng Fan <peng.fan@nxp.com>
Peng Fan88057bc2018-01-10 13:20:22 +0800[diff] [blame]6 */
7
8#ifndef _ASM_ARCH_IMX8M_CLOCK_H
9#define _ASM_ARCH_IMX8M_CLOCK_H
10
11#include <linux/bitops.h>
12
13enum pll_clocks {
14 ANATOP_ARM_PLL,
15 ANATOP_GPU_PLL,
16 ANATOP_SYSTEM_PLL1,
17 ANATOP_SYSTEM_PLL2,
18 ANATOP_SYSTEM_PLL3,
19 ANATOP_AUDIO_PLL1,
20 ANATOP_AUDIO_PLL2,
21 ANATOP_VIDEO_PLL1,
22 ANATOP_VIDEO_PLL2,
23 ANATOP_DRAM_PLL,
24};
25
26enum clk_slice_type {
27 CORE_CLOCK_SLICE,
28 BUS_CLOCK_SLICE,
29 IP_CLOCK_SLICE,
30 AHB_CLOCK_SLICE,
31 IPG_CLOCK_SLICE,
32 CORE_SEL_CLOCK_SLICE,
33 DRAM_SEL_CLOCK_SLICE,
34};
35
36enum clk_root_index {
37 MXC_ARM_CLK = 0,
38 ARM_A53_CLK_ROOT = 0,
39 ARM_M4_CLK_ROOT = 1,
40 VPU_A53_CLK_ROOT = 2,
41 GPU_CORE_CLK_ROOT = 3,
42 GPU_SHADER_CLK_ROOT = 4,
43 MAIN_AXI_CLK_ROOT = 16,
44 ENET_AXI_CLK_ROOT = 17,
45 NAND_USDHC_BUS_CLK_ROOT = 18,
46 VPU_BUS_CLK_ROOT = 19,
47 DISPLAY_AXI_CLK_ROOT = 20,
48 DISPLAY_APB_CLK_ROOT = 21,
49 DISPLAY_RTRM_CLK_ROOT = 22,
50 USB_BUS_CLK_ROOT = 23,
51 GPU_AXI_CLK_ROOT = 24,
52 GPU_AHB_CLK_ROOT = 25,
53 NOC_CLK_ROOT = 26,
54 NOC_APB_CLK_ROOT = 27,
55 AHB_CLK_ROOT = 32,
56 IPG_CLK_ROOT = 33,
57 MXC_IPG_CLK = 33,
58 AUDIO_AHB_CLK_ROOT = 34,
59 MIPI_DSI_ESC_RX_CLK_ROOT = 36,
60 DRAM_SEL_CFG = 48,
61 CORE_SEL_CFG = 49,
62 DRAM_ALT_CLK_ROOT = 64,
63 DRAM_APB_CLK_ROOT = 65,
64 VPU_G1_CLK_ROOT = 66,
65 VPU_G2_CLK_ROOT = 67,
66 DISPLAY_DTRC_CLK_ROOT = 68,
67 DISPLAY_DC8000_CLK_ROOT = 69,
68 PCIE1_CTRL_CLK_ROOT = 70,
69 PCIE1_PHY_CLK_ROOT = 71,
70 PCIE1_AUX_CLK_ROOT = 72,
71 DC_PIXEL_CLK_ROOT = 73,
72 LCDIF_PIXEL_CLK_ROOT = 74,
73 SAI1_CLK_ROOT = 75,
74 SAI2_CLK_ROOT = 76,
75 SAI3_CLK_ROOT = 77,
76 SAI4_CLK_ROOT = 78,
77 SAI5_CLK_ROOT = 79,
78 SAI6_CLK_ROOT = 80,
79 SPDIF1_CLK_ROOT = 81,
80 SPDIF2_CLK_ROOT = 82,
81 ENET_REF_CLK_ROOT = 83,
82 ENET_TIMER_CLK_ROOT = 84,
83 ENET_PHY_REF_CLK_ROOT = 85,
84 NAND_CLK_ROOT = 86,
85 QSPI_CLK_ROOT = 87,
86 MXC_ESDHC_CLK = 88,
87 USDHC1_CLK_ROOT = 88,
88 MXC_ESDHC2_CLK = 89,
89 USDHC2_CLK_ROOT = 89,
90 I2C1_CLK_ROOT = 90,
91 MXC_I2C_CLK = 90,
92 I2C2_CLK_ROOT = 91,
93 I2C3_CLK_ROOT = 92,
94 I2C4_CLK_ROOT = 93,
95 UART1_CLK_ROOT = 94,
96 UART2_CLK_ROOT = 95,
97 UART3_CLK_ROOT = 96,
98 UART4_CLK_ROOT = 97,
99 USB_CORE_REF_CLK_ROOT = 98,
100 USB_PHY_REF_CLK_ROOT = 99,
101 GIC_CLK_ROOT = 100,
102 ECSPI1_CLK_ROOT = 101,
103 ECSPI2_CLK_ROOT = 102,
104 PWM1_CLK_ROOT = 103,
105 PWM2_CLK_ROOT = 104,
106 PWM3_CLK_ROOT = 105,
107 PWM4_CLK_ROOT = 106,
108 GPT1_CLK_ROOT = 107,
109 GPT2_CLK_ROOT = 108,
110 GPT3_CLK_ROOT = 109,
111 GPT4_CLK_ROOT = 110,
112 GPT5_CLK_ROOT = 111,
113 GPT6_CLK_ROOT = 112,
114 TRACE_CLK_ROOT = 113,
115 WDOG_CLK_ROOT = 114,
116 WRCLK_CLK_ROOT = 115,
117 IPP_DO_CLKO1 = 116,
118 IPP_DO_CLKO2 = 117,
119 MIPI_DSI_CORE_CLK_ROOT = 118,
120 MIPI_DSI_PHY_REF_CLK_ROOT = 119,
121 MIPI_DSI_DBI_CLK_ROOT = 120,
122 OLD_MIPI_DSI_ESC_CLK_ROOT = 121,
123 MIPI_CSI1_CORE_CLK_ROOT = 122,
124 MIPI_CSI1_PHY_REF_CLK_ROOT = 123,
125 MIPI_CSI1_ESC_CLK_ROOT = 124,
126 MIPI_CSI2_CORE_CLK_ROOT = 125,
127 MIPI_CSI2_PHY_REF_CLK_ROOT = 126,
128 MIPI_CSI2_ESC_CLK_ROOT = 127,
129 PCIE2_CTRL_CLK_ROOT = 128,
130 PCIE2_PHY_CLK_ROOT = 129,
131 PCIE2_AUX_CLK_ROOT = 130,
132 ECSPI3_CLK_ROOT = 131,
133 OLD_MIPI_DSI_ESC_RX_ROOT = 132,
134 DISPLAY_HDMI_CLK_ROOT = 133,
135 CLK_ROOT_MAX,
136};
137
138enum clk_root_src {
139 OSC_25M_CLK,
140 ARM_PLL_CLK,
141 DRAM_PLL1_CLK,
142 VIDEO_PLL2_CLK,
143 VPU_PLL_CLK,
144 GPU_PLL_CLK,
145 SYSTEM_PLL1_800M_CLK,
146 SYSTEM_PLL1_400M_CLK,
147 SYSTEM_PLL1_266M_CLK,
148 SYSTEM_PLL1_200M_CLK,
149 SYSTEM_PLL1_160M_CLK,
150 SYSTEM_PLL1_133M_CLK,
151 SYSTEM_PLL1_100M_CLK,
152 SYSTEM_PLL1_80M_CLK,
153 SYSTEM_PLL1_40M_CLK,
154 SYSTEM_PLL2_1000M_CLK,
155 SYSTEM_PLL2_500M_CLK,
156 SYSTEM_PLL2_333M_CLK,
157 SYSTEM_PLL2_250M_CLK,
158 SYSTEM_PLL2_200M_CLK,
159 SYSTEM_PLL2_166M_CLK,
160 SYSTEM_PLL2_125M_CLK,
161 SYSTEM_PLL2_100M_CLK,
162 SYSTEM_PLL2_50M_CLK,
163 SYSTEM_PLL3_CLK,
164 AUDIO_PLL1_CLK,
165 AUDIO_PLL2_CLK,
166 VIDEO_PLL_CLK,
167 OSC_32K_CLK,
168 EXT_CLK_1,
169 EXT_CLK_2,
170 EXT_CLK_3,
171 EXT_CLK_4,
172 OSC_27M_CLK,
173};
174
175/* CCGR index */
176enum clk_ccgr_index {
177 CCGR_DVFS = 0,
178 CCGR_ANAMIX = 1,
179 CCGR_CPU = 2,
180 CCGR_CSU = 4,
181 CCGR_DRAM1 = 5,
182 CCGR_DRAM2_OBSOLETE = 6,
183 CCGR_ECSPI1 = 7,
184 CCGR_ECSPI2 = 8,
185 CCGR_ECSPI3 = 9,
186 CCGR_ENET1 = 10,
187 CCGR_GPIO1 = 11,
188 CCGR_GPIO2 = 12,
189 CCGR_GPIO3 = 13,
190 CCGR_GPIO4 = 14,
191 CCGR_GPIO5 = 15,
192 CCGR_GPT1 = 16,
193 CCGR_GPT2 = 17,
194 CCGR_GPT3 = 18,
195 CCGR_GPT4 = 19,
196 CCGR_GPT5 = 20,
197 CCGR_GPT6 = 21,
198 CCGR_HS = 22,
199 CCGR_I2C1 = 23,
200 CCGR_I2C2 = 24,
201 CCGR_I2C3 = 25,
202 CCGR_I2C4 = 26,
203 CCGR_IOMUX = 27,
204 CCGR_IOMUX1 = 28,
205 CCGR_IOMUX2 = 29,
206 CCGR_IOMUX3 = 30,
207 CCGR_IOMUX4 = 31,
208 CCGR_M4 = 32,
209 CCGR_MU = 33,
210 CCGR_OCOTP = 34,
211 CCGR_OCRAM = 35,
212 CCGR_OCRAM_S = 36,
213 CCGR_PCIE = 37,
214 CCGR_PERFMON1 = 38,
215 CCGR_PERFMON2 = 39,
216 CCGR_PWM1 = 40,
217 CCGR_PWM2 = 41,
218 CCGR_PWM3 = 42,
219 CCGR_PWM4 = 43,
220 CCGR_QOS = 44,
221 CCGR_DISMIX = 45,
222 CCGR_MEGAMIX = 46,
223 CCGR_QSPI = 47,
224 CCGR_RAWNAND = 48,
225 CCGR_RDC = 49,
226 CCGR_ROM = 50,
227 CCGR_SAI1 = 51,
228 CCGR_SAI2 = 52,
229 CCGR_SAI3 = 53,
230 CCGR_SAI4 = 54,
231 CCGR_SAI5 = 55,
232 CCGR_SAI6 = 56,
233 CCGR_SCTR = 57,
234 CCGR_SDMA1 = 58,
235 CCGR_SDMA2 = 59,
236 CCGR_SEC_DEBUG = 60,
237 CCGR_SEMA1 = 61,
238 CCGR_SEMA2 = 62,
239 CCGR_SIM_DISPLAY = 63,
240 CCGR_SIM_ENET = 64,
241 CCGR_SIM_M = 65,
242 CCGR_SIM_MAIN = 66,
243 CCGR_SIM_S = 67,
244 CCGR_SIM_WAKEUP = 68,
245 CCGR_SIM_USB = 69,
246 CCGR_SIM_VPU = 70,
247 CCGR_SNVS = 71,
248 CCGR_TRACE = 72,
249 CCGR_UART1 = 73,
250 CCGR_UART2 = 74,
251 CCGR_UART3 = 75,
252 CCGR_UART4 = 76,
253 CCGR_USB_CTRL1 = 77,
254 CCGR_USB_CTRL2 = 78,
255 CCGR_USB_PHY1 = 79,
256 CCGR_USB_PHY2 = 80,
257 CCGR_USDHC1 = 81,
258 CCGR_USDHC2 = 82,
259 CCGR_WDOG1 = 83,
260 CCGR_WDOG2 = 84,
261 CCGR_WDOG3 = 85,
262 CCGR_VA53 = 86,
263 CCGR_GPU = 87,
264 CCGR_HEVC = 88,
265 CCGR_AVC = 89,
266 CCGR_VP9 = 90,
267 CCGR_HEVC_INTER = 91,
268 CCGR_GIC = 92,
269 CCGR_DISPLAY = 93,
270 CCGR_HDMI = 94,
271 CCGR_HDMI_PHY = 95,
272 CCGR_XTAL = 96,
273 CCGR_PLL = 97,
274 CCGR_TSENSOR = 98,
275 CCGR_VPU_DEC = 99,
276 CCGR_PCIE2 = 100,
277 CCGR_MIPI_CSI1 = 101,
278 CCGR_MIPI_CSI2 = 102,
279 CCGR_MAX,
280};
281
282/* src index */
283enum clk_src_index {
284 CLK_SRC_CKIL_SYNC_REQ = 0,
285 CLK_SRC_ARM_PLL_EN = 1,
286 CLK_SRC_GPU_PLL_EN = 2,
287 CLK_SRC_VPU_PLL_EN = 3,
288 CLK_SRC_DRAM_PLL_EN = 4,
289 CLK_SRC_SYSTEM_PLL1_EN = 5,
290 CLK_SRC_SYSTEM_PLL2_EN = 6,
291 CLK_SRC_SYSTEM_PLL3_EN = 7,
292 CLK_SRC_AUDIO_PLL1_EN = 8,
293 CLK_SRC_AUDIO_PLL2_EN = 9,
294 CLK_SRC_VIDEO_PLL1_EN = 10,
295 CLK_SRC_VIDEO_PLL2_EN = 11,
296 CLK_SRC_ARM_PLL = 12,
297 CLK_SRC_GPU_PLL = 13,
298 CLK_SRC_VPU_PLL = 14,
299 CLK_SRC_DRAM_PLL = 15,
300 CLK_SRC_SYSTEM_PLL1_800M = 16,
301 CLK_SRC_SYSTEM_PLL1_400M = 17,
302 CLK_SRC_SYSTEM_PLL1_266M = 18,
303 CLK_SRC_SYSTEM_PLL1_200M = 19,
304 CLK_SRC_SYSTEM_PLL1_160M = 20,
305 CLK_SRC_SYSTEM_PLL1_133M = 21,
306 CLK_SRC_SYSTEM_PLL1_100M = 22,
307 CLK_SRC_SYSTEM_PLL1_80M = 23,
308 CLK_SRC_SYSTEM_PLL1_40M = 24,
309 CLK_SRC_SYSTEM_PLL2_1000M = 25,
310 CLK_SRC_SYSTEM_PLL2_500M = 26,
311 CLK_SRC_SYSTEM_PLL2_333M = 27,
312 CLK_SRC_SYSTEM_PLL2_250M = 28,
313 CLK_SRC_SYSTEM_PLL2_200M = 29,
314 CLK_SRC_SYSTEM_PLL2_166M = 30,
315 CLK_SRC_SYSTEM_PLL2_125M = 31,
316 CLK_SRC_SYSTEM_PLL2_100M = 32,
317 CLK_SRC_SYSTEM_PLL2_50M = 33,
318 CLK_SRC_SYSTEM_PLL3 = 34,
319 CLK_SRC_AUDIO_PLL1 = 35,
320 CLK_SRC_AUDIO_PLL2 = 36,
321 CLK_SRC_VIDEO_PLL1 = 37,
322 CLK_SRC_VIDEO_PLL2 = 38,
323 CLK_SRC_OSC_25M = 39,
324 CLK_SRC_OSC_27M = 40,
325};
326
327enum root_pre_div {
328 CLK_ROOT_PRE_DIV1 = 0,
329 CLK_ROOT_PRE_DIV2,
330 CLK_ROOT_PRE_DIV3,
331 CLK_ROOT_PRE_DIV4,
332 CLK_ROOT_PRE_DIV5,
333 CLK_ROOT_PRE_DIV6,
334 CLK_ROOT_PRE_DIV7,
335 CLK_ROOT_PRE_DIV8,
336};
337
338enum root_post_div {
339 CLK_ROOT_POST_DIV1 = 0,
340 CLK_ROOT_POST_DIV2,
341 CLK_ROOT_POST_DIV3,
342 CLK_ROOT_POST_DIV4,
343 CLK_ROOT_POST_DIV5,
344 CLK_ROOT_POST_DIV6,
345 CLK_ROOT_POST_DIV7,
346 CLK_ROOT_POST_DIV8,
347 CLK_ROOT_POST_DIV9,
348 CLK_ROOT_POST_DIV10,
349 CLK_ROOT_POST_DIV11,
350 CLK_ROOT_POST_DIV12,
351 CLK_ROOT_POST_DIV13,
352 CLK_ROOT_POST_DIV14,
353 CLK_ROOT_POST_DIV15,
354 CLK_ROOT_POST_DIV16,
355 CLK_ROOT_POST_DIV17,
356 CLK_ROOT_POST_DIV18,
357 CLK_ROOT_POST_DIV19,
358 CLK_ROOT_POST_DIV20,
359 CLK_ROOT_POST_DIV21,
360 CLK_ROOT_POST_DIV22,
361 CLK_ROOT_POST_DIV23,
362 CLK_ROOT_POST_DIV24,
363 CLK_ROOT_POST_DIV25,
364 CLK_ROOT_POST_DIV26,
365 CLK_ROOT_POST_DIV27,
366 CLK_ROOT_POST_DIV28,
367 CLK_ROOT_POST_DIV29,
368 CLK_ROOT_POST_DIV30,
369 CLK_ROOT_POST_DIV31,
370 CLK_ROOT_POST_DIV32,
371 CLK_ROOT_POST_DIV33,
372 CLK_ROOT_POST_DIV34,
373 CLK_ROOT_POST_DIV35,
374 CLK_ROOT_POST_DIV36,
375 CLK_ROOT_POST_DIV37,
376 CLK_ROOT_POST_DIV38,
377 CLK_ROOT_POST_DIV39,
378 CLK_ROOT_POST_DIV40,
379 CLK_ROOT_POST_DIV41,
380 CLK_ROOT_POST_DIV42,
381 CLK_ROOT_POST_DIV43,
382 CLK_ROOT_POST_DIV44,
383 CLK_ROOT_POST_DIV45,
384 CLK_ROOT_POST_DIV46,
385 CLK_ROOT_POST_DIV47,
386 CLK_ROOT_POST_DIV48,
387 CLK_ROOT_POST_DIV49,
388 CLK_ROOT_POST_DIV50,
389 CLK_ROOT_POST_DIV51,
390 CLK_ROOT_POST_DIV52,
391 CLK_ROOT_POST_DIV53,
392 CLK_ROOT_POST_DIV54,
393 CLK_ROOT_POST_DIV55,
394 CLK_ROOT_POST_DIV56,
395 CLK_ROOT_POST_DIV57,
396 CLK_ROOT_POST_DIV58,
397 CLK_ROOT_POST_DIV59,
398 CLK_ROOT_POST_DIV60,
399 CLK_ROOT_POST_DIV61,
400 CLK_ROOT_POST_DIV62,
401 CLK_ROOT_POST_DIV63,
402 CLK_ROOT_POST_DIV64,
403};
404
405struct clk_root_map {
406 enum clk_root_index entry;
407 enum clk_slice_type slice_type;
408 u32 slice_index;
409 u8 src_mux[8];
410};
411
412struct ccm_ccgr {
413 u32 ccgr;
414 u32 ccgr_set;
415 u32 ccgr_clr;
416 u32 ccgr_tog;
417};
418
419struct ccm_root {
420 u32 target_root;
421 u32 target_root_set;
422 u32 target_root_clr;
423 u32 target_root_tog;
424 u32 misc;
425 u32 misc_set;
426 u32 misc_clr;
427 u32 misc_tog;
428 u32 nm_post;
429 u32 nm_post_root_set;
430 u32 nm_post_root_clr;
431 u32 nm_post_root_tog;
432 u32 nm_pre;
433 u32 nm_pre_root_set;
434 u32 nm_pre_root_clr;
435 u32 nm_pre_root_tog;
436 u32 db_post;
437 u32 db_post_root_set;
438 u32 db_post_root_clr;
439 u32 db_post_root_tog;
440 u32 db_pre;
441 u32 db_pre_root_set;
442 u32 db_pre_root_clr;
443 u32 db_pre_root_tog;
444 u32 reserved[4];
445 u32 access_ctrl;
446 u32 access_ctrl_root_set;
447 u32 access_ctrl_root_clr;
448 u32 access_ctrl_root_tog;
449};
450
451struct ccm_reg {
452 u32 reserved_0[4096];
453 struct ccm_ccgr ccgr_array[192];
454 u32 reserved_1[3328];
455 struct ccm_root core_root[5];
456 u32 reserved_2[352];
457 struct ccm_root bus_root[12];
458 u32 reserved_3[128];
459 struct ccm_root ahb_ipg_root[4];
460 u32 reserved_4[384];
461 struct ccm_root dram_sel;
462 struct ccm_root core_sel;
463 u32 reserved_5[448];
464 struct ccm_root ip_root[78];
465};
466
467#define CCGR_CLK_ON_MASK 0x03
468#define CLK_SRC_ON_MASK 0x03
469
470#define CLK_ROOT_ON BIT(28)
471#define CLK_ROOT_OFF (0 << 28)
472#define CLK_ROOT_ENABLE_MASK BIT(28)
473#define CLK_ROOT_ENABLE_SHIFT 28
474#define CLK_ROOT_SOURCE_SEL(n) (((n) & 0x7) << 24)
475
476/* For SEL, only use 1 bit */
477#define CLK_ROOT_SRC_MUX_MASK 0x07000000
478#define CLK_ROOT_SRC_MUX_SHIFT 24
479#define CLK_ROOT_SRC_0 0x00000000
480#define CLK_ROOT_SRC_1 0x01000000
481#define CLK_ROOT_SRC_2 0x02000000
482#define CLK_ROOT_SRC_3 0x03000000
483#define CLK_ROOT_SRC_4 0x04000000
484#define CLK_ROOT_SRC_5 0x05000000
485#define CLK_ROOT_SRC_6 0x06000000
486#define CLK_ROOT_SRC_7 0x07000000
487
488#define CLK_ROOT_PRE_DIV_MASK (0x00070000)
489#define CLK_ROOT_PRE_DIV_SHIFT 16
490#define CLK_ROOT_PRE_DIV(n) (((n) << 16) & 0x00070000)
491
492#define CLK_ROOT_AUDO_SLOW_EN 0x1000
493
494#define CLK_ROOT_AUDO_DIV_MASK 0x700
495#define CLK_ROOT_AUDO_DIV_SHIFT 0x8
496#define CLK_ROOT_AUDO_DIV(n) (((n) << 8) & 0x700)
497
498/* For CORE: mask is 0x7; For IPG: mask is 0x3 */
499#define CLK_ROOT_POST_DIV_MASK 0x3f
500#define CLK_ROOT_CORE_POST_DIV_MASK 0x7
501#define CLK_ROOT_IPG_POST_DIV_MASK 0x3
502#define CLK_ROOT_POST_DIV_SHIFT 0
503#define CLK_ROOT_POST_DIV(n) ((n) & 0x3f)
504
505/* AUDIO PLL1/2 VIDEO PLL1 GPU PLL VPU PLL ARM PLL*/
506#define FRAC_PLL_LOCK_MASK BIT(31)
507#define FRAC_PLL_CLKE_MASK BIT(21)
508#define FRAC_PLL_PD_MASK BIT(19)
509#define FRAC_PLL_REFCLK_SEL_MASK BIT(16)
510#define FRAC_PLL_LOCK_SEL_MASK BIT(15)
511#define FRAC_PLL_BYPASS_MASK BIT(14)
512#define FRAC_PLL_COUNTCLK_SEL_MASK BIT(13)
513#define FRAC_PLL_NEWDIV_VAL_MASK BIT(12)
514#define FRAC_PLL_NEWDIV_ACK_MASK BIT(11)
515#define FRAC_PLL_REFCLK_DIV_VAL(n) (((n) << 5) & (0x3f << 5))
516#define FRAC_PLL_REFCLK_DIV_VAL_MASK (0x3f << 5)
517#define FRAC_PLL_REFCLK_DIV_VAL_SHIFT 5
518#define FRAC_PLL_OUTPUT_DIV_VAL_MASK 0x1f
519#define FRAC_PLL_OUTPUT_DIV_VAL(n) ((n) & 0x1f)
520
521#define FRAC_PLL_REFCLK_SEL_OSC_25M (0 << 16)
522#define FRAC_PLL_REFCLK_SEL_OSC_27M BIT(16)
523#define FRAC_PLL_REFCLK_SEL_HDMI_PHY_27M (2 << 16)
524#define FRAC_PLL_REFCLK_SEL_CLK_PN (3 << 16)
525
526#define FRAC_PLL_FRAC_DIV_CTL_MASK (0x1ffffff << 7)
527#define FRAC_PLL_FRAC_DIV_CTL_SHIFT 7
528#define FRAC_PLL_INT_DIV_CTL_MASK 0x7f
529#define FRAC_PLL_INT_DIV_CTL_VAL(n) ((n) & 0x7f)
530
531/* SYS PLL1/2/3 VIDEO PLL2 DRAM PLL */
532#define SSCG_PLL_LOCK_MASK BIT(31)
533#define SSCG_PLL_CLKE_MASK BIT(25)
534#define SSCG_PLL_DIV2_CLKE_MASK BIT(23)
535#define SSCG_PLL_DIV3_CLKE_MASK BIT(21)
536#define SSCG_PLL_DIV4_CLKE_MASK BIT(19)
537#define SSCG_PLL_DIV5_CLKE_MASK BIT(17)
538#define SSCG_PLL_DIV6_CLKE_MASK BIT(15)
539#define SSCG_PLL_DIV8_CLKE_MASK BIT(13)
540#define SSCG_PLL_DIV10_CLKE_MASK BIT(11)
541#define SSCG_PLL_DIV20_CLKE_MASK BIT(9)
542#define SSCG_PLL_VIDEO_PLL2_CLKE_MASK BIT(9)
543#define SSCG_PLL_DRAM_PLL_CLKE_MASK BIT(9)
544#define SSCG_PLL_PLL3_CLKE_MASK BIT(9)
545#define SSCG_PLL_PD_MASK BIT(7)
546#define SSCG_PLL_BYPASS1_MASK BIT(5)
547#define SSCG_PLL_BYPASS2_MASK BIT(4)
548#define SSCG_PLL_LOCK_SEL_MASK BIT(3)
549#define SSCG_PLL_COUNTCLK_SEL_MASK BIT(2)
550#define SSCG_PLL_REFCLK_SEL_MASK 0x3
551#define SSCG_PLL_REFCLK_SEL_OSC_25M (0 << 16)
552#define SSCG_PLL_REFCLK_SEL_OSC_27M BIT(16)
553#define SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M (2 << 16)
554#define SSCG_PLL_REFCLK_SEL_CLK_PN (3 << 16)
555
556#define SSCG_PLL_SSDS_MASK BIT(8)
557#define SSCG_PLL_SSMD_MASK (0x7 << 5)
558#define SSCG_PLL_SSMF_MASK (0xf << 1)
559#define SSCG_PLL_SSE_MASK 0x1
560
561#define SSCG_PLL_REF_DIVR1_MASK (0x7 << 25)
562#define SSCG_PLL_REF_DIVR1_SHIFT 25
563#define SSCG_PLL_REF_DIVR1_VAL(n) (((n) << 25) & SSCG_PLL_REF_DIVR1_MASK)
564#define SSCG_PLL_REF_DIVR2_MASK (0x3f << 19)
565#define SSCG_PLL_REF_DIVR2_SHIFT 19
566#define SSCG_PLL_REF_DIVR2_VAL(n) (((n) << 19) & SSCG_PLL_REF_DIVR2_MASK)
567#define SSCG_PLL_FEEDBACK_DIV_F1_MASK (0x3f << 13)
568#define SSCG_PLL_FEEDBACK_DIV_F1_SHIFT 13
569#define SSCG_PLL_FEEDBACK_DIV_F1_VAL(n) (((n) << 13) & \
570 SSCG_PLL_FEEDBACK_DIV_F1_MASK)
571#define SSCG_PLL_FEEDBACK_DIV_F2_MASK (0x3f << 7)
572#define SSCG_PLL_FEEDBACK_DIV_F2_SHIFT 7
573#define SSCG_PLL_FEEDBACK_DIV_F2_VAL(n) (((n) << 7) & \
574 SSCG_PLL_FEEDBACK_DIV_F2_MASK)
575#define SSCG_PLL_OUTPUT_DIV_VAL_MASK (0x3f << 1)
576#define SSCG_PLL_OUTPUT_DIV_VAL_SHIFT 1
577#define SSCG_PLL_OUTPUT_DIV_VAL(n) (((n) << 1) & \
578 SSCG_PLL_OUTPUT_DIV_VAL_MASK)
579#define SSCG_PLL_FILTER_RANGE_MASK 0x1
580
581#define HW_DIGPROG_MAJOR_UPPER_MASK (0xff << 16)
582#define HW_DIGPROG_MAJOR_LOWER_MASK (0xff << 8)
583#define HW_DIGPROG_MINOR_MASK 0xff
584
585#define HW_OSC_27M_CLKE_MASK BIT(4)
586#define HW_OSC_25M_CLKE_MASK BIT(2)
587#define HW_OSC_32K_SEL_MASK 0x1
588#define HW_OSC_32K_SEL_RTC 0x1
589#define HW_OSC_32K_SEL_25M_DIV800 0x0
590
591#define HW_FRAC_ARM_PLL_DIV_MASK (0x7 << 20)
592#define HW_FRAC_ARM_PLL_DIV_SHIFT 20
593#define HW_FRAC_VPU_PLL_DIV_MASK (0x7 << 16)
594#define HW_FRAC_VPU_PLL_DIV_SHIFT 16
595#define HW_FRAC_GPU_PLL_DIV_MASK (0x7 << 12)
596#define HW_FRAC_GPU_PLL_DIV_SHIFT 12
597#define HW_FRAC_VIDEO_PLL1_DIV_MASK (0x7 << 10)
598#define HW_FRAC_VIDEO_PLL1_DIV_SHIFT 10
599#define HW_FRAC_AUDIO_PLL2_DIV_MASK (0x7 << 4)
600#define HW_FRAC_AUDIO_PLL2_DIV_SHIFT 4
601#define HW_FRAC_AUDIO_PLL1_DIV_MASK 0x7
602#define HW_FRAC_AUDIO_PLL1_DIV_SHIFT 0
603
604#define HW_SSCG_VIDEO_PLL2_DIV_MASK (0x7 << 16)
605#define HW_SSCG_VIDEO_PLL2_DIV_SHIFT 16
606#define HW_SSCG_DRAM_PLL_DIV_MASK (0x7 << 14)
607#define HW_SSCG_DRAM_PLL_DIV_SHIFT 14
608#define HW_SSCG_SYSTEM_PLL3_DIV_MASK (0x7 << 8)
609#define HW_SSCG_SYSTEM_PLL3_DIV_SHIFT 8
610#define HW_SSCG_SYSTEM_PLL2_DIV_MASK (0x7 << 4)
611#define HW_SSCG_SYSTEM_PLL2_DIV_SHIFT 4
612#define HW_SSCG_SYSTEM_PLL1_DIV_MASK 0x7
613#define HW_SSCG_SYSTEM_PLL1_DIV_SHIFT 0
614
615#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x01000000
616#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000
617#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x03000000
618#define ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x07000000
619#define ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M 0x01000000
620#define ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000
621#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x01000000
622
623enum enet_freq {
624 ENET_25MHZ = 0,
625 ENET_50MHZ,
626 ENET_125MHZ,
627};
628
629enum frac_pll_out_val {
630 FRAC_PLL_OUT_1000M,
631 FRAC_PLL_OUT_1600M,
632};
633
634u32 imx_get_fecclk(void);
635u32 imx_get_uartclk(void);
636int clock_init(void);
637void init_clk_usdhc(u32 index);
638void init_uart_clk(u32 index);
639void init_wdog_clk(void);
640unsigned int mxc_get_clock(enum clk_root_index clk);
641int clock_enable(enum clk_ccgr_index index, bool enable);
642int clock_root_enabled(enum clk_root_index clock_id);
643int clock_root_cfg(enum clk_root_index clock_id, enum root_pre_div pre_div,
644 enum root_post_div post_div, enum clk_root_src clock_src);
645int clock_set_target_val(enum clk_root_index clock_id, u32 val);
646int clock_get_target_val(enum clk_root_index clock_id, u32 *val);
647int clock_get_prediv(enum clk_root_index clock_id, enum root_pre_div *pre_div);
648int clock_get_postdiv(enum clk_root_index clock_id,
649 enum root_post_div *post_div);
650int clock_get_src(enum clk_root_index clock_id, enum clk_root_src *p_clock_src);
651void mxs_set_lcdclk(u32 base_addr, u32 freq);
652int set_clk_qspi(void);
653void enable_ocotp_clk(unsigned char enable);
654int enable_i2c_clk(unsigned char enable, unsigned int i2c_num);
655int set_clk_enet(enum enet_freq type);
656#endif