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git01.mediatek.com / filogic / uboot / 30e64b97797f930a92c5a6f1028a2cd866f0e6e6 / . / dts / upstream / Bindings / net / renesas,ethertsn.yaml
blob: b4680a1d0a068ed6c5d128c503ee5c2da9dfa476 [file] [log] [blame]
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/renesas,ethertsn.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas Ethernet TSN End-station
8
9maintainers:
10 - Niklas Söderlund <niklas.soderlund@ragnatech.se>
11
12description:
13 The RTSN device provides Ethernet network using a 10 Mbps, 100 Mbps, or 1
14 Gbps full-duplex link via MII/GMII/RMII/RGMII. Depending on the connected PHY.
15
16allOf:
17 - $ref: ethernet-controller.yaml#
18
19properties:
20 compatible:
21 items:
22 - enum:
23 - renesas,r8a779g0-ethertsn # R-Car V4H
24 - const: renesas,rcar-gen4-ethertsn
25
26 reg:
27 items:
28 - description: TSN End Station target
29 - description: generalized Precision Time Protocol target
30
31 reg-names:
32 items:
33 - const: tsnes
34 - const: gptp
35
36 interrupts:
37 items:
38 - description: TX data interrupt
39 - description: RX data interrupt
40
41 interrupt-names:
42 items:
43 - const: tx
44 - const: rx
45
46 clocks:
47 maxItems: 1
48
49 power-domains:
50 maxItems: 1
51
52 resets:
53 maxItems: 1
54
55 phy-mode:
56 contains:
57 enum:
58 - mii
59 - rgmii
60
61 phy-handle:
62 $ref: /schemas/types.yaml#/definitions/phandle
63 description:
64 Specifies a reference to a node representing a PHY device.
65
66 rx-internal-delay-ps:
67 enum: [0, 1800]
68 default: 0
69
70 tx-internal-delay-ps:
71 enum: [0, 2000]
72 default: 0
73
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]74 mdio:
75 $ref: /schemas/net/mdio.yaml#
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]76 unevaluatedProperties: false
77
78required:
79 - compatible
80 - reg
81 - reg-names
82 - interrupts
83 - interrupt-names
84 - clocks
85 - power-domains
86 - resets
87 - phy-mode
88 - phy-handle
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]89 - mdio
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]90
91additionalProperties: false
92
93examples:
94 - |
95 #include <dt-bindings/clock/r8a779g0-cpg-mssr.h>
96 #include <dt-bindings/interrupt-controller/arm-gic.h>
97 #include <dt-bindings/power/r8a779g0-sysc.h>
98 #include <dt-bindings/gpio/gpio.h>
99
100 tsn0: ethernet@e6460000 {
101 compatible = "renesas,r8a779g0-ethertsn", "renesas,rcar-gen4-ethertsn";
102 reg = <0xe6460000 0x7000>,
103 <0xe6449000 0x500>;
104 reg-names = "tsnes", "gptp";
105 interrupts = <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
106 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
107 interrupt-names = "tx", "rx";
108 clocks = <&cpg CPG_MOD 2723>;
109 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
110 resets = <&cpg 2723>;
111
112 phy-mode = "rgmii";
113 tx-internal-delay-ps = <2000>;
114 phy-handle = <&phy3>;
115
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]116 mdio {
117 #address-cells = <1>;
118 #size-cells = <0>;
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]119
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]120 reset-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]121 reset-post-delay-us = <4000>;
122
123 phy3: ethernet-phy@0 {
124 compatible = "ethernet-phy-ieee802.3-c45";
125 reg = <0>;
126 interrupt-parent = <&gpio4>;
127 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
128 };
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]129 };
130 };