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git01.mediatek.com / filogic / uboot / 30d19660ba47c9f49ee4bd158ba9496cf4ce9af0 / . / board / nvidia / cardhu / pinmux-config-cardhu.h
blob: 255e4cd82bd55543f7647568b5eb06af2cc213a2 [file] [log] [blame]
Tom Warren23d7fe92012-12-11 13:34:18 +0000[diff] [blame]1/*
Tom Warren7110b952013-03-06 16:16:22 -0700[diff] [blame]2 * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
Tom Warren23d7fe92012-12-11 13:34:18 +0000[diff] [blame]3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#ifndef _PINMUX_CONFIG_CARDHU_H_
18#define _PINMUX_CONFIG_CARDHU_H_
19
Stephen Warrenf4df6052014-03-21 12:28:56 -0600[diff] [blame]20#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \
Tom Warren23d7fe92012-12-11 13:34:18 +0000[diff] [blame]21 { \
Stephen Warren43eed912014-03-21 12:28:59 -0600[diff] [blame]22 .pingrp = PMUX_PINGRP_##_pingrp, \
Tom Warren23d7fe92012-12-11 13:34:18 +0000[diff] [blame]23 .func = PMUX_FUNC_##_mux, \
24 .pull = PMUX_PULL_##_pull, \
25 .tristate = PMUX_TRI_##_tri, \
26 .io = PMUX_PIN_##_io, \
27 .lock = PMUX_PIN_LOCK_DEFAULT, \
28 .od = PMUX_PIN_OD_DEFAULT, \
29 .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
30 }
31
Stephen Warrenf4df6052014-03-21 12:28:56 -0600[diff] [blame]32#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \
Tom Warren23d7fe92012-12-11 13:34:18 +0000[diff] [blame]33 { \
Stephen Warren43eed912014-03-21 12:28:59 -0600[diff] [blame]34 .pingrp = PMUX_PINGRP_##_pingrp, \
Tom Warren23d7fe92012-12-11 13:34:18 +0000[diff] [blame]35 .func = PMUX_FUNC_##_mux, \
36 .pull = PMUX_PULL_##_pull, \
37 .tristate = PMUX_TRI_##_tri, \
38 .io = PMUX_PIN_##_io, \
39 .lock = PMUX_PIN_LOCK_##_lock, \
40 .od = PMUX_PIN_OD_##_od, \
41 .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
42 }
43
Stephen Warrenf4df6052014-03-21 12:28:56 -0600[diff] [blame]44#define LV_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \
Tom Warren23d7fe92012-12-11 13:34:18 +0000[diff] [blame]45 { \
Stephen Warren43eed912014-03-21 12:28:59 -0600[diff] [blame]46 .pingrp = PMUX_PINGRP_##_pingrp, \
Tom Warren23d7fe92012-12-11 13:34:18 +0000[diff] [blame]47 .func = PMUX_FUNC_##_mux, \
48 .pull = PMUX_PULL_##_pull, \
49 .tristate = PMUX_TRI_##_tri, \
50 .io = PMUX_PIN_##_io, \
51 .lock = PMUX_PIN_LOCK_##_lock, \
52 .od = PMUX_PIN_OD_DEFAULT, \
53 .ioreset = PMUX_PIN_IO_RESET_##_ioreset \
54 }
55
Stephen Warrenf4df6052014-03-21 12:28:56 -0600[diff] [blame]56#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
Tom Warren7110b952013-03-06 16:16:22 -0700[diff] [blame]57 { \
Stephen Warren43eed912014-03-21 12:28:59 -0600[diff] [blame]58 .drvgrp = PMUX_DRVGRP_##_drvgrp, \
Tom Warren7110b952013-03-06 16:16:22 -0700[diff] [blame]59 .slwf = _slwf, \
60 .slwr = _slwr, \
61 .drvup = _drvup, \
62 .drvdn = _drvdn, \
Stephen Warrenf4df6052014-03-21 12:28:56 -0600[diff] [blame]63 .lpmd = PMUX_LPMD_##_lpmd, \
64 .schmt = PMUX_SCHMT_##_schmt, \
65 .hsm = PMUX_HSM_##_hsm, \
Tom Warren7110b952013-03-06 16:16:22 -0700[diff] [blame]66 }
67
Stephen Warrenf4df6052014-03-21 12:28:56 -0600[diff] [blame]68static struct pmux_pingrp_config tegra3_pinmux_common[] = {
Tom Warren23d7fe92012-12-11 13:34:18 +0000[diff] [blame]69 /* SDMMC1 pinmux */
Stephen Warren43eed912014-03-21 12:28:59 -0600[diff] [blame]70 DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT),
71 DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT),
72 DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT),
73 DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT),
74 DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT),
75 DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT),
Tom Warren23d7fe92012-12-11 13:34:18 +0000[diff] [blame]76
77 /* SDMMC3 pinmux */
Stephen Warren43eed912014-03-21 12:28:59 -0600[diff] [blame]78 DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT),
79 DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT),
80 DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT),
81 DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT),
82 DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT),
83 DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT),
84 DEFAULT_PINMUX(SDMMC3_DAT6_PD3, RSVD1, NORMAL, NORMAL, INPUT),
85 DEFAULT_PINMUX(SDMMC3_DAT7_PD4, RSVD1, NORMAL, NORMAL, INPUT),
Tom Warren23d7fe92012-12-11 13:34:18 +0000[diff] [blame]86
87 /* SDMMC4 pinmux */
Stephen Warren43eed912014-03-21 12:28:59 -0600[diff] [blame]88 LV_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
89 LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
90 LV_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
91 LV_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
92 LV_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
93 LV_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
94 LV_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
95 LV_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
96 LV_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
97 LV_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
98 LV_PINMUX(SDMMC4_RST_N_PCC3, RSVD1, DOWN, NORMAL, INPUT, DISABLE, DISABLE),
Tom Warren23d7fe92012-12-11 13:34:18 +0000[diff] [blame]99
100 /* I2C1 pinmux */
Stephen Warren43eed912014-03-21 12:28:59 -0600[diff] [blame]101 I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
102 I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
Tom Warren23d7fe92012-12-11 13:34:18 +0000[diff] [blame]103
104 /* I2C2 pinmux */
Stephen Warren43eed912014-03-21 12:28:59 -0600[diff] [blame]105 I2C_PINMUX(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
106 I2C_PINMUX(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
Tom Warren23d7fe92012-12-11 13:34:18 +0000[diff] [blame]107
108 /* I2C3 pinmux */
Stephen Warren43eed912014-03-21 12:28:59 -0600[diff] [blame]109 I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
110 I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
Tom Warren23d7fe92012-12-11 13:34:18 +0000[diff] [blame]111
112 /* I2C4 pinmux */
Stephen Warren43eed912014-03-21 12:28:59 -0600[diff] [blame]113 I2C_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
114 I2C_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
Tom Warren23d7fe92012-12-11 13:34:18 +0000[diff] [blame]115
116 /* Power I2C pinmux */
Stephen Warren43eed912014-03-21 12:28:59 -0600[diff] [blame]117 I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
118 I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
Tom Warren23d7fe92012-12-11 13:34:18 +0000[diff] [blame]119
Stephen Warren43eed912014-03-21 12:28:59 -0600[diff] [blame]120 DEFAULT_PINMUX(ULPI_DATA0_PO1, UARTA, NORMAL, NORMAL, OUTPUT),
121 DEFAULT_PINMUX(ULPI_DATA1_PO2, UARTA, NORMAL, NORMAL, INPUT),
122 DEFAULT_PINMUX(ULPI_DATA2_PO3, UARTA, NORMAL, NORMAL, INPUT),
123 DEFAULT_PINMUX(ULPI_DATA3_PO4, RSVD1, NORMAL, NORMAL, INPUT),
124 DEFAULT_PINMUX(ULPI_DATA4_PO5, UARTA, NORMAL, NORMAL, INPUT),
125 DEFAULT_PINMUX(ULPI_DATA5_PO6, UARTA, NORMAL, NORMAL, INPUT),
126 DEFAULT_PINMUX(ULPI_DATA6_PO7, UARTA, NORMAL, NORMAL, INPUT),
127 DEFAULT_PINMUX(ULPI_DATA7_PO0, UARTA, NORMAL, NORMAL, OUTPUT),
128 DEFAULT_PINMUX(ULPI_CLK_PY0, UARTD, NORMAL, NORMAL, OUTPUT),
129 DEFAULT_PINMUX(ULPI_DIR_PY1, UARTD, NORMAL, NORMAL, INPUT),
130 DEFAULT_PINMUX(ULPI_NXT_PY2, UARTD, NORMAL, NORMAL, INPUT),
131 DEFAULT_PINMUX(ULPI_STP_PY3, UARTD, NORMAL, NORMAL, OUTPUT),
132 DEFAULT_PINMUX(DAP3_FS_PP0, I2S2, NORMAL, NORMAL, INPUT),
133 DEFAULT_PINMUX(DAP3_DIN_PP1, I2S2, NORMAL, NORMAL, INPUT),
134 DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, NORMAL, NORMAL, INPUT),
135 DEFAULT_PINMUX(DAP3_SCLK_PP3, I2S2, NORMAL, NORMAL, INPUT),
136 DEFAULT_PINMUX(PV2, OWR, NORMAL, NORMAL, OUTPUT),
137 DEFAULT_PINMUX(PV3, RSVD1, NORMAL, NORMAL, OUTPUT),
138 DEFAULT_PINMUX(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, INPUT),
139 DEFAULT_PINMUX(CLK2_REQ_PCC5, DAP, NORMAL, NORMAL, INPUT),
140 DEFAULT_PINMUX(LCD_PWR1_PC1, DISPLAYA, NORMAL, NORMAL, INPUT),
141 DEFAULT_PINMUX(LCD_PWR2_PC6, DISPLAYA, NORMAL, NORMAL, INPUT),
142 DEFAULT_PINMUX(LCD_SDIN_PZ2, DISPLAYA, NORMAL, NORMAL, INPUT),
143 DEFAULT_PINMUX(LCD_SDOUT_PN5, DISPLAYA, NORMAL, NORMAL, INPUT),
144 DEFAULT_PINMUX(LCD_WR_N_PZ3, DISPLAYA, NORMAL, NORMAL, INPUT),
145 DEFAULT_PINMUX(LCD_CS0_N_PN4, DISPLAYA, NORMAL, NORMAL, INPUT),
146 DEFAULT_PINMUX(LCD_DC0_PN6, DISPLAYA, NORMAL, NORMAL, INPUT),
147 DEFAULT_PINMUX(LCD_SCK_PZ4, DISPLAYA, NORMAL, NORMAL, INPUT),
148 DEFAULT_PINMUX(LCD_PWR0_PB2, DISPLAYA, NORMAL, NORMAL, INPUT),
149 DEFAULT_PINMUX(LCD_PCLK_PB3, DISPLAYA, NORMAL, NORMAL, INPUT),
150 DEFAULT_PINMUX(LCD_DE_PJ1, DISPLAYA, NORMAL, NORMAL, INPUT),
151 DEFAULT_PINMUX(LCD_HSYNC_PJ3, DISPLAYA, NORMAL, NORMAL, INPUT),
152 DEFAULT_PINMUX(LCD_VSYNC_PJ4, DISPLAYA, NORMAL, NORMAL, INPUT),
153 DEFAULT_PINMUX(LCD_D0_PE0, DISPLAYA, NORMAL, NORMAL, INPUT),
154 DEFAULT_PINMUX(LCD_D1_PE1, DISPLAYA, NORMAL, NORMAL, INPUT),
155 DEFAULT_PINMUX(LCD_D2_PE2, DISPLAYA, NORMAL, NORMAL, INPUT),
156 DEFAULT_PINMUX(LCD_D3_PE3, DISPLAYA, NORMAL, NORMAL, INPUT),
157 DEFAULT_PINMUX(LCD_D4_PE4, DISPLAYA, NORMAL, NORMAL, INPUT),
158 DEFAULT_PINMUX(LCD_D5_PE5, DISPLAYA, NORMAL, NORMAL, INPUT),
159 DEFAULT_PINMUX(LCD_D6_PE6, DISPLAYA, NORMAL, NORMAL, INPUT),
160 DEFAULT_PINMUX(LCD_D7_PE7, DISPLAYA, NORMAL, NORMAL, INPUT),
161 DEFAULT_PINMUX(LCD_D8_PF0, DISPLAYA, NORMAL, NORMAL, INPUT),
162 DEFAULT_PINMUX(LCD_D9_PF1, DISPLAYA, NORMAL, NORMAL, INPUT),
163 DEFAULT_PINMUX(LCD_D10_PF2, DISPLAYA, NORMAL, NORMAL, INPUT),
164 DEFAULT_PINMUX(LCD_D11_PF3, DISPLAYA, NORMAL, NORMAL, INPUT),
165 DEFAULT_PINMUX(LCD_D12_PF4, DISPLAYA, NORMAL, NORMAL, INPUT),
166 DEFAULT_PINMUX(LCD_D13_PF5, DISPLAYA, NORMAL, NORMAL, INPUT),
167 DEFAULT_PINMUX(LCD_D14_PF6, DISPLAYA, NORMAL, NORMAL, INPUT),
168 DEFAULT_PINMUX(LCD_D15_PF7, DISPLAYA, NORMAL, NORMAL, INPUT),
169 DEFAULT_PINMUX(LCD_D16_PM0, DISPLAYA, NORMAL, NORMAL, INPUT),
170 DEFAULT_PINMUX(LCD_D17_PM1, DISPLAYA, NORMAL, NORMAL, INPUT),
171 DEFAULT_PINMUX(LCD_D18_PM2, DISPLAYA, NORMAL, NORMAL, INPUT),
172 DEFAULT_PINMUX(LCD_D19_PM3, DISPLAYA, NORMAL, NORMAL, INPUT),
173 DEFAULT_PINMUX(LCD_D20_PM4, DISPLAYA, NORMAL, NORMAL, INPUT),
174 DEFAULT_PINMUX(LCD_D21_PM5, DISPLAYA, NORMAL, NORMAL, INPUT),
175 DEFAULT_PINMUX(LCD_D22_PM6, DISPLAYA, NORMAL, NORMAL, INPUT),
176 DEFAULT_PINMUX(LCD_D23_PM7, DISPLAYA, NORMAL, NORMAL, INPUT),
177 DEFAULT_PINMUX(LCD_CS1_N_PW0, DISPLAYA, NORMAL, NORMAL, INPUT),
178 DEFAULT_PINMUX(LCD_M1_PW1, DISPLAYA, NORMAL, NORMAL, INPUT),
179 DEFAULT_PINMUX(LCD_DC1_PD2, DISPLAYA, NORMAL, NORMAL, INPUT),
180 DEFAULT_PINMUX(CRT_HSYNC_PV6, CRT, NORMAL, NORMAL, OUTPUT),
181 DEFAULT_PINMUX(CRT_VSYNC_PV7, CRT, NORMAL, NORMAL, OUTPUT),
182 LV_PINMUX(VI_D0_PT4, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
183 LV_PINMUX(VI_D1_PD5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
184 LV_PINMUX(VI_D2_PL0, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
185 LV_PINMUX(VI_D3_PL1, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
186 LV_PINMUX(VI_D4_PL2, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
187 LV_PINMUX(VI_D5_PL3, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
188 LV_PINMUX(VI_D7_PL5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
189 LV_PINMUX(VI_D10_PT2, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
190 LV_PINMUX(VI_MCLK_PT1, VI, UP, NORMAL, INPUT, DISABLE, DISABLE),
191 DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, NORMAL, NORMAL, INPUT),
192 DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, OUTPUT),
193 DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT),
194 DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, NORMAL, NORMAL, INPUT),
195 DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT),
196 DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, NORMAL, INPUT),
197 DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, NORMAL, INPUT),
198 DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT),
199 DEFAULT_PINMUX(PU0, RSVD1, NORMAL, NORMAL, INPUT),
200 DEFAULT_PINMUX(PU1, RSVD1, NORMAL, NORMAL, OUTPUT),
201 DEFAULT_PINMUX(PU2, RSVD1, NORMAL, NORMAL, INPUT),
202 DEFAULT_PINMUX(PU3, RSVD1, NORMAL, NORMAL, INPUT),
203 DEFAULT_PINMUX(PU4, PWM1, NORMAL, NORMAL, OUTPUT),
204 DEFAULT_PINMUX(PU5, PWM2, NORMAL, NORMAL, OUTPUT),
205 DEFAULT_PINMUX(PU6, RSVD1, NORMAL, NORMAL, INPUT),
206 DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, NORMAL, NORMAL, INPUT),
207 DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, NORMAL, NORMAL, INPUT),
208 DEFAULT_PINMUX(DAP4_DOUT_PP6, I2S3, NORMAL, NORMAL, INPUT),
209 DEFAULT_PINMUX(DAP4_SCLK_PP7, I2S3, NORMAL, NORMAL, INPUT),
210 DEFAULT_PINMUX(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT),
211 DEFAULT_PINMUX(CLK3_REQ_PEE1, DEV3, NORMAL, NORMAL, INPUT),
212 DEFAULT_PINMUX(GMI_WP_N_PC7, GMI, NORMAL, NORMAL, INPUT),
213 DEFAULT_PINMUX(GMI_CS2_N_PK3, RSVD1, UP, NORMAL, INPUT), /* EN_VDD_BL1 */
214 DEFAULT_PINMUX(GMI_AD8_PH0, PWM0, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_PWM */
215 DEFAULT_PINMUX(GMI_AD10_PH2, NAND, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_EN */
216 DEFAULT_PINMUX(GMI_A16_PJ7, SPI4, NORMAL, NORMAL, INPUT),
217 DEFAULT_PINMUX(GMI_A17_PB0, SPI4, NORMAL, NORMAL, INPUT),
218 DEFAULT_PINMUX(GMI_A18_PB1, SPI4, NORMAL, NORMAL, INPUT),
219 DEFAULT_PINMUX(GMI_A19_PK7, SPI4, NORMAL, NORMAL, INPUT),
220 DEFAULT_PINMUX(CAM_MCLK_PCC0, VI_ALT3, UP, NORMAL, INPUT),
221 DEFAULT_PINMUX(PCC1, RSVD1, NORMAL, NORMAL, INPUT),
222 DEFAULT_PINMUX(PBB0, RSVD1, NORMAL, NORMAL, INPUT),
223 DEFAULT_PINMUX(PBB3, VGP3, NORMAL, NORMAL, INPUT),
224 DEFAULT_PINMUX(PBB5, VGP5, NORMAL, NORMAL, INPUT),
225 DEFAULT_PINMUX(PBB6, VGP6, NORMAL, NORMAL, INPUT),
226 DEFAULT_PINMUX(PBB7, I2S4, NORMAL, NORMAL, INPUT),
227 DEFAULT_PINMUX(PCC2, I2S4, NORMAL, NORMAL, INPUT),
228 DEFAULT_PINMUX(JTAG_RTCK_PU7, RTCK, NORMAL, NORMAL, OUTPUT),
Tom Warren23d7fe92012-12-11 13:34:18 +0000[diff] [blame]229
230 /* KBC keys */
Stephen Warren43eed912014-03-21 12:28:59 -0600[diff] [blame]231 DEFAULT_PINMUX(KB_ROW0_PR0, KBC, UP, NORMAL, INPUT),
232 DEFAULT_PINMUX(KB_ROW1_PR1, KBC, UP, NORMAL, INPUT),
233 DEFAULT_PINMUX(KB_ROW2_PR2, KBC, UP, NORMAL, INPUT),
234 DEFAULT_PINMUX(KB_ROW3_PR3, KBC, UP, NORMAL, INPUT),
235 DEFAULT_PINMUX(KB_ROW4_PR4, KBC, UP, NORMAL, INPUT),
236 DEFAULT_PINMUX(KB_ROW5_PR5, KBC, UP, NORMAL, INPUT),
237 DEFAULT_PINMUX(KB_ROW6_PR6, KBC, UP, NORMAL, INPUT),
238 DEFAULT_PINMUX(KB_ROW7_PR7, KBC, UP, NORMAL, INPUT),
239 DEFAULT_PINMUX(KB_ROW8_PS0, KBC, UP, NORMAL, INPUT),
240 DEFAULT_PINMUX(KB_ROW9_PS1, KBC, UP, NORMAL, INPUT),
241 DEFAULT_PINMUX(KB_ROW10_PS2, KBC, UP, NORMAL, INPUT),
242 DEFAULT_PINMUX(KB_ROW11_PS3, KBC, UP, NORMAL, INPUT),
243 DEFAULT_PINMUX(KB_ROW12_PS4, KBC, UP, NORMAL, INPUT),
244 DEFAULT_PINMUX(KB_ROW13_PS5, KBC, UP, NORMAL, INPUT),
245 DEFAULT_PINMUX(KB_ROW14_PS6, KBC, UP, NORMAL, INPUT),
246 DEFAULT_PINMUX(KB_ROW15_PS7, KBC, UP, NORMAL, INPUT),
247 DEFAULT_PINMUX(KB_COL0_PQ0, KBC, UP, NORMAL, INPUT),
248 DEFAULT_PINMUX(KB_COL1_PQ1, KBC, UP, NORMAL, INPUT),
249 DEFAULT_PINMUX(KB_COL2_PQ2, KBC, UP, NORMAL, INPUT),
250 DEFAULT_PINMUX(KB_COL3_PQ3, KBC, UP, NORMAL, INPUT),
251 DEFAULT_PINMUX(KB_COL4_PQ4, KBC, UP, NORMAL, INPUT),
252 DEFAULT_PINMUX(KB_COL5_PQ5, KBC, UP, NORMAL, INPUT),
253 DEFAULT_PINMUX(KB_COL6_PQ6, KBC, UP, NORMAL, INPUT),
254 DEFAULT_PINMUX(KB_COL7_PQ7, KBC, UP, NORMAL, INPUT),
255 DEFAULT_PINMUX(PV0, RSVD1, UP, NORMAL, INPUT),
Tom Warren23d7fe92012-12-11 13:34:18 +0000[diff] [blame]256
Stephen Warren43eed912014-03-21 12:28:59 -0600[diff] [blame]257 DEFAULT_PINMUX(CLK_32K_OUT_PA0, BLINK, NORMAL, NORMAL, OUTPUT),
258 DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, OUTPUT),
Tom Warren23d7fe92012-12-11 13:34:18 +0000[diff] [blame]259 DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT),
Stephen Warren43eed912014-03-21 12:28:59 -0600[diff] [blame]260 DEFAULT_PINMUX(DAP1_FS_PN0, I2S0, NORMAL, NORMAL, INPUT),
261 DEFAULT_PINMUX(DAP1_DIN_PN1, I2S0, NORMAL, NORMAL, INPUT),
262 DEFAULT_PINMUX(DAP1_DOUT_PN2, I2S0, NORMAL, NORMAL, INPUT),
263 DEFAULT_PINMUX(DAP1_SCLK_PN3, I2S0, NORMAL, NORMAL, INPUT),
264 DEFAULT_PINMUX(CLK1_REQ_PEE2, DAP, NORMAL, NORMAL, INPUT),
265 DEFAULT_PINMUX(CLK1_OUT_PW4, EXTPERIPH1, NORMAL, NORMAL, INPUT),
266 DEFAULT_PINMUX(SPDIF_IN_PK6, SPDIF, NORMAL, NORMAL, INPUT),
267 DEFAULT_PINMUX(SPDIF_OUT_PK5, SPDIF, NORMAL, NORMAL, OUTPUT),
268 DEFAULT_PINMUX(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT),
269 DEFAULT_PINMUX(DAP2_DIN_PA4, I2S1, NORMAL, NORMAL, INPUT),
270 DEFAULT_PINMUX(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT),
271 DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT),
Tom Warren23d7fe92012-12-11 13:34:18 +0000[diff] [blame]272
Stephen Warren43eed912014-03-21 12:28:59 -0600[diff] [blame]273 DEFAULT_PINMUX(SPI2_CS1_N_PW2, SPI2, UP, NORMAL, INPUT),
274 DEFAULT_PINMUX(SPI1_MOSI_PX4, SPI1, NORMAL, NORMAL, INPUT),
275 DEFAULT_PINMUX(SPI1_SCK_PX5, SPI1, NORMAL, NORMAL, INPUT),
276 DEFAULT_PINMUX(SPI1_CS0_N_PX6, SPI1, NORMAL, NORMAL, INPUT),
277 DEFAULT_PINMUX(SPI1_MISO_PX7, SPI1, NORMAL, NORMAL, INPUT),
278 DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, PCIE, NORMAL, NORMAL, INPUT),
279 DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, NORMAL, OUTPUT),
280 DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, PCIE, NORMAL, NORMAL, INPUT),
281 DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT),
282 DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, NORMAL, NORMAL, INPUT),
283 DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, NORMAL, NORMAL, OUTPUT),
284 DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, NORMAL, NORMAL, INPUT),
285 DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT),
286 DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, OUTPUT),
287 DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, INPUT),
288 DEFAULT_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT),
289 DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, NORMAL, TRISTATE, INPUT),
Tom Warren23d7fe92012-12-11 13:34:18 +0000[diff] [blame]290
291 /* GPIOs */
292 /* SDMMC1 CD gpio */
Stephen Warren43eed912014-03-21 12:28:59 -0600[diff] [blame]293 DEFAULT_PINMUX(GMI_IORDY_PI5, RSVD1, UP, NORMAL, INPUT),
Tom Warren23d7fe92012-12-11 13:34:18 +0000[diff] [blame]294 /* SDMMC1 WP gpio */
Stephen Warren43eed912014-03-21 12:28:59 -0600[diff] [blame]295 LV_PINMUX(VI_D11_PT3, RSVD1, UP, NORMAL, INPUT, DISABLE, DISABLE),
Tom Warren23d7fe92012-12-11 13:34:18 +0000[diff] [blame]296
297 /* Touch panel GPIO */
298 /* Touch IRQ */
Stephen Warren43eed912014-03-21 12:28:59 -0600[diff] [blame]299 DEFAULT_PINMUX(GMI_AD12_PH4, NAND, UP, NORMAL, INPUT),
Tom Warren23d7fe92012-12-11 13:34:18 +0000[diff] [blame]300
301 /* Touch RESET */
Stephen Warren43eed912014-03-21 12:28:59 -0600[diff] [blame]302 DEFAULT_PINMUX(GMI_AD14_PH6, NAND, NORMAL, NORMAL, OUTPUT),
Tom Warren23d7fe92012-12-11 13:34:18 +0000[diff] [blame]303
304 /* Power rails GPIO */
Stephen Warren43eed912014-03-21 12:28:59 -0600[diff] [blame]305 DEFAULT_PINMUX(SPI2_SCK_PX2, GMI, NORMAL, NORMAL, INPUT),
306 DEFAULT_PINMUX(PBB4, VGP4, NORMAL, NORMAL, INPUT),
307 DEFAULT_PINMUX(KB_ROW8_PS0, KBC, UP, NORMAL, INPUT),
308 DEFAULT_PINMUX(SDMMC3_DAT5_PD0, SDMMC3, UP, NORMAL, INPUT),
309 DEFAULT_PINMUX(SDMMC3_DAT4_PD1, SDMMC3, UP, NORMAL, INPUT),
Tom Warren23d7fe92012-12-11 13:34:18 +0000[diff] [blame]310
Stephen Warren43eed912014-03-21 12:28:59 -0600[diff] [blame]311 LV_PINMUX(VI_D6_PL4, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
312 LV_PINMUX(VI_D8_PL6, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
313 LV_PINMUX(VI_D9_PL7, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
314 LV_PINMUX(VI_PCLK_PT0, RSVD1, UP, TRISTATE, INPUT, DISABLE, DISABLE),
315 LV_PINMUX(VI_HSYNC_PD7, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
316 LV_PINMUX(VI_VSYNC_PD6, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
Tom Warren23d7fe92012-12-11 13:34:18 +0000[diff] [blame]317};
318
Stephen Warrenf4df6052014-03-21 12:28:56 -0600[diff] [blame]319static struct pmux_pingrp_config unused_pins_lowpower[] = {
Stephen Warren43eed912014-03-21 12:28:59 -0600[diff] [blame]320 DEFAULT_PINMUX(GMI_WAIT_PI7, NAND, UP, TRISTATE, OUTPUT),
321 DEFAULT_PINMUX(GMI_ADV_N_PK0, NAND, NORMAL, TRISTATE, OUTPUT),
322 DEFAULT_PINMUX(GMI_CLK_PK1, NAND, NORMAL, TRISTATE, OUTPUT),
323 DEFAULT_PINMUX(GMI_CS3_N_PK4, NAND, NORMAL, NORMAL, OUTPUT),
324 DEFAULT_PINMUX(GMI_CS7_N_PI6, NAND, UP, NORMAL, INPUT),
325 DEFAULT_PINMUX(GMI_AD0_PG0, NAND, NORMAL, TRISTATE, OUTPUT),
326 DEFAULT_PINMUX(GMI_AD1_PG1, NAND, NORMAL, TRISTATE, OUTPUT),
327 DEFAULT_PINMUX(GMI_AD2_PG2, NAND, NORMAL, TRISTATE, OUTPUT),
328 DEFAULT_PINMUX(GMI_AD3_PG3, NAND, NORMAL, TRISTATE, OUTPUT),
329 DEFAULT_PINMUX(GMI_AD4_PG4, NAND, NORMAL, TRISTATE, OUTPUT),
330 DEFAULT_PINMUX(GMI_AD5_PG5, NAND, NORMAL, TRISTATE, OUTPUT),
331 DEFAULT_PINMUX(GMI_AD6_PG6, NAND, NORMAL, TRISTATE, OUTPUT),
332 DEFAULT_PINMUX(GMI_AD7_PG7, NAND, NORMAL, TRISTATE, OUTPUT),
333 DEFAULT_PINMUX(GMI_AD9_PH1, PWM1, NORMAL, NORMAL, OUTPUT),
334 DEFAULT_PINMUX(GMI_AD11_PH3, NAND, NORMAL, NORMAL, OUTPUT),
335 DEFAULT_PINMUX(GMI_AD13_PH5, NAND, UP, NORMAL, INPUT),
336 DEFAULT_PINMUX(GMI_WR_N_PI0, NAND, NORMAL, TRISTATE, OUTPUT),
337 DEFAULT_PINMUX(GMI_OE_N_PI1, NAND, NORMAL, TRISTATE, OUTPUT),
338 DEFAULT_PINMUX(GMI_DQS_PI2, NAND, NORMAL, TRISTATE, OUTPUT),
Tom Warren23d7fe92012-12-11 13:34:18 +0000[diff] [blame]339};
340
Stephen Warrenf4df6052014-03-21 12:28:56 -0600[diff] [blame]341static struct pmux_drvgrp_config cardhu_padctrl[] = {
342 /* (_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
Tom Warren7110b952013-03-06 16:16:22 -0700[diff] [blame]343 DEFAULT_PADCFG(SDIO1, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, \
344 SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, DISABLE, DISABLE),
345};
346#endif /* _PINMUX_CONFIG_CARDHU_H_ */