TENART Antoine | 7a5eb65 | 2013-07-02 12:06:00 +0200 | [diff] [blame] | 1 | /* |
| 2 | * ti816x_evm.h |
| 3 | * |
| 4 | * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> |
| 5 | * Antoine Tenart, <atenart@adeneo-embedded.com> |
| 6 | * |
| 7 | * SPDX-License-Identifier: GPL-2.0+ |
| 8 | */ |
| 9 | |
| 10 | #ifndef __CONFIG_TI816X_EVM_H |
| 11 | #define __CONFIG_TI816X_EVM_H |
| 12 | |
| 13 | #define CONFIG_TI81XX |
| 14 | #define CONFIG_TI816X |
| 15 | #define CONFIG_SYS_NO_FLASH |
| 16 | #define CONFIG_OMAP |
| 17 | #define CONFIG_OMAP_COMMON |
| 18 | |
| 19 | #define CONFIG_ARCH_CPU_INIT |
| 20 | |
| 21 | #include <asm/arch/omap.h> |
| 22 | |
| 23 | #define CONFIG_ENV_SIZE 0x2000 |
| 24 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (32 * 1024)) |
| 25 | #define CONFIG_SYS_LONGHELP /* undef save memory */ |
TENART Antoine | 7a5eb65 | 2013-07-02 12:06:00 +0200 | [diff] [blame] | 26 | #define CONFIG_MACH_TYPE MACH_TYPE_TI8168EVM |
| 27 | |
TENART Antoine | 7a5eb65 | 2013-07-02 12:06:00 +0200 | [diff] [blame] | 28 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ |
| 29 | #define CONFIG_SETUP_MEMORY_TAGS |
| 30 | #define CONFIG_INITRD_TAG /* required for ramdisk support */ |
| 31 | |
TENART Antoine | 7a5eb65 | 2013-07-02 12:06:00 +0200 | [diff] [blame] | 32 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 33 | "loadaddr=0x81000000\0" \ |
| 34 | |
| 35 | #define CONFIG_BOOTCOMMAND \ |
| 36 | "mmc rescan;" \ |
| 37 | "fatload mmc 0 ${loadaddr} uImage;" \ |
| 38 | "bootm ${loadaddr}" \ |
| 39 | |
| 40 | #define CONFIG_BOOTARGS "console=ttyO2,115200n8 noinitrd earlyprintk" |
| 41 | |
| 42 | /* Clock Defines */ |
| 43 | #define V_OSCK 24000000 /* Clock output from T2 */ |
| 44 | #define V_SCLK (V_OSCK >> 1) |
| 45 | |
| 46 | #define CONFIG_SYS_MAXARGS 32 |
| 47 | #define CONFIG_SYS_CBSIZE 512 /* console I/O buffer size */ |
| 48 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ |
| 49 | + sizeof(CONFIG_SYS_PROMPT) + 16) /* print buffer size */ |
| 50 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* boot arg buffer size */ |
| 51 | |
TENART Antoine | 7a5eb65 | 2013-07-02 12:06:00 +0200 | [diff] [blame] | 52 | #define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */ |
TENART Antoine | 7a5eb65 | 2013-07-02 12:06:00 +0200 | [diff] [blame] | 53 | |
| 54 | #define CONFIG_CMD_ASKEN |
TENART Antoine | 7a5eb65 | 2013-07-02 12:06:00 +0200 | [diff] [blame] | 55 | #define CONFIG_OMAP_GPIO |
| 56 | #define CONFIG_MMC |
| 57 | #define CONFIG_GENERIC_MMC |
| 58 | #define CONFIG_OMAP_HSMMC |
TENART Antoine | 7a5eb65 | 2013-07-02 12:06:00 +0200 | [diff] [blame] | 59 | #define CONFIG_DOS_PARTITION |
TENART Antoine | 7a5eb65 | 2013-07-02 12:06:00 +0200 | [diff] [blame] | 60 | |
| 61 | #define CONFIG_FS_FAT |
| 62 | |
| 63 | /* |
| 64 | * Only one of the following two options (DDR3/DDR2) should be enabled |
| 65 | * CONFIG_TI816X_EVM_DDR2 |
| 66 | * CONFIG_TI816X_EVM_DDR3 |
| 67 | */ |
| 68 | #define CONFIG_TI816X_EVM_DDR3 |
| 69 | |
| 70 | /* |
| 71 | * Supported values: 400, 531, 675 or 796 MHz |
| 72 | */ |
| 73 | #define CONFIG_TI816X_DDR_PLL_796 |
| 74 | |
| 75 | #define CONFIG_TI816X_USE_EMIF0 1 |
| 76 | #define CONFIG_TI816X_USE_EMIF1 1 |
| 77 | |
TENART Antoine | 7a5eb65 | 2013-07-02 12:06:00 +0200 | [diff] [blame] | 78 | #define CONFIG_NR_DRAM_BANKS 2 /* we have 2 banks of DRAM */ |
| 79 | #define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */ |
| 80 | #define PHYS_DRAM_1_SIZE 0x40000000 /* 1 GB */ |
| 81 | #define PHYS_DRAM_2 0xC0000000 /* DRAM Bank #2 */ |
| 82 | #define PHYS_DRAM_2_SIZE 0x40000000 /* 1 GB */ |
| 83 | |
| 84 | #define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2048MB */ |
| 85 | #define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1 |
| 86 | #define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ |
| 87 | GENERATED_GBL_DATA_SIZE) |
| 88 | |
| 89 | /** |
| 90 | * Platform/Board specific defs |
| 91 | */ |
| 92 | #define CONFIG_SYS_CLK_FREQ 27000000 |
| 93 | #define CONFIG_SYS_TIMERBASE 0x4802E000 |
| 94 | #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ |
| 95 | |
| 96 | #undef CONFIG_NAND_OMAP_GPMC |
| 97 | |
| 98 | /* |
| 99 | * NS16550 Configuration |
| 100 | */ |
TENART Antoine | 7a5eb65 | 2013-07-02 12:06:00 +0200 | [diff] [blame] | 101 | #define CONFIG_SYS_NS16550_SERIAL |
| 102 | #define CONFIG_SYS_NS16550_REG_SIZE (-4) |
| 103 | #define CONFIG_SYS_NS16550_CLK (48000000) |
| 104 | #define CONFIG_SYS_NS16550_COM1 0x48024000 /* Base EVM has UART2 */ |
| 105 | |
| 106 | #define CONFIG_BAUDRATE 115200 |
| 107 | |
| 108 | /* allow overwriting serial config and ethaddr */ |
| 109 | #define CONFIG_ENV_OVERWRITE |
| 110 | |
| 111 | #define CONFIG_SERIAL1 |
| 112 | #define CONFIG_SERIAL2 |
| 113 | #define CONFIG_SERIAL3 |
| 114 | #define CONFIG_CONS_INDEX 1 |
TENART Antoine | 7a5eb65 | 2013-07-02 12:06:00 +0200 | [diff] [blame] | 115 | |
| 116 | #define CONFIG_ENV_IS_NOWHERE |
| 117 | |
| 118 | /* SPL */ |
| 119 | /* Defines for SPL */ |
TENART Antoine | 7a5eb65 | 2013-07-02 12:06:00 +0200 | [diff] [blame] | 120 | #define CONFIG_SPL_FRAMEWORK |
| 121 | #define CONFIG_SPL_TEXT_BASE 0x40400000 |
Tom Rini | cfff4aa | 2016-08-26 13:30:43 -0400 | [diff] [blame] | 122 | #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ |
| 123 | CONFIG_SPL_TEXT_BASE) |
TENART Antoine | 7a5eb65 | 2013-07-02 12:06:00 +0200 | [diff] [blame] | 124 | |
| 125 | #define CONFIG_SPL_BSS_START_ADDR 0x80000000 |
| 126 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ |
| 127 | |
Paul Kocialkowski | 341e8cd | 2014-11-08 23:14:55 +0100 | [diff] [blame] | 128 | #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 |
Guillaume GARDET | 602a16c | 2014-10-15 17:53:11 +0200 | [diff] [blame] | 129 | #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" |
TENART Antoine | 7a5eb65 | 2013-07-02 12:06:00 +0200 | [diff] [blame] | 130 | |
TENART Antoine | 7a5eb65 | 2013-07-02 12:06:00 +0200 | [diff] [blame] | 131 | #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 |
| 132 | #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 |
| 133 | #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" |
| 134 | |
| 135 | #define CONFIG_SPL_BOARD_INIT |
| 136 | |
| 137 | #define CONFIG_SYS_TEXT_BASE 0x80800000 |
| 138 | #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 |
| 139 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 |
| 140 | |
| 141 | /* Since SPL did pll and ddr initialization for us, |
| 142 | * we don't need to do it twice. |
| 143 | */ |
| 144 | #ifndef CONFIG_SPL_BUILD |
| 145 | #define CONFIG_SKIP_LOWLEVEL_INIT |
| 146 | #endif |
| 147 | |
| 148 | /* Unsupported features */ |
| 149 | #undef CONFIG_USE_IRQ |
| 150 | |
| 151 | #endif |