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Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +09001/*
2 * Configuation settings for the Renesas SH7763RDP board
3 *
4 * Copyright (C) 2008 Renesas Solutions Corp.
5 * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
6 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +09008 */
9
10#ifndef __SH7763RDP_H
11#define __SH7763RDP_H
12
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090013#define CONFIG_CPU_SH7763 1
14#define CONFIG_SH7763RDP 1
15#define __LITTLE_ENDIAN 1
16
17/*
18 * Command line configuration.
19 */
20#define CONFIG_CMD_SDRAM
Nobuhiro Iwamatsu8a0d1c72008-08-08 16:30:23 +090021#define CONFIG_CMD_JFFS2
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090022
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090023#define CONFIG_BOOTARGS "console=ttySC2,115200 root=1f01"
24#define CONFIG_ENV_OVERWRITE 1
25
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090026#undef CONFIG_SHOW_BOOT_PROGRESS
27
28/* SCIF */
Jean-Christophe PLAGNIOL-VILLARD6ce9ea62008-08-13 01:40:38 +020029#define CONFIG_SCIF_CONSOLE 1
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090030#define CONFIG_BAUDRATE 115200
31#define CONFIG_CONS_SCIF2 1
32
Nobuhiro Iwamatsu69633662011-01-17 20:53:29 +090033#define CONFIG_SYS_TEXT_BASE 0x8FFC0000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020034#define CONFIG_SYS_LONGHELP /* undef to save memory */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020035#define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */
36#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
37#define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */
38#define CONFIG_SYS_BARGSIZE 512 /* Buffer size for Boot Arguments
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090039 passed to kernel */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020040#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090041 settings for this board */
42
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090043/* SDRAM */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020044#define CONFIG_SYS_SDRAM_BASE (0x8C000000)
45#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
46#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
47#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090048
49/* Flash(NOR) */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020050#define CONFIG_SYS_FLASH_BASE (0xA0000000)
51#define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT)
52#define CONFIG_SYS_MAX_FLASH_BANKS (1)
53#define CONFIG_SYS_MAX_FLASH_SECT (520)
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090054
Bin Meng75574052016-02-05 19:30:11 -080055/* U-Boot setting */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020056#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
57#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
58#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090059/* Size of DRAM reserved for malloc() use */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020060#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020061#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090062
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020063#define CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +020064#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020065#undef CONFIG_SYS_FLASH_QUIET_TEST
66#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090067/* Timeout for Flash erase operations (in ms) */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020068#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090069/* Timeout for Flash write operations (in ms) */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020070#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090071/* Timeout for Flash set sector lock bit operations (in ms) */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020072#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090073/* Timeout for Flash clear lock bit operations (in ms) */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020074#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090075/* Use hardware flash sectors protection instead of U-Boot software protection */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020076#undef CONFIG_SYS_FLASH_PROTECTION
77#undef CONFIG_SYS_DIRECT_FLASH_TFTP
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +020078#define CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +020079#define CONFIG_ENV_SECT_SIZE (128 * 1024)
80#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020081#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + (1 * CONFIG_ENV_SECT_SIZE))
82/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
83#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +020084#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020085#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090086
87/* Clock */
88#define CONFIG_SYS_CLK_FREQ 66666666
Nobuhiro Iwamatsue6984492013-08-21 16:11:21 +090089#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
90#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
Jean-Christophe PLAGNIOL-VILLARD32e6acc2009-06-04 12:06:48 +020091#define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +090092
Nobuhiro Iwamatsu8a0d1c72008-08-08 16:30:23 +090093/* Ether */
94#define CONFIG_SH_ETHER 1
95#define CONFIG_SH_ETHER_USE_PORT (1)
96#define CONFIG_SH_ETHER_PHY_ADDR (0x01)
Yoshihiro Shimodac578baa2011-10-31 10:44:18 +090097#define CONFIG_PHYLIB
98#define CONFIG_BITBANGMII
99#define CONFIG_BITBANGMII_MULTI
Nobuhiro Iwamatsu32f900e2012-05-16 10:23:21 +0900100#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
Nobuhiro Iwamatsu8a0d1c72008-08-08 16:30:23 +0900101
Nobuhiro Iwamatsu113a37e2008-06-09 13:39:57 +0900102#endif /* __SH7763RDP_H */