Mark Jonas | 35a398a | 2008-03-10 11:37:10 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Configuation settings for MPR2 |
| 3 | * |
| 4 | * Copyright (C) 2008 |
| 5 | * Mark Jonas <mark.jonas@de.bosch.com> |
| 6 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 7 | * SPDX-License-Identifier: GPL-2.0+ |
Mark Jonas | 35a398a | 2008-03-10 11:37:10 +0100 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | #ifndef __MPR2_H |
| 11 | #define __MPR2_H |
| 12 | |
| 13 | /* Supported commands */ |
Mark Jonas | 35a398a | 2008-03-10 11:37:10 +0100 | [diff] [blame] | 14 | |
| 15 | /* Default environment variables */ |
| 16 | #define CONFIG_BAUDRATE 115200 |
| 17 | #define CONFIG_BOOTARGS "console=ttySC0,115200" |
Joe Hershberger | e4da248 | 2011-10-13 13:03:48 +0000 | [diff] [blame] | 18 | #define CONFIG_BOOTFILE "/boot/zImage" |
Mark Jonas | 35a398a | 2008-03-10 11:37:10 +0100 | [diff] [blame] | 19 | #define CONFIG_LOADADDR 0x8E000000 |
Mark Jonas | 35a398a | 2008-03-10 11:37:10 +0100 | [diff] [blame] | 20 | |
| 21 | /* CPU and platform */ |
Mark Jonas | 35a398a | 2008-03-10 11:37:10 +0100 | [diff] [blame] | 22 | #define CONFIG_CPU_SH7720 1 |
| 23 | #define CONFIG_MPR2 1 |
| 24 | |
| 25 | /* U-Boot internals */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 26 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 27 | #define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */ |
| 28 | #define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */ |
| 29 | #define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */ |
| 30 | #define CONFIG_SYS_BARGSIZE 512 /* Buffer size for Boot Arguments passed to kernel */ |
| 31 | #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */ |
| 32 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024) |
| 33 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
| 34 | #define CONFIG_SYS_MONITOR_LEN (128 * 1024) |
| 35 | #define CONFIG_SYS_MALLOC_LEN (256 * 1024) |
Mark Jonas | 35a398a | 2008-03-10 11:37:10 +0100 | [diff] [blame] | 36 | |
Nobuhiro Iwamatsu | b6e3069 | 2011-01-17 21:13:49 +0900 | [diff] [blame] | 37 | #define CONFIG_SYS_TEXT_BASE 0x8FFC0000 |
| 38 | |
Mark Jonas | 35a398a | 2008-03-10 11:37:10 +0100 | [diff] [blame] | 39 | /* Memory */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 40 | #define CONFIG_SYS_SDRAM_BASE 0x8C000000 |
| 41 | #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) |
| 42 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE |
| 43 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024)) |
Mark Jonas | 35a398a | 2008-03-10 11:37:10 +0100 | [diff] [blame] | 44 | |
| 45 | /* Flash */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 46 | #define CONFIG_SYS_FLASH_CFI |
Jean-Christophe PLAGNIOL-VILLARD | 8d94c23 | 2008-08-13 01:40:42 +0200 | [diff] [blame] | 47 | #define CONFIG_FLASH_CFI_DRIVER |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 48 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
| 49 | #define CONFIG_SYS_FLASH_BASE 0xA0000000 |
| 50 | #define CONFIG_SYS_MAX_FLASH_SECT 256 |
| 51 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 |
| 52 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } |
Jean-Christophe PLAGNIOL-VILLARD | 53db4cd | 2008-09-10 22:48:04 +0200 | [diff] [blame] | 53 | #define CONFIG_ENV_IS_IN_FLASH |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 54 | #define CONFIG_ENV_SECT_SIZE (128 * 1024) |
| 55 | #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 56 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
| 57 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 |
| 58 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 |
Mark Jonas | 35a398a | 2008-03-10 11:37:10 +0100 | [diff] [blame] | 59 | |
| 60 | /* Clocks */ |
| 61 | #define CONFIG_SYS_CLK_FREQ 24000000 |
Nobuhiro Iwamatsu | e698449 | 2013-08-21 16:11:21 +0900 | [diff] [blame] | 62 | #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ |
| 63 | #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ |
Jean-Christophe PLAGNIOL-VILLARD | 32e6acc | 2009-06-04 12:06:48 +0200 | [diff] [blame] | 64 | #define CONFIG_SYS_TMU_CLK_DIV 4 /* 4 (default), 16, 64, 256 or 1024 */ |
Mark Jonas | 35a398a | 2008-03-10 11:37:10 +0100 | [diff] [blame] | 65 | |
| 66 | /* UART */ |
Jean-Christophe PLAGNIOL-VILLARD | 6ce9ea6 | 2008-08-13 01:40:38 +0200 | [diff] [blame] | 67 | #define CONFIG_SCIF_CONSOLE 1 |
Mark Jonas | 35a398a | 2008-03-10 11:37:10 +0100 | [diff] [blame] | 68 | #define CONFIG_CONS_SCIF0 1 |
| 69 | |
| 70 | #endif /* __MPR2_H */ |