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Heiko Schocherac1956e2006-04-20 08:42:42 +02001/*
Jens Scharsig2686eff2012-05-02 00:57:08 +00002 * Configuation settings for the BuS EB+CPU5283 boards (aka EB+MCF-EV123)
Heiko Schocherac1956e2006-04-20 08:42:42 +02003 *
Jens Scharsig772d9b02009-07-24 10:31:48 +02004 * (C) Copyright 2005-2009 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
Heiko Schocherac1956e2006-04-20 08:42:42 +02005 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Heiko Schocherac1956e2006-04-20 08:42:42 +02007 */
8
Jens Scharsig2686eff2012-05-02 00:57:08 +00009#ifndef _CONFIG_EB_CPU5282_H_
10#define _CONFIG_EB_CPU5282_H_
Heiko Schocherac1956e2006-04-20 08:42:42 +020011
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020012#undef CONFIG_SYS_HALT_BEFOR_RAM_JUMP
Wolfgang Denkf7290752006-06-10 22:00:40 +020013
Jens Scharsig772d9b02009-07-24 10:31:48 +020014/*----------------------------------------------------------------------*
15 * High Level Configuration Options (easy to change) *
16 *----------------------------------------------------------------------*/
Heiko Schocherac1956e2006-04-20 08:42:42 +020017
Heiko Schocherac1956e2006-04-20 08:42:42 +020018#define CONFIG_MISC_INIT_R
19
TsiChungLiewceaf3332007-08-15 19:55:10 -050020#define CONFIG_MCFUART
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020021#define CONFIG_SYS_UART_PORT (0)
Jens Scharsig (BuS Elektronik)e5e58372012-10-30 00:46:05 +000022#define CONFIG_BAUDRATE 115200
Heiko Schocherac1956e2006-04-20 08:42:42 +020023
Jens Scharsig772d9b02009-07-24 10:31:48 +020024#undef CONFIG_MONITOR_IS_IN_RAM /* starts uboot direct */
Heiko Schocherac1956e2006-04-20 08:42:42 +020025
26#define CONFIG_BOOTCOMMAND "printenv"
27
Jens Scharsig772d9b02009-07-24 10:31:48 +020028/*----------------------------------------------------------------------*
29 * Options *
30 *----------------------------------------------------------------------*/
31
32#define CONFIG_BOOT_RETRY_TIME -1
33#define CONFIG_RESET_TO_RETRY
34#define CONFIG_SPLASH_SCREEN
35
Jens Scharsig (BuS Elektronik)e5e58372012-10-30 00:46:05 +000036#define CONFIG_HW_WATCHDOG
37
38#define CONFIG_STATUS_LED
39#define CONFIG_BOARD_SPECIFIC_LED
40#define STATUS_LED_ACTIVE 0
41#define STATUS_LED_BIT 0x0008 /* Timer7 GPIO */
42#define STATUS_LED_BOOT 0
43#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
44#define STATUS_LED_STATE STATUS_LED_OFF
45
Jens Scharsig772d9b02009-07-24 10:31:48 +020046/*----------------------------------------------------------------------*
47 * Configuration for environment *
48 * Environment is in the second sector of the first 256k of flash *
49 *----------------------------------------------------------------------*/
50
Jens Scharsig (BuS Elektronik)e5e58372012-10-30 00:46:05 +000051#define CONFIG_ENV_ADDR 0xFF040000
52#define CONFIG_ENV_SECT_SIZE 0x00020000
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +020053#define CONFIG_ENV_IS_IN_FLASH 1
Heiko Schocherac1956e2006-04-20 08:42:42 +020054
Jon Loeligerdbb2b542007-07-07 20:56:05 -050055/*
Jon Loeligerf5709d12007-07-10 09:02:57 -050056 * BOOTP options
57 */
58#define CONFIG_BOOTP_BOOTFILESIZE
59#define CONFIG_BOOTP_BOOTPATH
60#define CONFIG_BOOTP_GATEWAY
61#define CONFIG_BOOTP_HOSTNAME
62
Jon Loeligerf5709d12007-07-10 09:02:57 -050063/*
Jon Loeligerdbb2b542007-07-07 20:56:05 -050064 * Command line configuration.
65 */
Jens Scharsig (BuS Elektronik)e5e58372012-10-30 00:46:05 +000066#define CONFIG_CMDLINE_EDITING
Jens Scharsig (BuS Elektronik)e5e58372012-10-30 00:46:05 +000067#define CONFIG_CMD_DATE
Jens Scharsig (BuS Elektronik)e5e58372012-10-30 00:46:05 +000068#define CONFIG_CMD_LED
Jon Loeligerdbb2b542007-07-07 20:56:05 -050069
TsiChung Liew26c9f3c2008-07-09 15:21:44 -050070#define CONFIG_MCFTMR
71
Jens Scharsig772d9b02009-07-24 10:31:48 +020072#define CONFIG_SYS_LONGHELP 1
Heiko Schocherac1956e2006-04-20 08:42:42 +020073
Jens Scharsig772d9b02009-07-24 10:31:48 +020074#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Jens Scharsig772d9b02009-07-24 10:31:48 +020075#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
76#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
77#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
Heiko Schocherac1956e2006-04-20 08:42:42 +020078
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020079#define CONFIG_SYS_LOAD_ADDR 0x20000
Heiko Schocherac1956e2006-04-20 08:42:42 +020080
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020081#define CONFIG_SYS_MEMTEST_START 0x100000
82#define CONFIG_SYS_MEMTEST_END 0x400000
83/*#define CONFIG_SYS_DRAM_TEST 1 */
84#undef CONFIG_SYS_DRAM_TEST
Heiko Schocherac1956e2006-04-20 08:42:42 +020085
Jens Scharsig772d9b02009-07-24 10:31:48 +020086/*----------------------------------------------------------------------*
87 * Clock and PLL Configuration *
88 *----------------------------------------------------------------------*/
Jens Scharsig (BuS Elektronik)e5e58372012-10-30 00:46:05 +000089#define CONFIG_SYS_CLK 80000000 /* 8MHz * 8 */
Heiko Schocherac1956e2006-04-20 08:42:42 +020090
Jens Scharsig (BuS Elektronik)e5e58372012-10-30 00:46:05 +000091/* PLL Configuration: Ext Clock * 8 (see table 9-4 of MCF user manual) */
Heiko Schocherac1956e2006-04-20 08:42:42 +020092
Jens Scharsig (BuS Elektronik)e5e58372012-10-30 00:46:05 +000093#define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */
Jens Scharsig772d9b02009-07-24 10:31:48 +020094#define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */
Heiko Schocherac1956e2006-04-20 08:42:42 +020095
Jens Scharsig772d9b02009-07-24 10:31:48 +020096/*----------------------------------------------------------------------*
97 * Network *
98 *----------------------------------------------------------------------*/
99
100#define CONFIG_MCFFEC
Jens Scharsig772d9b02009-07-24 10:31:48 +0200101#define CONFIG_MII 1
102#define CONFIG_MII_INIT 1
103#define CONFIG_SYS_DISCOVER_PHY
104#define CONFIG_SYS_RX_ETH_BUFFER 8
105#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
106
107#define CONFIG_SYS_FEC0_PINMUX 0
108#define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
109#define MCFFEC_TOUT_LOOP 50000
110
Jens Scharsig772d9b02009-07-24 10:31:48 +0200111#define CONFIG_OVERWRITE_ETHADDR_ONCE
112
113/*-------------------------------------------------------------------------
Heiko Schocherac1956e2006-04-20 08:42:42 +0200114 * Low Level Configuration Settings
115 * (address mappings, register initial values, etc.)
116 * You should know what you are doing if you make changes here.
Jens Scharsig772d9b02009-07-24 10:31:48 +0200117 *-----------------------------------------------------------------------*/
118
119#define CONFIG_SYS_MBAR 0x40000000
Heiko Schocherac1956e2006-04-20 08:42:42 +0200120
Heiko Schocherac1956e2006-04-20 08:42:42 +0200121/*-----------------------------------------------------------------------
122 * Definitions for initial stack pointer and data area (in DPRAM)
Jens Scharsig772d9b02009-07-24 10:31:48 +0200123 *-----------------------------------------------------------------------*/
124
125#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
Jens Scharsig (BuS Elektronik)e5e58372012-10-30 00:46:05 +0000126#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
Jens Scharsig772d9b02009-07-24 10:31:48 +0200127#define CONFIG_SYS_GBL_DATA_OFFSET \
Wolfgang Denk0191e472010-10-26 14:34:52 +0200128 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200129#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Heiko Schocherac1956e2006-04-20 08:42:42 +0200130
131/*-----------------------------------------------------------------------
132 * Start addresses for the final memory configuration
133 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200134 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
Heiko Schocherac1956e2006-04-20 08:42:42 +0200135 */
Jens Scharsig (BuS Elektronik)e5e58372012-10-30 00:46:05 +0000136#define CONFIG_SYS_SDRAM_BASE0 0x00000000
137#define CONFIG_SYS_SDRAM_SIZE0 16 /* SDRAM size in MB */
Heiko Schocherac1956e2006-04-20 08:42:42 +0200138
Jens Scharsig (BuS Elektronik)e5e58372012-10-30 00:46:05 +0000139#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM_BASE0
140#define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM_SIZE0
Heiko Schocherac1956e2006-04-20 08:42:42 +0200141
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200142#define CONFIG_SYS_MONITOR_LEN 0x20000
Jens Scharsig (BuS Elektronik)ef1030c2013-09-23 08:26:41 +0200143#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200144#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
Heiko Schocherac1956e2006-04-20 08:42:42 +0200145
146/*
147 * For booting Linux, the board info and command line data
148 * have to be in the first 8 MB of memory, since this is
149 * the maximum mapped by the Linux kernel during initialization ??
150 */
Jens Scharsig772d9b02009-07-24 10:31:48 +0200151#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Heiko Schocherac1956e2006-04-20 08:42:42 +0200152
153/*-----------------------------------------------------------------------
154 * FLASH organization
155 */
Jens Scharsig (BuS Elektronik)e5e58372012-10-30 00:46:05 +0000156#define CONFIG_FLASH_SHOW_PROGRESS 45
Jens Scharsig772d9b02009-07-24 10:31:48 +0200157
158#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
159#define CONFIG_SYS_INT_FLASH_BASE 0xF0000000
160#define CONFIG_SYS_INT_FLASH_ENABLE 0x21
161
Jens Scharsig (BuS Elektronik)e5e58372012-10-30 00:46:05 +0000162#define CONFIG_SYS_MAX_FLASH_SECT 128
163#define CONFIG_SYS_MAX_FLASH_BANKS 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200164#define CONFIG_SYS_FLASH_ERASE_TOUT 10000000
165#define CONFIG_SYS_FLASH_PROTECTION
Heiko Schocherac1956e2006-04-20 08:42:42 +0200166
Jens Scharsig (BuS Elektronik)e5e58372012-10-30 00:46:05 +0000167#define CONFIG_SYS_FLASH_CFI
168#define CONFIG_FLASH_CFI_DRIVER
169#define CONFIG_SYS_FLASH_SIZE 16*1024*1024
170#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
171
172#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
173
Heiko Schocherac1956e2006-04-20 08:42:42 +0200174/*-----------------------------------------------------------------------
175 * Cache Configuration
176 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200177#define CONFIG_SYS_CACHELINE_SIZE 16
Heiko Schocherac1956e2006-04-20 08:42:42 +0200178
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600179#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200180 CONFIG_SYS_INIT_RAM_SIZE - 8)
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600181#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200182 CONFIG_SYS_INIT_RAM_SIZE - 4)
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600183#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM)
184#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
185 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
186 CF_ACR_EN | CF_ACR_SM_ALL)
187#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
188 CF_CACR_CEIB | CF_CACR_DBWE | \
189 CF_CACR_EUSP)
190
Heiko Schocherac1956e2006-04-20 08:42:42 +0200191/*-----------------------------------------------------------------------
192 * Memory bank definitions
193 */
194
Jens Scharsig (BuS Elektronik)e5e58372012-10-30 00:46:05 +0000195#define CONFIG_SYS_CS0_BASE 0xFF000000
TsiChung Liew7f1a0462008-10-21 10:03:07 +0000196#define CONFIG_SYS_CS0_CTRL 0x00001980
Jens Scharsig (BuS Elektronik)e5e58372012-10-30 00:46:05 +0000197#define CONFIG_SYS_CS0_MASK 0x00FF0001
Heiko Schocherac1956e2006-04-20 08:42:42 +0200198
Jens Scharsig (BuS Elektronik)e5e58372012-10-30 00:46:05 +0000199#define CONFIG_SYS_CS2_BASE 0xE0000000
200#define CONFIG_SYS_CS2_CTRL 0x00001980
201#define CONFIG_SYS_CS2_MASK 0x000F0001
202
203#define CONFIG_SYS_CS3_BASE 0xE0100000
204#define CONFIG_SYS_CS3_CTRL 0x00001980
TsiChung Liew7f1a0462008-10-21 10:03:07 +0000205#define CONFIG_SYS_CS3_MASK 0x000F0001
Heiko Schocherac1956e2006-04-20 08:42:42 +0200206
207/*-----------------------------------------------------------------------
208 * Port configuration
209 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200210#define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */
211#define CONFIG_SYS_PADDR 0x0000000
212#define CONFIG_SYS_PADAT 0x0000000
Heiko Schocherac1956e2006-04-20 08:42:42 +0200213
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200214#define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */
215#define CONFIG_SYS_PBDDR 0x0000000
216#define CONFIG_SYS_PBDAT 0x0000000
Heiko Schocherac1956e2006-04-20 08:42:42 +0200217
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200218#define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */
219#define CONFIG_SYS_PCDDR 0x0000000
220#define CONFIG_SYS_PCDAT 0x0000000
Heiko Schocherac1956e2006-04-20 08:42:42 +0200221
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200222#define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */
223#define CONFIG_SYS_PCDDR 0x0000000
224#define CONFIG_SYS_PCDAT 0x0000000
Heiko Schocherac1956e2006-04-20 08:42:42 +0200225
Jens Scharsig (BuS Elektronik)e5e58372012-10-30 00:46:05 +0000226#define CONFIG_SYS_PASPAR 0x0F0F
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200227#define CONFIG_SYS_PEHLPAR 0xC0
Jens Scharsig772d9b02009-07-24 10:31:48 +0200228#define CONFIG_SYS_PUAPAR 0x0F
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200229#define CONFIG_SYS_DDRUA 0x05
230#define CONFIG_SYS_PJPAR 0xFF
Heiko Schocherac1956e2006-04-20 08:42:42 +0200231
232/*-----------------------------------------------------------------------
Jens Scharsig (BuS Elektronik)e5e58372012-10-30 00:46:05 +0000233 * I2C
234 */
235
Heiko Schocherf2850742012-10-24 13:48:22 +0200236#define CONFIG_SYS_I2C
237#define CONFIG_SYS_I2C_FSL
Jens Scharsig (BuS Elektronik)e5e58372012-10-30 00:46:05 +0000238
Heiko Schocherf2850742012-10-24 13:48:22 +0200239#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300
Jens Scharsig (BuS Elektronik)e5e58372012-10-30 00:46:05 +0000240#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
241
Heiko Schocherf2850742012-10-24 13:48:22 +0200242#define CONFIG_SYS_FSL_I2C_SPEED 100000
243#define CONFIG_SYS_FSL_I2C_SLAVE 0
Jens Scharsig (BuS Elektronik)e5e58372012-10-30 00:46:05 +0000244
245#ifdef CONFIG_CMD_DATE
246#define CONFIG_RTC_DS1338
247#define CONFIG_I2C_RTC_ADDR 0x68
248#endif
249
250/*-----------------------------------------------------------------------
Jens Scharsig772d9b02009-07-24 10:31:48 +0200251 * VIDEO configuration
Heiko Schocherac1956e2006-04-20 08:42:42 +0200252 */
253
Jens Scharsig772d9b02009-07-24 10:31:48 +0200254#ifdef CONFIG_VIDEO
Jens Scharsig (BuS Elektronik)e5e58372012-10-30 00:46:05 +0000255#define CONFIG_VIDEO_VCXK 1
Jens Scharsig772d9b02009-07-24 10:31:48 +0200256
257#define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN 2
258#define CONFIG_SYS_VCXK_DOUBLEBUFFERED 1
Jens Scharsig (BuS Elektronik)e5e58372012-10-30 00:46:05 +0000259#define CONFIG_SYS_VCXK_BASE CONFIG_SYS_CS2_BASE
Jens Scharsig772d9b02009-07-24 10:31:48 +0200260
261#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT MCFGPTB_GPTPORT
262#define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR MCFGPTB_GPTDDR
263#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN 0x0001
264
265#define CONFIG_SYS_VCXK_ENABLE_PORT MCFGPTB_GPTPORT
266#define CONFIG_SYS_VCXK_ENABLE_DDR MCFGPTB_GPTDDR
267#define CONFIG_SYS_VCXK_ENABLE_PIN 0x0002
268
269#define CONFIG_SYS_VCXK_REQUEST_PORT MCFGPTB_GPTPORT
270#define CONFIG_SYS_VCXK_REQUEST_DDR MCFGPTB_GPTDDR
271#define CONFIG_SYS_VCXK_REQUEST_PIN 0x0004
272
273#define CONFIG_SYS_VCXK_INVERT_PORT MCFGPIO_PORTE
274#define CONFIG_SYS_VCXK_INVERT_DDR MCFGPIO_DDRE
275#define CONFIG_SYS_VCXK_INVERT_PIN MCFGPIO_PORT2
Heiko Schocherac1956e2006-04-20 08:42:42 +0200276
Jens Scharsig772d9b02009-07-24 10:31:48 +0200277#endif /* CONFIG_VIDEO */
Heiko Schocherac1956e2006-04-20 08:42:42 +0200278#endif /* _CONFIG_M5282EVB_H */
279/*---------------------------------------------------------------------*/