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Igor Grinbergc3373ee2014-11-05 14:25:35 +02001/*
2 * (C) Copyright 2013 CompuLab, Ltd.
3 * Author: Igor Grinberg <grinberg@compulab.co.il>
4 *
5 * Configuration settings for the CompuLab CM-T3517 board
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13/*
14 * High Level Configuration Options
15 */
16#define CONFIG_OMAP /* in a TI OMAP core */
17#define CONFIG_CM_T3517 /* working with CM-T3517 */
18#define CONFIG_OMAP_COMMON
Nishanth Menon3e46e3e2015-03-09 17:12:08 -050019/* Common ARM Erratas */
20#define CONFIG_ARM_ERRATA_454179
21#define CONFIG_ARM_ERRATA_430973
22#define CONFIG_ARM_ERRATA_621766
Igor Grinbergc3373ee2014-11-05 14:25:35 +020023
24#define CONFIG_SYS_TEXT_BASE 0x80008000
25
26/*
27 * This is needed for the DMA stuff.
28 * Although the default iss 64, we still define it
29 * to be on the safe side once the default is changed.
30 */
Igor Grinbergc3373ee2014-11-05 14:25:35 +020031
32#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
33
34#include <asm/arch/cpu.h> /* get chip and board defs */
Nishanth Menonfa96c962015-03-09 17:12:04 -050035#include <asm/arch/omap.h>
Igor Grinbergc3373ee2014-11-05 14:25:35 +020036
Dmitry Lifshitza65120c2015-09-09 11:27:17 +030037#define CONFIG_MACH_TYPE MACH_TYPE_CM_T3517
38
Igor Grinbergc3373ee2014-11-05 14:25:35 +020039/* Clock Defines */
40#define V_OSCK 26000000 /* Clock output from T2 */
41#define V_SCLK (V_OSCK >> 1)
42
43#define CONFIG_MISC_INIT_R
44
Igor Grinbergc3373ee2014-11-05 14:25:35 +020045/*
46 * The early kernel mapping on ARM currently only maps from the base of DRAM
47 * to the end of the kernel image. The kernel is loaded at DRAM base + 0x8000.
48 * The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000,
49 * so that leaves DRAM base to DRAM base + 0x4000 available.
50 */
51#define CONFIG_SYS_BOOTMAPSZ 0x4000
52
53#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
54#define CONFIG_SETUP_MEMORY_TAGS
55#define CONFIG_INITRD_TAG
56#define CONFIG_REVISION_TAG
57#define CONFIG_SERIAL_TAG
58
59/*
60 * Size of malloc() pool
61 */
Dmitry Lifshitz4fb49e02015-09-09 11:25:39 +030062#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
Igor Grinbergc3373ee2014-11-05 14:25:35 +020063#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
64
65/*
66 * Hardware drivers
67 */
68
69/*
70 * NS16550 Configuration
71 */
Igor Grinbergc3373ee2014-11-05 14:25:35 +020072#define CONFIG_SYS_NS16550_SERIAL
73#define CONFIG_SYS_NS16550_REG_SIZE (-4)
74#define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
75
76/*
77 * select serial console configuration
78 */
79#define CONFIG_CONS_INDEX 3
80#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
81#define CONFIG_SERIAL3 3 /* UART3 */
Igor Grinbergc3373ee2014-11-05 14:25:35 +020082
83/* allow to overwrite serial and ethaddr */
84#define CONFIG_ENV_OVERWRITE
85#define CONFIG_BAUDRATE 115200
86#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
87 115200}
88
89#define CONFIG_OMAP_GPIO
90
91#define CONFIG_GENERIC_MMC
92#define CONFIG_MMC
93#define CONFIG_OMAP_HSMMC
94#define CONFIG_DOS_PARTITION
95
Igor Grinbergf7fd7e42014-11-03 11:32:25 +020096/* USB */
97#define CONFIG_USB_MUSB_AM35X
98
99#ifndef CONFIG_USB_MUSB_AM35X
100#define CONFIG_USB_OMAP3
101#define CONFIG_USB_EHCI
102#define CONFIG_USB_EHCI_OMAP
103#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 146
104#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 147
105#else /* !CONFIG_USB_MUSB_AM35X */
Paul Kocialkowskif34dfcb2015-08-04 17:04:06 +0200106#define CONFIG_USB_MUSB_PIO_ONLY
Igor Grinbergf7fd7e42014-11-03 11:32:25 +0200107#endif /* CONFIG_USB_MUSB_AM35X */
108
Igor Grinbergc3373ee2014-11-05 14:25:35 +0200109/* commands to include */
Igor Grinbergc3373ee2014-11-05 14:25:35 +0200110#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
111#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
112#define CONFIG_MTD_PARTITIONS
113#define MTDIDS_DEFAULT "nand0=nand"
114#define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\
115 "1920k(u-boot),256k(u-boot-env),"\
116 "4m(kernel),-(fs)"
117
Igor Grinbergc3373ee2014-11-05 14:25:35 +0200118#define CONFIG_CMD_NAND /* NAND support */
Igor Grinbergc3373ee2014-11-05 14:25:35 +0200119
Igor Grinbergc3373ee2014-11-05 14:25:35 +0200120#define CONFIG_SYS_NO_FLASH
121#define CONFIG_SYS_I2C
122#define CONFIG_SYS_OMAP24_I2C_SPEED 400000
123#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
124#define CONFIG_SYS_I2C_OMAP34XX
125#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
126#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
127#define CONFIG_SYS_I2C_EEPROM_BUS 0
128#define CONFIG_I2C_MULTI_BUS
129
130/*
131 * Board NAND Info.
132 */
Igor Grinbergc3373ee2014-11-05 14:25:35 +0200133#define CONFIG_NAND_OMAP_GPMC
134#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
135 /* to access nand */
136#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
137 /* to access nand at */
138 /* CS0 */
139#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
140 /* devices */
141
142/* Environment information */
Igor Grinbergc3373ee2014-11-05 14:25:35 +0200143#define CONFIG_EXTRA_ENV_SETTINGS \
144 "loadaddr=0x82000000\0" \
145 "baudrate=115200\0" \
146 "console=ttyO2,115200n8\0" \
Dmitry Lifshitz0233cbc2015-09-08 09:50:00 +0300147 "netretry=yes\0" \
Igor Grinbergc3373ee2014-11-05 14:25:35 +0200148 "mpurate=auto\0" \
149 "vram=12M\0" \
150 "dvimode=1024x768MR-16@60\0" \
151 "defaultdisplay=dvi\0" \
152 "mmcdev=0\0" \
153 "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
154 "mmcrootfstype=ext4\0" \
155 "nandroot=/dev/mtdblock4 rw\0" \
156 "nandrootfstype=ubifs\0" \
157 "mmcargs=setenv bootargs console=${console} " \
158 "mpurate=${mpurate} " \
159 "vram=${vram} " \
160 "omapfb.mode=dvi:${dvimode} " \
161 "omapdss.def_disp=${defaultdisplay} " \
162 "root=${mmcroot} " \
163 "rootfstype=${mmcrootfstype}\0" \
164 "nandargs=setenv bootargs console=${console} " \
165 "mpurate=${mpurate} " \
166 "vram=${vram} " \
167 "omapfb.mode=dvi:${dvimode} " \
168 "omapdss.def_disp=${defaultdisplay} " \
169 "root=${nandroot} " \
170 "rootfstype=${nandrootfstype}\0" \
171 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
172 "bootscript=echo Running bootscript from mmc ...; " \
173 "source ${loadaddr}\0" \
174 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
175 "mmcboot=echo Booting from mmc ...; " \
176 "run mmcargs; " \
177 "bootm ${loadaddr}\0" \
178 "nandboot=echo Booting from nand ...; " \
179 "run nandargs; " \
180 "nand read ${loadaddr} 2a0000 400000; " \
181 "bootm ${loadaddr}\0" \
182
Igor Grinbergc3373ee2014-11-05 14:25:35 +0200183#define CONFIG_BOOTCOMMAND \
184 "mmc dev ${mmcdev}; if mmc rescan; then " \
185 "if run loadbootscript; then " \
186 "run bootscript; " \
187 "else " \
188 "if run loaduimage; then " \
189 "run mmcboot; " \
190 "else run nandboot; " \
191 "fi; " \
192 "fi; " \
193 "else run nandboot; fi"
194
195/*
196 * Miscellaneous configurable options
197 */
198#define CONFIG_AUTO_COMPLETE
199#define CONFIG_CMDLINE_EDITING
200#define CONFIG_TIMESTAMP
201#define CONFIG_SYS_AUTOLOAD "no"
202#define CONFIG_SYS_LONGHELP /* undef to save memory */
Igor Grinbergc3373ee2014-11-05 14:25:35 +0200203#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
204/* Print Buffer Size */
205#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
206 sizeof(CONFIG_SYS_PROMPT) + 16)
207#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
208/* Boot Argument Buffer Size */
209#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
210
211#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000)
212
213/*
214 * AM3517 has 12 GP timers, they can be driven by the system clock
215 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
216 * This rate is divided by a local divisor.
217 */
218#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
219#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
220#define CONFIG_SYS_HZ 1000
221
222/*-----------------------------------------------------------------------
223 * Physical Memory Map
224 */
225#define CONFIG_NR_DRAM_BANKS 1 /* CM-T3517 DRAM is only on CS0 */
226#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
227#define CONFIG_SYS_CS0_SIZE (256 << 20)
228
229/*-----------------------------------------------------------------------
230 * FLASH and environment organization
231 */
232
233/* **** PISMO SUPPORT *** */
234/* Monitor at start of flash */
235#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
236#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
237
238#define CONFIG_ENV_IS_IN_NAND
239#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
240#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
241#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
242
Igor Grinbergdfb92d02014-11-03 11:32:26 +0200243#if defined(CONFIG_CMD_NET)
244#define CONFIG_DRIVER_TI_EMAC
245#define CONFIG_DRIVER_TI_EMAC_USE_RMII
246#define CONFIG_MII
247#define CONFIG_SMC911X
248#define CONFIG_SMC911X_32_BIT
249#define CONFIG_SMC911X_BASE (0x2C000000 + (16 << 20))
Dmitry Lifshitz0233cbc2015-09-08 09:50:00 +0300250#define CONFIG_ARP_TIMEOUT 200UL
251#define CONFIG_NET_RETRY_COUNT 5
Igor Grinbergdfb92d02014-11-03 11:32:26 +0200252#endif /* CONFIG_CMD_NET */
253
Igor Grinbergc3373ee2014-11-05 14:25:35 +0200254/* additions for new relocation code, must be added to all boards */
255#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
256#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
257#define CONFIG_SYS_INIT_RAM_SIZE 0x800
258#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
259 CONFIG_SYS_INIT_RAM_SIZE - \
260 GENERATED_GBL_DATA_SIZE)
261
262/* Status LED */
263#define CONFIG_STATUS_LED /* Status LED enabled */
264#define CONFIG_BOARD_SPECIFIC_LED
265#define CONFIG_GPIO_LED
266#define GREEN_LED_GPIO 186 /* CM-T3517 Green LED is GPIO186 */
267#define GREEN_LED_DEV 0
268#define STATUS_LED_BIT GREEN_LED_GPIO
269#define STATUS_LED_STATE STATUS_LED_ON
270#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
271#define STATUS_LED_BOOT GREEN_LED_DEV
272
273/* GPIO banks */
274#ifdef CONFIG_STATUS_LED
275#define CONFIG_OMAP3_GPIO_6 /* GPIO186 is in GPIO bank 6 */
276#endif
277
Igor Grinberg62a95852014-11-03 11:32:27 +0200278/* Display Configuration */
279#define CONFIG_OMAP3_GPIO_2
280#define CONFIG_OMAP3_GPIO_5
281#define CONFIG_VIDEO_OMAP3
282#define LCD_BPP LCD_COLOR16
283
Igor Grinberg62a95852014-11-03 11:32:27 +0200284#define CONFIG_SPLASH_SCREEN
285#define CONFIG_SPLASHIMAGE_GUARD
286#define CONFIG_CMD_BMP
287#define CONFIG_BMP_16BPP
288#define CONFIG_SCF0403_LCD
289
290#define CONFIG_OMAP3_SPI
291
Nikita Kiryanov8e06caf2016-04-16 17:55:08 +0300292/* EEPROM */
293#define CONFIG_CMD_EEPROM
294#define CONFIG_ENV_EEPROM_IS_ON_I2C
295#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
296#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
297#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
298#define CONFIG_SYS_EEPROM_SIZE 256
299
300#define CONFIG_CMD_EEPROM_LAYOUT
301#define CONFIG_EEPROM_LAYOUT_HELP_STRING "v1, v2, v3"
302
Igor Grinbergc3373ee2014-11-05 14:25:35 +0200303#endif /* __CONFIG_H */