wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 1 | /* |
Wolfgang Denk | 3edb620 | 2014-10-24 15:31:26 +0200 | [diff] [blame] | 2 | * (C) Copyright 2000-2014 |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | /* |
| 9 | * board/config.h - configuration options, board specific |
| 10 | */ |
| 11 | |
| 12 | #ifndef __CONFIG_H |
| 13 | #define __CONFIG_H |
| 14 | |
| 15 | /* |
| 16 | * High Level Configuration Options |
| 17 | * (easy to change) |
| 18 | */ |
| 19 | |
| 20 | #define CONFIG_MPC860 1 |
| 21 | #define CONFIG_MPC860T 1 |
| 22 | #define CONFIG_MPC862 1 |
| 23 | |
| 24 | #define CONFIG_TQM862M 1 /* ...on a TQM8xxM module */ |
| 25 | |
Wolfgang Denk | 291ba1b | 2010-10-06 09:05:45 +0200 | [diff] [blame] | 26 | #define CONFIG_SYS_TEXT_BASE 0x40000000 |
| 27 | |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 28 | #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
Wolfgang Denk | f0d526a | 2009-07-28 22:13:52 +0200 | [diff] [blame] | 29 | #define CONFIG_SYS_SMC_RXBUFLEN 128 |
| 30 | #define CONFIG_SYS_MAXIDLE 10 |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 31 | #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ |
| 32 | |
wdenk | fb229ae | 2003-08-07 22:18:11 +0000 | [diff] [blame] | 33 | #define CONFIG_BOOTCOUNT_LIMIT |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 34 | |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 35 | |
| 36 | #define CONFIG_BOARD_TYPES 1 /* support board types */ |
| 37 | |
| 38 | #define CONFIG_PREBOOT "echo;" \ |
Wolfgang Denk | 1baed66 | 2008-03-03 12:16:44 +0100 | [diff] [blame] | 39 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 40 | "echo" |
| 41 | |
| 42 | #undef CONFIG_BOOTARGS |
| 43 | |
| 44 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 45 | "netdev=eth0\0" \ |
| 46 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
Wolfgang Denk | 86eb3b7 | 2005-11-20 21:40:11 +0100 | [diff] [blame] | 47 | "nfsroot=${serverip}:${rootpath}\0" \ |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 48 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
Wolfgang Denk | 86eb3b7 | 2005-11-20 21:40:11 +0100 | [diff] [blame] | 49 | "addip=setenv bootargs ${bootargs} " \ |
| 50 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ |
| 51 | ":${hostname}:${netdev}:off panic=1\0" \ |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 52 | "flash_nfs=run nfsargs addip;" \ |
Wolfgang Denk | 86eb3b7 | 2005-11-20 21:40:11 +0100 | [diff] [blame] | 53 | "bootm ${kernel_addr}\0" \ |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 54 | "flash_self=run ramargs addip;" \ |
Wolfgang Denk | 86eb3b7 | 2005-11-20 21:40:11 +0100 | [diff] [blame] | 55 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
| 56 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 57 | "rootpath=/opt/eldk/ppc_8xx\0" \ |
Wolfgang Denk | dae5bfd | 2008-08-09 23:17:32 +0200 | [diff] [blame] | 58 | "hostname=TQM862M\0" \ |
| 59 | "bootfile=TQM862M/uImage\0" \ |
Wolfgang Denk | 64ab518 | 2007-09-16 02:39:35 +0200 | [diff] [blame] | 60 | "fdt_addr=40080000\0" \ |
| 61 | "kernel_addr=400A0000\0" \ |
| 62 | "ramdisk_addr=40280000\0" \ |
Wolfgang Denk | dae5bfd | 2008-08-09 23:17:32 +0200 | [diff] [blame] | 63 | "u-boot=TQM862M/u-image.bin\0" \ |
| 64 | "load=tftp 200000 ${u-boot}\0" \ |
| 65 | "update=prot off 40000000 +${filesize};" \ |
| 66 | "era 40000000 +${filesize};" \ |
| 67 | "cp.b 200000 40000000 ${filesize};" \ |
| 68 | "sete filesize;save\0" \ |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 69 | "" |
| 70 | #define CONFIG_BOOTCOMMAND "run flash_self" |
| 71 | |
| 72 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 73 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 74 | |
| 75 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
| 76 | |
| 77 | #define CONFIG_STATUS_LED 1 /* Status LED enabled */ |
| 78 | |
| 79 | #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ |
| 80 | |
Jon Loeliger | 530ca67 | 2007-07-09 21:38:02 -0500 | [diff] [blame] | 81 | /* |
| 82 | * BOOTP options |
| 83 | */ |
| 84 | #define CONFIG_BOOTP_SUBNETMASK |
| 85 | #define CONFIG_BOOTP_GATEWAY |
| 86 | #define CONFIG_BOOTP_HOSTNAME |
| 87 | #define CONFIG_BOOTP_BOOTPATH |
| 88 | #define CONFIG_BOOTP_BOOTFILESIZE |
| 89 | |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 90 | #define CONFIG_MAC_PARTITION |
| 91 | #define CONFIG_DOS_PARTITION |
| 92 | |
| 93 | #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ |
| 94 | |
Jon Loeliger | edccb46 | 2007-07-04 22:30:50 -0500 | [diff] [blame] | 95 | /* |
| 96 | * Command line configuration. |
| 97 | */ |
Jon Loeliger | edccb46 | 2007-07-04 22:30:50 -0500 | [diff] [blame] | 98 | #define CONFIG_CMD_DATE |
Jon Loeliger | edccb46 | 2007-07-04 22:30:50 -0500 | [diff] [blame] | 99 | #define CONFIG_CMD_IDE |
Wolfgang Denk | dae5bfd | 2008-08-09 23:17:32 +0200 | [diff] [blame] | 100 | #define CONFIG_CMD_JFFS2 |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 101 | |
Wolfgang Denk | dae5bfd | 2008-08-09 23:17:32 +0200 | [diff] [blame] | 102 | #define CONFIG_NETCONSOLE |
| 103 | |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 104 | /* |
| 105 | * Miscellaneous configurable options |
| 106 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 107 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 108 | |
Wolfgang Denk | 274bac5 | 2006-10-28 02:29:14 +0200 | [diff] [blame] | 109 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 110 | |
Jon Loeliger | edccb46 | 2007-07-04 22:30:50 -0500 | [diff] [blame] | 111 | #if defined(CONFIG_CMD_KGDB) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 112 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 113 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 114 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 115 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 116 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 117 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| 118 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 119 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 120 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
| 121 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 122 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 123 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 124 | |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 125 | /* |
| 126 | * Low Level Configuration Settings |
| 127 | * (address mappings, register initial values, etc.) |
| 128 | * You should know what you are doing if you make changes here. |
| 129 | */ |
| 130 | /*----------------------------------------------------------------------- |
| 131 | * Internal Memory Mapped Register |
| 132 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 133 | #define CONFIG_SYS_IMMR 0xFFF00000 |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 134 | |
| 135 | /*----------------------------------------------------------------------- |
| 136 | * Definitions for initial stack pointer and data area (in DPRAM) |
| 137 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 138 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
Wolfgang Denk | 1c2e98e | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 139 | #define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ |
Wolfgang Denk | 0191e47 | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 140 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 141 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 142 | |
| 143 | /*----------------------------------------------------------------------- |
| 144 | * Start addresses for the final memory configuration |
| 145 | * (Set up by the startup code) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 146 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 147 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 148 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
| 149 | #define CONFIG_SYS_FLASH_BASE 0x40000000 |
| 150 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
| 151 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
| 152 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 153 | |
| 154 | /* |
| 155 | * For booting Linux, the board info and command line data |
| 156 | * have to be in the first 8 MB of memory, since this is |
| 157 | * the maximum mapped by the Linux kernel during initialization. |
| 158 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 159 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 160 | |
| 161 | /*----------------------------------------------------------------------- |
| 162 | * FLASH organization |
| 163 | */ |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 164 | |
Martin Krause | c098b0e | 2007-09-27 11:10:08 +0200 | [diff] [blame] | 165 | /* use CFI flash driver */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 166 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ |
Jean-Christophe PLAGNIOL-VILLARD | 8d94c23 | 2008-08-13 01:40:42 +0200 | [diff] [blame] | 167 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 168 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } |
| 169 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
| 170 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 |
| 171 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
| 172 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 173 | |
Jean-Christophe PLAGNIOL-VILLARD | 53db4cd | 2008-09-10 22:48:04 +0200 | [diff] [blame] | 174 | #define CONFIG_ENV_IS_IN_FLASH 1 |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 175 | #define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ |
| 176 | #define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */ |
| 177 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 178 | |
| 179 | /* Address and size of Redundant Environment Sector */ |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 180 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) |
| 181 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 182 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 183 | #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ |
Wolfgang Denk | 4ed40bb | 2007-09-16 17:10:04 +0200 | [diff] [blame] | 184 | |
Wolfgang Denk | 8d82cc0 | 2008-09-16 18:02:19 +0200 | [diff] [blame] | 185 | #define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ |
| 186 | |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 187 | /*----------------------------------------------------------------------- |
Wolfgang Denk | dae5bfd | 2008-08-09 23:17:32 +0200 | [diff] [blame] | 188 | * Dynamic MTD partition support |
| 189 | */ |
Stefan Roese | b1423dd | 2009-03-19 13:30:36 +0100 | [diff] [blame] | 190 | #define CONFIG_CMD_MTDPARTS |
Stefan Roese | 5dc958f | 2009-05-12 14:32:58 +0200 | [diff] [blame] | 191 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ |
| 192 | #define CONFIG_FLASH_CFI_MTD |
Wolfgang Denk | dae5bfd | 2008-08-09 23:17:32 +0200 | [diff] [blame] | 193 | #define MTDIDS_DEFAULT "nor0=TQM8xxM-0" |
| 194 | |
| 195 | #define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ |
| 196 | "128k(dtb)," \ |
| 197 | "1920k(kernel)," \ |
| 198 | "5632(rootfs)," \ |
Wolfgang Denk | 1ec1677 | 2008-08-12 16:08:38 +0200 | [diff] [blame] | 199 | "4m(data)" |
Wolfgang Denk | dae5bfd | 2008-08-09 23:17:32 +0200 | [diff] [blame] | 200 | |
| 201 | /*----------------------------------------------------------------------- |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 202 | * Hardware Information Block |
| 203 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 204 | #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ |
| 205 | #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ |
| 206 | #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 207 | |
| 208 | /*----------------------------------------------------------------------- |
| 209 | * Cache Configuration |
| 210 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 211 | #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
Jon Loeliger | edccb46 | 2007-07-04 22:30:50 -0500 | [diff] [blame] | 212 | #if defined(CONFIG_CMD_KGDB) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 213 | #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 214 | #endif |
| 215 | |
| 216 | /*----------------------------------------------------------------------- |
| 217 | * SYPCR - System Protection Control 11-9 |
| 218 | * SYPCR can only be written once after reset! |
| 219 | *----------------------------------------------------------------------- |
| 220 | * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze |
| 221 | */ |
| 222 | #if defined(CONFIG_WATCHDOG) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 223 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 224 | SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
| 225 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 226 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 227 | #endif |
| 228 | |
| 229 | /*----------------------------------------------------------------------- |
| 230 | * SIUMCR - SIU Module Configuration 11-6 |
| 231 | *----------------------------------------------------------------------- |
| 232 | * PCMCIA config., multi-function pin tri-state |
| 233 | */ |
| 234 | #ifndef CONFIG_CAN_DRIVER |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 235 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 236 | #else /* we must activate GPL5 in the SIUMCR for CAN */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 237 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 238 | #endif /* CONFIG_CAN_DRIVER */ |
| 239 | |
| 240 | /*----------------------------------------------------------------------- |
| 241 | * TBSCR - Time Base Status and Control 11-26 |
| 242 | *----------------------------------------------------------------------- |
| 243 | * Clear Reference Interrupt Status, Timebase freezing enabled |
| 244 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 245 | #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 246 | |
| 247 | /*----------------------------------------------------------------------- |
| 248 | * RTCSC - Real-Time Clock Status and Control Register 11-27 |
| 249 | *----------------------------------------------------------------------- |
| 250 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 251 | #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 252 | |
| 253 | /*----------------------------------------------------------------------- |
| 254 | * PISCR - Periodic Interrupt Status and Control 11-31 |
| 255 | *----------------------------------------------------------------------- |
| 256 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled |
| 257 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 258 | #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 259 | |
| 260 | /*----------------------------------------------------------------------- |
| 261 | * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 |
| 262 | *----------------------------------------------------------------------- |
| 263 | * Reset PLL lock status sticky bit, timer expired status bit and timer |
| 264 | * interrupt status bit |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 265 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 266 | #define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 267 | |
| 268 | /*----------------------------------------------------------------------- |
| 269 | * SCCR - System Clock and reset Control Register 15-27 |
| 270 | *----------------------------------------------------------------------- |
| 271 | * Set clock output, timebase and RTC source and divider, |
| 272 | * power management and some other internal clocks |
| 273 | */ |
| 274 | #define SCCR_MASK SCCR_EBDF11 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 275 | #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 276 | SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ |
| 277 | SCCR_DFALCD00) |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 278 | |
| 279 | /*----------------------------------------------------------------------- |
| 280 | * PCMCIA stuff |
| 281 | *----------------------------------------------------------------------- |
| 282 | * |
| 283 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 284 | #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) |
| 285 | #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) |
| 286 | #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) |
| 287 | #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) |
| 288 | #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) |
| 289 | #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) |
| 290 | #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) |
| 291 | #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 292 | |
| 293 | /*----------------------------------------------------------------------- |
| 294 | * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) |
| 295 | *----------------------------------------------------------------------- |
| 296 | */ |
| 297 | |
Pavel Herrmann | 2c13c4a | 2012-10-09 07:01:56 +0000 | [diff] [blame] | 298 | #define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 299 | #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ |
| 300 | |
| 301 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ |
| 302 | #undef CONFIG_IDE_LED /* LED for ide not supported */ |
| 303 | #undef CONFIG_IDE_RESET /* reset for ide not supported */ |
| 304 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 305 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
| 306 | #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 307 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 308 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 309 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 310 | #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 311 | |
| 312 | /* Offset for data I/O */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 313 | #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 314 | |
| 315 | /* Offset for normal register accesses */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 316 | #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 317 | |
| 318 | /* Offset for alternate registers */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 319 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 320 | |
| 321 | /*----------------------------------------------------------------------- |
| 322 | * |
| 323 | *----------------------------------------------------------------------- |
| 324 | * |
| 325 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 326 | #define CONFIG_SYS_DER 0 |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 327 | |
| 328 | /* |
| 329 | * Init Memory Controller: |
| 330 | * |
| 331 | * BR0/1 and OR0/1 (FLASH) |
| 332 | */ |
| 333 | |
| 334 | #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ |
| 335 | #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #1 */ |
| 336 | |
| 337 | /* used to re-map FLASH both when starting from SRAM or FLASH: |
| 338 | * restrict access enough to keep SRAM working (if any) |
| 339 | * but not too much to meddle with FLASH accesses |
| 340 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 341 | #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ |
| 342 | #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 343 | |
| 344 | /* |
| 345 | * FLASH timing: |
| 346 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 347 | #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 348 | OR_SCY_3_CLK | OR_EHTR | OR_BI) |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 349 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 350 | #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
| 351 | #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
| 352 | #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 353 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 354 | #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP |
| 355 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM |
| 356 | #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 357 | |
| 358 | /* |
| 359 | * BR2/3 and OR2/3 (SDRAM) |
| 360 | * |
| 361 | */ |
| 362 | #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ |
| 363 | #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ |
| 364 | #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ |
| 365 | |
| 366 | /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 367 | #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 368 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 369 | #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) |
| 370 | #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 371 | |
| 372 | #ifndef CONFIG_CAN_DRIVER |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 373 | #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM |
| 374 | #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 375 | #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 376 | #define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ |
| 377 | #define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ |
| 378 | #define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) |
| 379 | #define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 380 | BR_PS_8 | BR_MS_UPMB | BR_V ) |
| 381 | #endif /* CONFIG_CAN_DRIVER */ |
| 382 | |
| 383 | /* |
| 384 | * Memory Periodic Timer Prescaler |
| 385 | * |
| 386 | * The Divider for PTA (refresh timer) configuration is based on an |
| 387 | * example SDRAM configuration (64 MBit, one bank). The adjustment to |
| 388 | * the number of chip selects (NCS) and the actually needed refresh |
| 389 | * rate is done by setting MPTPR. |
| 390 | * |
| 391 | * PTA is calculated from |
| 392 | * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) |
| 393 | * |
| 394 | * gclk CPU clock (not bus clock!) |
| 395 | * Trefresh Refresh cycle * 4 (four word bursts used) |
| 396 | * |
| 397 | * 4096 Rows from SDRAM example configuration |
| 398 | * 1000 factor s -> ms |
| 399 | * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration |
| 400 | * 4 Number of refresh cycles per period |
| 401 | * 64 Refresh cycle in ms per number of rows |
| 402 | * -------------------------------------------- |
| 403 | * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 |
| 404 | * |
| 405 | * 50 MHz => 50.000.000 / Divider = 98 |
| 406 | * 66 Mhz => 66.000.000 / Divider = 129 |
| 407 | * 80 Mhz => 80.000.000 / Divider = 156 |
| 408 | * 100 Mhz => 100.000.000 / Divider = 195 |
| 409 | */ |
wdenk | c78bf13 | 2004-04-24 23:23:30 +0000 | [diff] [blame] | 410 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 411 | #define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) |
| 412 | #define CONFIG_SYS_MAMR_PTA 98 |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 413 | |
| 414 | /* |
| 415 | * For 16 MBit, refresh rates could be 31.3 us |
| 416 | * (= 64 ms / 2K = 125 / quad bursts). |
| 417 | * For a simpler initialization, 15.6 us is used instead. |
| 418 | * |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 419 | * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks |
| 420 | * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 421 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 422 | #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ |
| 423 | #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 424 | |
| 425 | /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 426 | #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ |
| 427 | #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 428 | |
| 429 | /* |
| 430 | * MAMR settings for SDRAM |
| 431 | */ |
| 432 | |
| 433 | /* 8 column SDRAM */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 434 | #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 435 | MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ |
| 436 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
| 437 | /* 9 column SDRAM */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 438 | #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 439 | MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ |
| 440 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
| 441 | |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 442 | #define CONFIG_SCC1_ENET |
| 443 | #define CONFIG_FEC_ENET |
Heiko Schocher | c5e8405 | 2010-07-20 17:45:02 +0200 | [diff] [blame] | 444 | #define CONFIG_ETHPRIME "SCC" |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 445 | |
Heiko Schocher | c95fa8b | 2010-02-09 15:50:27 +0100 | [diff] [blame] | 446 | #define CONFIG_HWCONFIG 1 |
| 447 | |
wdenk | 7a428cc | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 448 | #endif /* __CONFIG_H */ |