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Andy Fleming71706df2007-04-23 02:54:25 -05001/*
Kumar Gala957ff362011-01-04 18:01:49 -06002 * Copyright 2004-2007, 2010-2011 Freescale Semiconductor.
Andy Fleming71706df2007-04-23 02:54:25 -05003 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +02004 * SPDX-License-Identifier: GPL-2.0+
Andy Fleming71706df2007-04-23 02:54:25 -05005 */
6
7/*
8 * mpc8568mds board configuration file
9 */
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13/* High Level Configuration Options */
14#define CONFIG_BOOKE 1 /* BOOKE */
Andy Flemingee0e9172007-08-14 00:14:25 -050015#define CONFIG_E500 1 /* BOOKE e500 family */
Andy Fleming71706df2007-04-23 02:54:25 -050016#define CONFIG_MPC8568 1 /* MPC8568 specific */
17#define CONFIG_MPC8568MDS 1 /* MPC8568MDS board specific */
18
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020019#define CONFIG_SYS_TEXT_BASE 0xfff80000
20
Kumar Gala957ff362011-01-04 18:01:49 -060021#define CONFIG_SYS_SRIO
22#define CONFIG_SRIO1 /* SRIO port 1 */
23
Haiying Wangf06709f2007-11-14 15:52:06 -050024#define CONFIG_PCI1 1 /* PCI controller */
25#define CONFIG_PCIE1 1 /* PCIE controller */
26#define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */
Gabor Juhosb4458732013-05-30 07:06:12 +000027#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
Kumar Gala93166d22007-12-07 12:17:34 -060028#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
Kumar Gala7738d5c2008-10-21 11:33:58 -050029#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Wolfgang Denka1be4762008-05-20 16:00:29 +020030#define CONFIG_TSEC_ENET /* tsec ethernet support */
Andy Fleming088e82c2007-08-15 20:03:34 -050031#define CONFIG_QE /* Enable QE */
Andy Fleming71706df2007-04-23 02:54:25 -050032#define CONFIG_ENV_OVERWRITE
Kumar Gala92c512a2008-01-16 09:15:29 -060033#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
Andy Fleming71706df2007-04-23 02:54:25 -050034
Andy Fleming71706df2007-04-23 02:54:25 -050035#ifndef __ASSEMBLY__
36extern unsigned long get_clock_freq(void);
37#endif /*Replace a call to get_clock_freq (after it is implemented)*/
38#define CONFIG_SYS_CLK_FREQ 66000000 /*TODO: restore if wanting to read from BCSR: get_clock_freq()*/ /* sysclk for MPC85xx */
39
40/*
41 * These can be toggled for performance analysis, otherwise use default.
42 */
Wolfgang Denka1be4762008-05-20 16:00:29 +020043#define CONFIG_L2_CACHE /* toggle L2 cache */
Haiying Wang6b9f1942007-08-23 15:20:54 -040044#define CONFIG_BTB /* toggle branch predition */
Andy Fleming71706df2007-04-23 02:54:25 -050045
46/*
47 * Only possible on E500 Version 2 or newer cores.
48 */
49#define CONFIG_ENABLE_36BIT_PHYS 1
50
Andy Fleming71706df2007-04-23 02:54:25 -050051#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
52
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020053#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
54#define CONFIG_SYS_MEMTEST_END 0x00400000
Andy Fleming71706df2007-04-23 02:54:25 -050055
Timur Tabid8f341c2011-08-04 18:03:41 -050056#define CONFIG_SYS_CCSRBAR 0xe0000000
57#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
Andy Fleming71706df2007-04-23 02:54:25 -050058
Jon Loeliger194de262008-03-18 13:51:05 -050059/* DDR Setup */
York Sunf0626592013-09-30 09:22:09 -070060#define CONFIG_SYS_FSL_DDR2
Jon Loeliger194de262008-03-18 13:51:05 -050061#undef CONFIG_FSL_DDR_INTERACTIVE
62#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
63#define CONFIG_DDR_SPD
Dave Liud3ca1242008-10-28 17:53:38 +080064#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
Jon Loeliger194de262008-03-18 13:51:05 -050065
66#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
67
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020068#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
69#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Andy Fleming71706df2007-04-23 02:54:25 -050070
Jon Loeliger194de262008-03-18 13:51:05 -050071#define CONFIG_NUM_DDR_CONTROLLERS 1
72#define CONFIG_DIMM_SLOTS_PER_CTLR 1
73#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
Andy Fleming71706df2007-04-23 02:54:25 -050074
Jon Loeliger194de262008-03-18 13:51:05 -050075/* I2C addresses of SPD EEPROMs */
76#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
77
78/* Make sure required options are set */
Andy Fleming71706df2007-04-23 02:54:25 -050079#ifndef CONFIG_SPD_EEPROM
80#error ("CONFIG_SPD_EEPROM is required")
81#endif
82
83#undef CONFIG_CLOCKS_IN_MHZ
84
Andy Fleming71706df2007-04-23 02:54:25 -050085/*
86 * Local Bus Definitions
87 */
88
89/*
90 * FLASH on the Local Bus
91 * Two banks, 8M each, using the CFI driver.
92 * Boot from BR0/OR0 bank at 0xff00_0000
93 * Alternate BR1/OR1 bank at 0xff80_0000
94 *
95 * BR0, BR1:
96 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
97 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
98 * Port Size = 16 bits = BRx[19:20] = 10
99 * Use GPCM = BRx[24:26] = 000
100 * Valid = BRx[31] = 1
101 *
102 * 0 4 8 12 16 20 24 28
103 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
104 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
105 *
106 * OR0, OR1:
107 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
108 * Reserved ORx[17:18] = 11, confusion here?
109 * CSNT = ORx[20] = 1
110 * ACS = half cycle delay = ORx[21:22] = 11
111 * SCY = 6 = ORx[24:27] = 0110
112 * TRLX = use relaxed timing = ORx[29] = 1
113 * EAD = use external address latch delay = OR[31] = 1
114 *
115 * 0 4 8 12 16 20 24 28
116 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
117 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200118#define CONFIG_SYS_BCSR_BASE 0xf8000000
Andy Fleming71706df2007-04-23 02:54:25 -0500119
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200120#define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */
Andy Fleming71706df2007-04-23 02:54:25 -0500121
122/*Chip select 0 - Flash*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200123#define CONFIG_SYS_BR0_PRELIM 0xfe001001
124#define CONFIG_SYS_OR0_PRELIM 0xfe006ff7
Andy Fleming71706df2007-04-23 02:54:25 -0500125
126/*Chip slelect 1 - BCSR*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200127#define CONFIG_SYS_BR1_PRELIM 0xf8000801
128#define CONFIG_SYS_OR1_PRELIM 0xffffe9f7
Andy Fleming71706df2007-04-23 02:54:25 -0500129
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200130/*#define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} */
131#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
132#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
133#undef CONFIG_SYS_FLASH_CHECKSUM
134#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
135#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Andy Fleming71706df2007-04-23 02:54:25 -0500136
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200137#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Andy Fleming71706df2007-04-23 02:54:25 -0500138
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +0200139#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200140#define CONFIG_SYS_FLASH_CFI
141#define CONFIG_SYS_FLASH_EMPTY_INFO
Andy Fleming71706df2007-04-23 02:54:25 -0500142
Andy Fleming71706df2007-04-23 02:54:25 -0500143/*
144 * SDRAM on the LocalBus
145 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200146#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
147#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
Andy Fleming71706df2007-04-23 02:54:25 -0500148
Andy Fleming71706df2007-04-23 02:54:25 -0500149/*Chip select 2 - SDRAM*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200150#define CONFIG_SYS_BR2_PRELIM 0xf0001861
151#define CONFIG_SYS_OR2_PRELIM 0xfc006901
Andy Fleming71706df2007-04-23 02:54:25 -0500152
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200153#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
154#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
155#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
156#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
Andy Fleming71706df2007-04-23 02:54:25 -0500157
158/*
Andy Fleming71706df2007-04-23 02:54:25 -0500159 * Common settings for all Local Bus SDRAM commands.
160 * At run time, either BSMA1516 (for CPU 1.1)
161 * or BSMA1617 (for CPU 1.0) (old)
162 * is OR'ed in too.
163 */
Kumar Gala727c6a62009-03-26 01:34:38 -0500164#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
165 | LSDMR_PRETOACT7 \
166 | LSDMR_ACTTORW7 \
167 | LSDMR_BL8 \
168 | LSDMR_WRC4 \
169 | LSDMR_CL3 \
170 | LSDMR_RFEN \
Andy Fleming71706df2007-04-23 02:54:25 -0500171 )
172
173/*
174 * The bcsr registers are connected to CS3 on MDS.
175 * The new memory map places bcsr at 0xf8000000.
176 *
177 * For BR3, need:
178 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
179 * port-size = 8-bits = BR[19:20] = 01
180 * no parity checking = BR[21:22] = 00
181 * GPMC for MSEL = BR[24:26] = 000
182 * Valid = BR[31] = 1
183 *
184 * 0 4 8 12 16 20 24 28
185 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
186 *
187 * For OR3, need:
188 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
189 * disable buffer ctrl OR[19] = 0
190 * CSNT OR[20] = 1
191 * ACS OR[21:22] = 11
192 * XACS OR[23] = 1
193 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
194 * SETA OR[28] = 0
195 * TRLX OR[29] = 1
196 * EHTR OR[30] = 1
197 * EAD extra time OR[31] = 1
198 *
199 * 0 4 8 12 16 20 24 28
200 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
201 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200202#define CONFIG_SYS_BCSR (0xf8000000)
Andy Fleming71706df2007-04-23 02:54:25 -0500203
204/*Chip slelect 4 - PIB*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200205#define CONFIG_SYS_BR4_PRELIM 0xf8008801
206#define CONFIG_SYS_OR4_PRELIM 0xffffe9f7
Andy Fleming71706df2007-04-23 02:54:25 -0500207
208/*Chip select 5 - PIB*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200209#define CONFIG_SYS_BR5_PRELIM 0xf8010801
210#define CONFIG_SYS_OR5_PRELIM 0xffff69f7
Andy Fleming71706df2007-04-23 02:54:25 -0500211
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200212#define CONFIG_SYS_INIT_RAM_LOCK 1
213#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200214#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
Andy Fleming71706df2007-04-23 02:54:25 -0500215
Wolfgang Denk0191e472010-10-26 14:34:52 +0200216#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200217#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Andy Fleming71706df2007-04-23 02:54:25 -0500218
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200219#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
220#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
Andy Fleming71706df2007-04-23 02:54:25 -0500221
222/* Serial Port */
223#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200224#define CONFIG_SYS_NS16550_SERIAL
225#define CONFIG_SYS_NS16550_REG_SIZE 1
226#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Andy Fleming71706df2007-04-23 02:54:25 -0500227
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200228#define CONFIG_SYS_BAUDRATE_TABLE \
Andy Fleming71706df2007-04-23 02:54:25 -0500229 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
230
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200231#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
232#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
Andy Fleming71706df2007-04-23 02:54:25 -0500233
Andy Fleming71706df2007-04-23 02:54:25 -0500234/*
235 * I2C
236 */
Heiko Schocherf2850742012-10-24 13:48:22 +0200237#define CONFIG_SYS_I2C
238#define CONFIG_SYS_I2C_FSL
239#define CONFIG_SYS_FSL_I2C_SPEED 400000
240#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
241#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
242#define CONFIG_SYS_FSL_I2C2_SPEED 400000
243#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
244#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
245#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200246#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
Andy Fleming71706df2007-04-23 02:54:25 -0500247
248/*
249 * General PCI
250 * Memory Addresses are mapped 1-1. I/O is mapped from 0
251 */
Kumar Galaef43b6e2008-12-02 16:08:39 -0600252#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
Kumar Gala3fe80872008-12-02 16:08:36 -0600253#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
Kumar Galaef43b6e2008-12-02 16:08:39 -0600254#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200255#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
Kumar Gala60ff4642008-12-02 16:08:40 -0600256#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
Kumar Gala64bb6d12008-12-02 16:08:37 -0600257#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200258#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
259#define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */
Andy Fleming71706df2007-04-23 02:54:25 -0500260
Kumar Gala2be70fa2010-12-17 10:13:19 -0600261#define CONFIG_SYS_PCIE1_NAME "Slot"
Kumar Galaef43b6e2008-12-02 16:08:39 -0600262#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
Kumar Gala3fe80872008-12-02 16:08:36 -0600263#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
Kumar Galaef43b6e2008-12-02 16:08:39 -0600264#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200265#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
Kumar Gala60ff4642008-12-02 16:08:40 -0600266#define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000
Kumar Gala64bb6d12008-12-02 16:08:37 -0600267#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200268#define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000
269#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
Andy Fleming71706df2007-04-23 02:54:25 -0500270
Kumar Gala957ff362011-01-04 18:01:49 -0600271#define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000
272#define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000
273#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS
274#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
Andy Fleming71706df2007-04-23 02:54:25 -0500275
Andy Flemingee0e9172007-08-14 00:14:25 -0500276#ifdef CONFIG_QE
277/*
278 * QE UEC ethernet configuration
279 */
280#define CONFIG_UEC_ETH
281#ifndef CONFIG_TSEC_ENET
Kim Phillipsb42cf5f2010-07-26 18:34:57 -0500282#define CONFIG_ETHPRIME "UEC0"
Andy Flemingee0e9172007-08-14 00:14:25 -0500283#endif
284#define CONFIG_PHY_MODE_NEED_CHANGE
285#define CONFIG_eTSEC_MDIO_BUS
286
287#ifdef CONFIG_eTSEC_MDIO_BUS
Wolfgang Denka1be4762008-05-20 16:00:29 +0200288#define CONFIG_MIIM_ADDRESS 0xE0024520
Andy Flemingee0e9172007-08-14 00:14:25 -0500289#endif
290
291#define CONFIG_UEC_ETH1 /* GETH1 */
292
293#ifdef CONFIG_UEC_ETH1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200294#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
295#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE
296#define CONFIG_SYS_UEC1_TX_CLK QE_CLK16
297#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
298#define CONFIG_SYS_UEC1_PHY_ADDR 7
Andy Fleming7832a462011-04-13 00:37:12 -0500299#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
Heiko Schocher40b44bc2010-01-20 09:04:28 +0100300#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
Andy Flemingee0e9172007-08-14 00:14:25 -0500301#endif
302
303#define CONFIG_UEC_ETH2 /* GETH2 */
304
305#ifdef CONFIG_UEC_ETH2
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200306#define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
307#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE
308#define CONFIG_SYS_UEC2_TX_CLK QE_CLK16
309#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
310#define CONFIG_SYS_UEC2_PHY_ADDR 1
Andy Fleming7832a462011-04-13 00:37:12 -0500311#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
Heiko Schocher40b44bc2010-01-20 09:04:28 +0100312#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
Andy Flemingee0e9172007-08-14 00:14:25 -0500313#endif
314#endif /* CONFIG_QE */
315
Haiying Wang593ac162007-11-19 10:02:13 -0500316#if defined(CONFIG_PCI)
Andy Fleming71706df2007-04-23 02:54:25 -0500317#undef CONFIG_EEPRO100
318#undef CONFIG_TULIP
319
320#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200321#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
Andy Fleming71706df2007-04-23 02:54:25 -0500322
323#endif /* CONFIG_PCI */
324
Andy Flemingee0e9172007-08-14 00:14:25 -0500325#if defined(CONFIG_TSEC_ENET)
326
Andy Fleming71706df2007-04-23 02:54:25 -0500327#define CONFIG_MII 1 /* MII PHY management */
Kim Phillips177e58f2007-05-16 16:52:19 -0500328#define CONFIG_TSEC1 1
329#define CONFIG_TSEC1_NAME "eTSEC0"
330#define CONFIG_TSEC2 1
331#define CONFIG_TSEC2_NAME "eTSEC1"
Andy Fleming71706df2007-04-23 02:54:25 -0500332
333#define TSEC1_PHY_ADDR 2
334#define TSEC2_PHY_ADDR 3
335
336#define TSEC1_PHYIDX 0
337#define TSEC2_PHYIDX 0
338
Andy Fleming09b88df2007-08-15 20:03:25 -0500339#define TSEC1_FLAGS TSEC_GIGABIT
340#define TSEC2_FLAGS TSEC_GIGABIT
341
Andy Fleming088e82c2007-08-15 20:03:34 -0500342/* Options are: eTSEC[0-1] */
Andy Fleming71706df2007-04-23 02:54:25 -0500343#define CONFIG_ETHPRIME "eTSEC0"
344
345#endif /* CONFIG_TSEC_ENET */
346
347/*
348 * Environment
349 */
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200350#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200351#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200352#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
353#define CONFIG_ENV_SIZE 0x2000
Andy Fleming71706df2007-04-23 02:54:25 -0500354
355#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200356#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Andy Fleming71706df2007-04-23 02:54:25 -0500357
Jon Loeligere63319f2007-06-13 13:22:08 -0500358/*
Jon Loeliger5c4ddae2007-07-10 10:12:10 -0500359 * BOOTP options
360 */
361#define CONFIG_BOOTP_BOOTFILESIZE
362#define CONFIG_BOOTP_BOOTPATH
363#define CONFIG_BOOTP_GATEWAY
364#define CONFIG_BOOTP_HOSTNAME
365
Jon Loeliger5c4ddae2007-07-10 10:12:10 -0500366/*
Jon Loeligere63319f2007-06-13 13:22:08 -0500367 * Command line configuration.
368 */
Kumar Gala489675d2008-09-22 23:40:42 -0500369#define CONFIG_CMD_IRQ
Becky Bruceee888da2010-06-17 11:37:25 -0500370#define CONFIG_CMD_REGINFO
Jon Loeligere63319f2007-06-13 13:22:08 -0500371
Andy Fleming71706df2007-04-23 02:54:25 -0500372#if defined(CONFIG_PCI)
Jon Loeligere63319f2007-06-13 13:22:08 -0500373 #define CONFIG_CMD_PCI
Andy Fleming71706df2007-04-23 02:54:25 -0500374#endif
Jon Loeligere63319f2007-06-13 13:22:08 -0500375
Andy Fleming71706df2007-04-23 02:54:25 -0500376#undef CONFIG_WATCHDOG /* watchdog disabled */
377
378/*
379 * Miscellaneous configurable options
380 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200381#define CONFIG_SYS_LONGHELP /* undef to save memory */
Kim Phillipsf7758c12010-07-14 19:47:18 -0500382#define CONFIG_CMDLINE_EDITING /* Command-line editing */
383#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200384#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Jon Loeligere63319f2007-06-13 13:22:08 -0500385#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200386#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Andy Fleming71706df2007-04-23 02:54:25 -0500387#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200388#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Andy Fleming71706df2007-04-23 02:54:25 -0500389#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200390#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
391#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
392#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Andy Fleming71706df2007-04-23 02:54:25 -0500393
394/*
395 * For booting Linux, the board info and command line data
Kumar Gala39ffcc12011-04-28 10:13:41 -0500396 * have to be in the first 64 MB of memory, since this is
Andy Fleming71706df2007-04-23 02:54:25 -0500397 * the maximum mapped by the Linux kernel during initialization.
398 */
Kumar Gala39ffcc12011-04-28 10:13:41 -0500399#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
400#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Andy Fleming71706df2007-04-23 02:54:25 -0500401
Jon Loeligere63319f2007-06-13 13:22:08 -0500402#if defined(CONFIG_CMD_KGDB)
Andy Fleming71706df2007-04-23 02:54:25 -0500403#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Andy Fleming71706df2007-04-23 02:54:25 -0500404#endif
405
406/*
407 * Environment Configuration
408 */
409
410/* The mac addresses for all ethernet interface */
Andy Flemingee0e9172007-08-14 00:14:25 -0500411#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_UEC_ETH)
412#define CONFIG_HAS_ETH0
Andy Fleming71706df2007-04-23 02:54:25 -0500413#define CONFIG_HAS_ETH1
Andy Fleming71706df2007-04-23 02:54:25 -0500414#define CONFIG_HAS_ETH2
Andy Flemingee0e9172007-08-14 00:14:25 -0500415#define CONFIG_HAS_ETH3
Andy Fleming71706df2007-04-23 02:54:25 -0500416#endif
417
418#define CONFIG_IPADDR 192.168.1.253
419
420#define CONFIG_HOSTNAME unknown
Joe Hershberger257ff782011-10-13 13:03:47 +0000421#define CONFIG_ROOTPATH "/nfsroot"
Joe Hershbergere4da2482011-10-13 13:03:48 +0000422#define CONFIG_BOOTFILE "your.uImage"
Andy Fleming71706df2007-04-23 02:54:25 -0500423
424#define CONFIG_SERVERIP 192.168.1.1
425#define CONFIG_GATEWAYIP 192.168.1.1
426#define CONFIG_NETMASK 255.255.255.0
427
428#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/
429
Andy Fleming71706df2007-04-23 02:54:25 -0500430#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
431
432#define CONFIG_BAUDRATE 115200
433
434#define CONFIG_EXTRA_ENV_SETTINGS \
435 "netdev=eth0\0" \
436 "consoledev=ttyS0\0" \
437 "ramdiskaddr=600000\0" \
438 "ramdiskfile=your.ramdisk.u-boot\0" \
439 "fdtaddr=400000\0" \
440 "fdtfile=your.fdt.dtb\0" \
441 "nfsargs=setenv bootargs root=/dev/nfs rw " \
442 "nfsroot=$serverip:$rootpath " \
443 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
444 "console=$consoledev,$baudrate $othbootargs\0" \
445 "ramargs=setenv bootargs root=/dev/ram rw " \
446 "console=$consoledev,$baudrate $othbootargs\0" \
447
Andy Fleming71706df2007-04-23 02:54:25 -0500448#define CONFIG_NFSBOOTCOMMAND \
449 "run nfsargs;" \
450 "tftp $loadaddr $bootfile;" \
451 "tftp $fdtaddr $fdtfile;" \
452 "bootm $loadaddr - $fdtaddr"
453
Andy Fleming71706df2007-04-23 02:54:25 -0500454#define CONFIG_RAMBOOTCOMMAND \
455 "run ramargs;" \
456 "tftp $ramdiskaddr $ramdiskfile;" \
457 "tftp $loadaddr $bootfile;" \
458 "bootm $loadaddr $ramdiskaddr"
459
460#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
461
462#endif /* __CONFIG_H */