wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 1 | /* |
Kumar Gala | a9db4ec | 2011-01-11 00:52:35 -0600 | [diff] [blame] | 2 | * Copyright 2004, 2011 Freescale Semiconductor. |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 3 | * |
Wolfgang Denk | bd8ec7e | 2013-10-07 13:07:26 +0200 | [diff] [blame] | 4 | * SPDX-License-Identifier: GPL-2.0+ |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | /* |
| 8 | * mpc8541cds board configuration file |
| 9 | * |
| 10 | * Please refer to doc/README.mpc85xxcds for more info. |
| 11 | * |
| 12 | */ |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 13 | #ifndef __CONFIG_H |
| 14 | #define __CONFIG_H |
| 15 | |
| 16 | /* High Level Configuration Options */ |
| 17 | #define CONFIG_BOOKE 1 /* BOOKE */ |
| 18 | #define CONFIG_E500 1 /* BOOKE e500 family */ |
Jon Loeliger | f5ad378 | 2005-07-23 10:37:35 -0500 | [diff] [blame] | 19 | #define CONFIG_CPM2 1 /* has CPM2 */ |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 20 | #define CONFIG_MPC8541 1 /* MPC8541 specific */ |
| 21 | #define CONFIG_MPC8541CDS 1 /* MPC8541CDS board specific */ |
| 22 | |
Wolfgang Denk | 291ba1b | 2010-10-06 09:05:45 +0200 | [diff] [blame] | 23 | #define CONFIG_SYS_TEXT_BASE 0xfff80000 |
| 24 | |
Gabor Juhos | b445873 | 2013-05-30 07:06:12 +0000 | [diff] [blame] | 25 | #define CONFIG_PCI_INDIRECT_BRIDGE |
Kumar Gala | 7738d5c | 2008-10-21 11:33:58 -0500 | [diff] [blame] | 26 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 27 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 28 | #define CONFIG_ENV_OVERWRITE |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 29 | |
Kumar Gala | 35b2b09 | 2008-01-16 01:45:10 -0600 | [diff] [blame] | 30 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 31 | |
Jon Loeliger | 6bcdb40 | 2008-03-19 15:02:07 -0500 | [diff] [blame] | 32 | #define CONFIG_FSL_VIA |
Jon Loeliger | 6bcdb40 | 2008-03-19 15:02:07 -0500 | [diff] [blame] | 33 | |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 34 | #ifndef __ASSEMBLY__ |
| 35 | extern unsigned long get_clock_freq(void); |
| 36 | #endif |
| 37 | #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ |
| 38 | |
| 39 | /* |
| 40 | * These can be toggled for performance analysis, otherwise use default. |
| 41 | */ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 42 | #define CONFIG_L2_CACHE /* toggle L2 cache */ |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 43 | #define CONFIG_BTB /* toggle branch predition */ |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 44 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 45 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ |
| 46 | #define CONFIG_SYS_MEMTEST_END 0x00400000 |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 47 | |
Timur Tabi | d8f341c | 2011-08-04 18:03:41 -0500 | [diff] [blame] | 48 | #define CONFIG_SYS_CCSRBAR 0xe0000000 |
| 49 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 50 | |
Jon Loeliger | 081bc6b | 2008-03-17 15:48:18 -0500 | [diff] [blame] | 51 | /* DDR Setup */ |
York Sun | f062659 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 52 | #define CONFIG_SYS_FSL_DDR1 |
Jon Loeliger | 081bc6b | 2008-03-17 15:48:18 -0500 | [diff] [blame] | 53 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ |
| 54 | #define CONFIG_DDR_SPD |
| 55 | #undef CONFIG_FSL_DDR_INTERACTIVE |
| 56 | |
| 57 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef |
| 58 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 59 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ |
| 60 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 61 | |
Jon Loeliger | 081bc6b | 2008-03-17 15:48:18 -0500 | [diff] [blame] | 62 | #define CONFIG_NUM_DDR_CONTROLLERS 1 |
| 63 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
| 64 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) |
| 65 | |
| 66 | /* I2C addresses of SPD EEPROMs */ |
| 67 | #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 68 | |
| 69 | /* |
| 70 | * Make sure required options are set |
| 71 | */ |
| 72 | #ifndef CONFIG_SPD_EEPROM |
| 73 | #error ("CONFIG_SPD_EEPROM is required by MPC85555CDS") |
| 74 | #endif |
| 75 | |
Jon Loeliger | 3f34a40 | 2005-07-25 11:13:26 -0500 | [diff] [blame] | 76 | #undef CONFIG_CLOCKS_IN_MHZ |
| 77 | |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 78 | /* |
Jon Loeliger | 3f34a40 | 2005-07-25 11:13:26 -0500 | [diff] [blame] | 79 | * Local Bus Definitions |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 80 | */ |
Jon Loeliger | 3f34a40 | 2005-07-25 11:13:26 -0500 | [diff] [blame] | 81 | |
| 82 | /* |
| 83 | * FLASH on the Local Bus |
| 84 | * Two banks, 8M each, using the CFI driver. |
| 85 | * Boot from BR0/OR0 bank at 0xff00_0000 |
| 86 | * Alternate BR1/OR1 bank at 0xff80_0000 |
| 87 | * |
| 88 | * BR0, BR1: |
| 89 | * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 |
| 90 | * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 |
| 91 | * Port Size = 16 bits = BRx[19:20] = 10 |
| 92 | * Use GPCM = BRx[24:26] = 000 |
| 93 | * Valid = BRx[31] = 1 |
| 94 | * |
| 95 | * 0 4 8 12 16 20 24 28 |
| 96 | * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 |
| 97 | * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 |
| 98 | * |
| 99 | * OR0, OR1: |
| 100 | * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 |
| 101 | * Reserved ORx[17:18] = 11, confusion here? |
| 102 | * CSNT = ORx[20] = 1 |
| 103 | * ACS = half cycle delay = ORx[21:22] = 11 |
| 104 | * SCY = 6 = ORx[24:27] = 0110 |
| 105 | * TRLX = use relaxed timing = ORx[29] = 1 |
| 106 | * EAD = use external address latch delay = OR[31] = 1 |
| 107 | * |
| 108 | * 0 4 8 12 16 20 24 28 |
| 109 | * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx |
| 110 | */ |
| 111 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 112 | #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 8M */ |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 113 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 114 | #define CONFIG_SYS_BR0_PRELIM 0xff801001 |
| 115 | #define CONFIG_SYS_BR1_PRELIM 0xff001001 |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 116 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 117 | #define CONFIG_SYS_OR0_PRELIM 0xff806e65 |
| 118 | #define CONFIG_SYS_OR1_PRELIM 0xff806e65 |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 119 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 120 | #define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} |
| 121 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ |
| 122 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ |
| 123 | #undef CONFIG_SYS_FLASH_CHECKSUM |
| 124 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
| 125 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 126 | |
Wolfgang Denk | 0708bc6 | 2010-10-07 21:51:12 +0200 | [diff] [blame] | 127 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 128 | |
Jean-Christophe PLAGNIOL-VILLARD | 8d94c23 | 2008-08-13 01:40:42 +0200 | [diff] [blame] | 129 | #define CONFIG_FLASH_CFI_DRIVER |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 130 | #define CONFIG_SYS_FLASH_CFI |
| 131 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 132 | |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 133 | /* |
Jon Loeliger | 3f34a40 | 2005-07-25 11:13:26 -0500 | [diff] [blame] | 134 | * SDRAM on the Local Bus |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 135 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 136 | #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ |
| 137 | #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 138 | |
| 139 | /* |
| 140 | * Base Register 2 and Option Register 2 configure SDRAM. |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 141 | * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 142 | * |
| 143 | * For BR2, need: |
| 144 | * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 |
| 145 | * port-size = 32-bits = BR2[19:20] = 11 |
| 146 | * no parity checking = BR2[21:22] = 00 |
| 147 | * SDRAM for MSEL = BR2[24:26] = 011 |
| 148 | * Valid = BR[31] = 1 |
| 149 | * |
| 150 | * 0 4 8 12 16 20 24 28 |
| 151 | * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 |
| 152 | * |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 153 | * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 154 | * FIXME: the top 17 bits of BR2. |
| 155 | */ |
| 156 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 157 | #define CONFIG_SYS_BR2_PRELIM 0xf0001861 |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 158 | |
| 159 | /* |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 160 | * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 161 | * |
| 162 | * For OR2, need: |
| 163 | * 64MB mask for AM, OR2[0:7] = 1111 1100 |
| 164 | * XAM, OR2[17:18] = 11 |
| 165 | * 9 columns OR2[19-21] = 010 |
| 166 | * 13 rows OR2[23-25] = 100 |
| 167 | * EAD set for extra time OR[31] = 1 |
| 168 | * |
| 169 | * 0 4 8 12 16 20 24 28 |
| 170 | * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 |
| 171 | */ |
| 172 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 173 | #define CONFIG_SYS_OR2_PRELIM 0xfc006901 |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 174 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 175 | #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ |
| 176 | #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ |
| 177 | #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ |
| 178 | #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 179 | |
| 180 | /* |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 181 | * Common settings for all Local Bus SDRAM commands. |
| 182 | * At run time, either BSMA1516 (for CPU 1.1) |
| 183 | * or BSMA1617 (for CPU 1.0) (old) |
| 184 | * is OR'ed in too. |
| 185 | */ |
Kumar Gala | 727c6a6 | 2009-03-26 01:34:38 -0500 | [diff] [blame] | 186 | #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ |
| 187 | | LSDMR_PRETOACT7 \ |
| 188 | | LSDMR_ACTTORW7 \ |
| 189 | | LSDMR_BL8 \ |
| 190 | | LSDMR_WRC4 \ |
| 191 | | LSDMR_CL3 \ |
| 192 | | LSDMR_RFEN \ |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 193 | ) |
| 194 | |
| 195 | /* |
| 196 | * The CADMUS registers are connected to CS3 on CDS. |
| 197 | * The new memory map places CADMUS at 0xf8000000. |
| 198 | * |
| 199 | * For BR3, need: |
| 200 | * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 |
| 201 | * port-size = 8-bits = BR[19:20] = 01 |
| 202 | * no parity checking = BR[21:22] = 00 |
| 203 | * GPMC for MSEL = BR[24:26] = 000 |
| 204 | * Valid = BR[31] = 1 |
| 205 | * |
| 206 | * 0 4 8 12 16 20 24 28 |
| 207 | * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 |
| 208 | * |
| 209 | * For OR3, need: |
| 210 | * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 |
| 211 | * disable buffer ctrl OR[19] = 0 |
| 212 | * CSNT OR[20] = 1 |
| 213 | * ACS OR[21:22] = 11 |
| 214 | * XACS OR[23] = 1 |
| 215 | * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe |
| 216 | * SETA OR[28] = 0 |
| 217 | * TRLX OR[29] = 1 |
| 218 | * EHTR OR[30] = 1 |
| 219 | * EAD extra time OR[31] = 1 |
| 220 | * |
| 221 | * 0 4 8 12 16 20 24 28 |
| 222 | * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 |
| 223 | */ |
| 224 | |
Jon Loeliger | 6bcdb40 | 2008-03-19 15:02:07 -0500 | [diff] [blame] | 225 | #define CONFIG_FSL_CADMUS |
| 226 | |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 227 | #define CADMUS_BASE_ADDR 0xf8000000 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 228 | #define CONFIG_SYS_BR3_PRELIM 0xf8000801 |
| 229 | #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 230 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 231 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
| 232 | #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ |
Wolfgang Denk | 1c2e98e | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 233 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 234 | |
Wolfgang Denk | 0191e47 | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 235 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 236 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 237 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 238 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
| 239 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 240 | |
| 241 | /* Serial Port */ |
| 242 | #define CONFIG_CONS_INDEX 2 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 243 | #define CONFIG_SYS_NS16550_SERIAL |
| 244 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
| 245 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 246 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 247 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 248 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
| 249 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 250 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
| 251 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 252 | |
Jon Loeliger | 43d818f | 2006-10-20 15:50:15 -0500 | [diff] [blame] | 253 | /* |
| 254 | * I2C |
| 255 | */ |
Heiko Schocher | f285074 | 2012-10-24 13:48:22 +0200 | [diff] [blame] | 256 | #define CONFIG_SYS_I2C |
| 257 | #define CONFIG_SYS_I2C_FSL |
| 258 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 |
| 259 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F |
| 260 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 |
| 261 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 262 | |
Timur Tabi | 0b87d3f | 2008-07-18 16:52:23 +0200 | [diff] [blame] | 263 | /* EEPROM */ |
| 264 | #define CONFIG_ID_EEPROM |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 265 | #define CONFIG_SYS_I2C_EEPROM_CCID |
| 266 | #define CONFIG_SYS_ID_EEPROM |
| 267 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 |
| 268 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 |
Timur Tabi | 0b87d3f | 2008-07-18 16:52:23 +0200 | [diff] [blame] | 269 | |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 270 | /* |
| 271 | * General PCI |
Sergei Shtylyov | 6ffad93 | 2006-12-27 22:07:15 +0300 | [diff] [blame] | 272 | * Memory space is mapped 1-1, but I/O space must start from 0. |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 273 | */ |
Kumar Gala | ef43b6e | 2008-12-02 16:08:39 -0600 | [diff] [blame] | 274 | #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 |
Kumar Gala | 3fe8087 | 2008-12-02 16:08:36 -0600 | [diff] [blame] | 275 | #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 |
Kumar Gala | ef43b6e | 2008-12-02 16:08:39 -0600 | [diff] [blame] | 276 | #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 277 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ |
Kumar Gala | 60ff464 | 2008-12-02 16:08:40 -0600 | [diff] [blame] | 278 | #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 |
Kumar Gala | 64bb6d1 | 2008-12-02 16:08:37 -0600 | [diff] [blame] | 279 | #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 280 | #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 |
| 281 | #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 282 | |
Kumar Gala | ef43b6e | 2008-12-02 16:08:39 -0600 | [diff] [blame] | 283 | #define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000 |
Kumar Gala | 3fe8087 | 2008-12-02 16:08:36 -0600 | [diff] [blame] | 284 | #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 |
Kumar Gala | ef43b6e | 2008-12-02 16:08:39 -0600 | [diff] [blame] | 285 | #define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 286 | #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ |
Kumar Gala | 60ff464 | 2008-12-02 16:08:40 -0600 | [diff] [blame] | 287 | #define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000 |
Kumar Gala | 64bb6d1 | 2008-12-02 16:08:37 -0600 | [diff] [blame] | 288 | #define CONFIG_SYS_PCI2_IO_BUS 0x00000000 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 289 | #define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000 |
| 290 | #define CONFIG_SYS_PCI2_IO_SIZE 0x100000 /* 1M */ |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 291 | |
Randy Vinson | 1dfd6d9 | 2007-02-27 19:42:22 -0700 | [diff] [blame] | 292 | #ifdef CONFIG_LEGACY |
| 293 | #define BRIDGE_ID 17 |
| 294 | #define VIA_ID 2 |
| 295 | #else |
| 296 | #define BRIDGE_ID 28 |
| 297 | #define VIA_ID 4 |
| 298 | #endif |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 299 | |
| 300 | #if defined(CONFIG_PCI) |
| 301 | |
Matthew McClintock | aa6dd06 | 2006-06-28 10:46:13 -0500 | [diff] [blame] | 302 | #define CONFIG_MPC85XX_PCI2 |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 303 | |
| 304 | #undef CONFIG_EEPRO100 |
| 305 | #undef CONFIG_TULIP |
| 306 | |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 307 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 308 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 309 | |
| 310 | #endif /* CONFIG_PCI */ |
| 311 | |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 312 | #if defined(CONFIG_TSEC_ENET) |
| 313 | |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 314 | #define CONFIG_MII 1 /* MII PHY management */ |
Kim Phillips | 177e58f | 2007-05-16 16:52:19 -0500 | [diff] [blame] | 315 | #define CONFIG_TSEC1 1 |
| 316 | #define CONFIG_TSEC1_NAME "TSEC0" |
| 317 | #define CONFIG_TSEC2 1 |
| 318 | #define CONFIG_TSEC2_NAME "TSEC1" |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 319 | #define TSEC1_PHY_ADDR 0 |
| 320 | #define TSEC2_PHY_ADDR 1 |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 321 | #define TSEC1_PHYIDX 0 |
| 322 | #define TSEC2_PHYIDX 0 |
Andy Fleming | 09b88df | 2007-08-15 20:03:25 -0500 | [diff] [blame] | 323 | #define TSEC1_FLAGS TSEC_GIGABIT |
| 324 | #define TSEC2_FLAGS TSEC_GIGABIT |
Jon Loeliger | 77a4f6e | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 325 | |
| 326 | /* Options are: TSEC[0-1] */ |
| 327 | #define CONFIG_ETHPRIME "TSEC0" |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 328 | |
| 329 | #endif /* CONFIG_TSEC_ENET */ |
| 330 | |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 331 | /* |
| 332 | * Environment |
| 333 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 53db4cd | 2008-09-10 22:48:04 +0200 | [diff] [blame] | 334 | #define CONFIG_ENV_IS_IN_FLASH 1 |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 335 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 336 | #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ |
| 337 | #define CONFIG_ENV_SIZE 0x2000 |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 338 | |
| 339 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 340 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 341 | |
Jon Loeliger | e63319f | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 342 | /* |
Jon Loeliger | ed26c74 | 2007-07-10 09:10:49 -0500 | [diff] [blame] | 343 | * BOOTP options |
| 344 | */ |
| 345 | #define CONFIG_BOOTP_BOOTFILESIZE |
| 346 | #define CONFIG_BOOTP_BOOTPATH |
| 347 | #define CONFIG_BOOTP_GATEWAY |
| 348 | #define CONFIG_BOOTP_HOSTNAME |
| 349 | |
Jon Loeliger | ed26c74 | 2007-07-10 09:10:49 -0500 | [diff] [blame] | 350 | /* |
Jon Loeliger | e63319f | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 351 | * Command line configuration. |
| 352 | */ |
Kumar Gala | 489675d | 2008-09-22 23:40:42 -0500 | [diff] [blame] | 353 | #define CONFIG_CMD_IRQ |
Becky Bruce | ee888da | 2010-06-17 11:37:25 -0500 | [diff] [blame] | 354 | #define CONFIG_CMD_REGINFO |
Jon Loeliger | e63319f | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 355 | |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 356 | #if defined(CONFIG_PCI) |
Jon Loeliger | e63319f | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 357 | #define CONFIG_CMD_PCI |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 358 | #endif |
Jon Loeliger | e63319f | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 359 | |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 360 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
| 361 | |
| 362 | /* |
| 363 | * Miscellaneous configurable options |
| 364 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 365 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
Kim Phillips | f7758c1 | 2010-07-14 19:47:18 -0500 | [diff] [blame] | 366 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
| 367 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 368 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
Jon Loeliger | e63319f | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 369 | #if defined(CONFIG_CMD_KGDB) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 370 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 371 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 372 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 373 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 374 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 375 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| 376 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 377 | |
| 378 | /* |
| 379 | * For booting Linux, the board info and command line data |
Kumar Gala | 39ffcc1 | 2011-04-28 10:13:41 -0500 | [diff] [blame] | 380 | * have to be in the first 64 MB of memory, since this is |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 381 | * the maximum mapped by the Linux kernel during initialization. |
| 382 | */ |
Kumar Gala | 39ffcc1 | 2011-04-28 10:13:41 -0500 | [diff] [blame] | 383 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ |
| 384 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 385 | |
Jon Loeliger | e63319f | 2007-06-13 13:22:08 -0500 | [diff] [blame] | 386 | #if defined(CONFIG_CMD_KGDB) |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 387 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 388 | #endif |
| 389 | |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 390 | /* |
| 391 | * Environment Configuration |
| 392 | */ |
| 393 | |
| 394 | /* The mac addresses for all ethernet interface */ |
| 395 | #if defined(CONFIG_TSEC_ENET) |
Andy Fleming | 458c389 | 2007-08-16 16:35:02 -0500 | [diff] [blame] | 396 | #define CONFIG_HAS_ETH0 |
wdenk | 54070ab | 2004-12-31 09:32:47 +0000 | [diff] [blame] | 397 | #define CONFIG_HAS_ETH1 |
wdenk | 54070ab | 2004-12-31 09:32:47 +0000 | [diff] [blame] | 398 | #define CONFIG_HAS_ETH2 |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 399 | #endif |
| 400 | |
| 401 | #define CONFIG_IPADDR 192.168.1.253 |
| 402 | |
| 403 | #define CONFIG_HOSTNAME unknown |
Joe Hershberger | 257ff78 | 2011-10-13 13:03:47 +0000 | [diff] [blame] | 404 | #define CONFIG_ROOTPATH "/nfsroot" |
Joe Hershberger | e4da248 | 2011-10-13 13:03:48 +0000 | [diff] [blame] | 405 | #define CONFIG_BOOTFILE "your.uImage" |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 406 | |
| 407 | #define CONFIG_SERVERIP 192.168.1.1 |
| 408 | #define CONFIG_GATEWAYIP 192.168.1.1 |
| 409 | #define CONFIG_NETMASK 255.255.255.0 |
| 410 | |
| 411 | #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ |
| 412 | |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 413 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ |
| 414 | |
| 415 | #define CONFIG_BAUDRATE 115200 |
| 416 | |
| 417 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 418 | "netdev=eth0\0" \ |
| 419 | "consoledev=ttyS1\0" \ |
Andy Fleming | 7243f97 | 2006-09-13 10:33:35 -0500 | [diff] [blame] | 420 | "ramdiskaddr=600000\0" \ |
| 421 | "ramdiskfile=your.ramdisk.u-boot\0" \ |
| 422 | "fdtaddr=400000\0" \ |
| 423 | "fdtfile=your.fdt.dtb\0" |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 424 | |
| 425 | #define CONFIG_NFSBOOTCOMMAND \ |
| 426 | "setenv bootargs root=/dev/nfs rw " \ |
| 427 | "nfsroot=$serverip:$rootpath " \ |
| 428 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ |
| 429 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 430 | "tftp $loadaddr $bootfile;" \ |
Andy Fleming | 7243f97 | 2006-09-13 10:33:35 -0500 | [diff] [blame] | 431 | "tftp $fdtaddr $fdtfile;" \ |
| 432 | "bootm $loadaddr - $fdtaddr" |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 433 | |
| 434 | #define CONFIG_RAMBOOTCOMMAND \ |
| 435 | "setenv bootargs root=/dev/ram rw " \ |
| 436 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 437 | "tftp $ramdiskaddr $ramdiskfile;" \ |
| 438 | "tftp $loadaddr $bootfile;" \ |
| 439 | "bootm $loadaddr $ramdiskaddr" |
| 440 | |
| 441 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND |
| 442 | |
wdenk | 0aeb853 | 2004-10-10 21:21:55 +0000 | [diff] [blame] | 443 | #endif /* __CONFIG_H */ |