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wdenk0aeb8532004-10-10 21:21:55 +00001/*
Kumar Galaa9db4ec2011-01-11 00:52:35 -06002 * Copyright 2004, 2011 Freescale Semiconductor.
wdenk0aeb8532004-10-10 21:21:55 +00003 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +02004 * SPDX-License-Identifier: GPL-2.0+
wdenk0aeb8532004-10-10 21:21:55 +00005 */
6
7/*
8 * mpc8541cds board configuration file
9 *
10 * Please refer to doc/README.mpc85xxcds for more info.
11 *
12 */
wdenk0aeb8532004-10-10 21:21:55 +000013#ifndef __CONFIG_H
14#define __CONFIG_H
15
16/* High Level Configuration Options */
17#define CONFIG_BOOKE 1 /* BOOKE */
18#define CONFIG_E500 1 /* BOOKE e500 family */
Jon Loeligerf5ad3782005-07-23 10:37:35 -050019#define CONFIG_CPM2 1 /* has CPM2 */
wdenk0aeb8532004-10-10 21:21:55 +000020#define CONFIG_MPC8541 1 /* MPC8541 specific */
21#define CONFIG_MPC8541CDS 1 /* MPC8541CDS board specific */
22
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020023#define CONFIG_SYS_TEXT_BASE 0xfff80000
24
Gabor Juhosb4458732013-05-30 07:06:12 +000025#define CONFIG_PCI_INDIRECT_BRIDGE
Kumar Gala7738d5c2008-10-21 11:33:58 -050026#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Wolfgang Denka1be4762008-05-20 16:00:29 +020027#define CONFIG_TSEC_ENET /* tsec ethernet support */
wdenk0aeb8532004-10-10 21:21:55 +000028#define CONFIG_ENV_OVERWRITE
Jon Loeliger77a4f6e2005-07-25 14:05:07 -050029
Kumar Gala35b2b092008-01-16 01:45:10 -060030#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
wdenk0aeb8532004-10-10 21:21:55 +000031
Jon Loeliger6bcdb402008-03-19 15:02:07 -050032#define CONFIG_FSL_VIA
Jon Loeliger6bcdb402008-03-19 15:02:07 -050033
wdenk0aeb8532004-10-10 21:21:55 +000034#ifndef __ASSEMBLY__
35extern unsigned long get_clock_freq(void);
36#endif
37#define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */
38
39/*
40 * These can be toggled for performance analysis, otherwise use default.
41 */
Wolfgang Denka1be4762008-05-20 16:00:29 +020042#define CONFIG_L2_CACHE /* toggle L2 cache */
wdenk0aeb8532004-10-10 21:21:55 +000043#define CONFIG_BTB /* toggle branch predition */
wdenk0aeb8532004-10-10 21:21:55 +000044
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020045#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
46#define CONFIG_SYS_MEMTEST_END 0x00400000
wdenk0aeb8532004-10-10 21:21:55 +000047
Timur Tabid8f341c2011-08-04 18:03:41 -050048#define CONFIG_SYS_CCSRBAR 0xe0000000
49#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
wdenk0aeb8532004-10-10 21:21:55 +000050
Jon Loeliger081bc6b2008-03-17 15:48:18 -050051/* DDR Setup */
York Sunf0626592013-09-30 09:22:09 -070052#define CONFIG_SYS_FSL_DDR1
Jon Loeliger081bc6b2008-03-17 15:48:18 -050053#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
54#define CONFIG_DDR_SPD
55#undef CONFIG_FSL_DDR_INTERACTIVE
56
57#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
58
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020059#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
60#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
wdenk0aeb8532004-10-10 21:21:55 +000061
Jon Loeliger081bc6b2008-03-17 15:48:18 -050062#define CONFIG_NUM_DDR_CONTROLLERS 1
63#define CONFIG_DIMM_SLOTS_PER_CTLR 1
64#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
65
66/* I2C addresses of SPD EEPROMs */
67#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
wdenk0aeb8532004-10-10 21:21:55 +000068
69/*
70 * Make sure required options are set
71 */
72#ifndef CONFIG_SPD_EEPROM
73#error ("CONFIG_SPD_EEPROM is required by MPC85555CDS")
74#endif
75
Jon Loeliger3f34a402005-07-25 11:13:26 -050076#undef CONFIG_CLOCKS_IN_MHZ
77
wdenk0aeb8532004-10-10 21:21:55 +000078/*
Jon Loeliger3f34a402005-07-25 11:13:26 -050079 * Local Bus Definitions
wdenk0aeb8532004-10-10 21:21:55 +000080 */
Jon Loeliger3f34a402005-07-25 11:13:26 -050081
82/*
83 * FLASH on the Local Bus
84 * Two banks, 8M each, using the CFI driver.
85 * Boot from BR0/OR0 bank at 0xff00_0000
86 * Alternate BR1/OR1 bank at 0xff80_0000
87 *
88 * BR0, BR1:
89 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
90 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
91 * Port Size = 16 bits = BRx[19:20] = 10
92 * Use GPCM = BRx[24:26] = 000
93 * Valid = BRx[31] = 1
94 *
95 * 0 4 8 12 16 20 24 28
96 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
97 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
98 *
99 * OR0, OR1:
100 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
101 * Reserved ORx[17:18] = 11, confusion here?
102 * CSNT = ORx[20] = 1
103 * ACS = half cycle delay = ORx[21:22] = 11
104 * SCY = 6 = ORx[24:27] = 0110
105 * TRLX = use relaxed timing = ORx[29] = 1
106 * EAD = use external address latch delay = OR[31] = 1
107 *
108 * 0 4 8 12 16 20 24 28
109 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
110 */
111
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200112#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 8M */
wdenk0aeb8532004-10-10 21:21:55 +0000113
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200114#define CONFIG_SYS_BR0_PRELIM 0xff801001
115#define CONFIG_SYS_BR1_PRELIM 0xff001001
wdenk0aeb8532004-10-10 21:21:55 +0000116
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200117#define CONFIG_SYS_OR0_PRELIM 0xff806e65
118#define CONFIG_SYS_OR1_PRELIM 0xff806e65
wdenk0aeb8532004-10-10 21:21:55 +0000119
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200120#define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE}
121#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
122#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
123#undef CONFIG_SYS_FLASH_CHECKSUM
124#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
125#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
wdenk0aeb8532004-10-10 21:21:55 +0000126
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200127#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
wdenk0aeb8532004-10-10 21:21:55 +0000128
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +0200129#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200130#define CONFIG_SYS_FLASH_CFI
131#define CONFIG_SYS_FLASH_EMPTY_INFO
wdenk0aeb8532004-10-10 21:21:55 +0000132
wdenk0aeb8532004-10-10 21:21:55 +0000133/*
Jon Loeliger3f34a402005-07-25 11:13:26 -0500134 * SDRAM on the Local Bus
wdenk0aeb8532004-10-10 21:21:55 +0000135 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200136#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
137#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
wdenk0aeb8532004-10-10 21:21:55 +0000138
139/*
140 * Base Register 2 and Option Register 2 configure SDRAM.
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200141 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
wdenk0aeb8532004-10-10 21:21:55 +0000142 *
143 * For BR2, need:
144 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
145 * port-size = 32-bits = BR2[19:20] = 11
146 * no parity checking = BR2[21:22] = 00
147 * SDRAM for MSEL = BR2[24:26] = 011
148 * Valid = BR[31] = 1
149 *
150 * 0 4 8 12 16 20 24 28
151 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
152 *
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200153 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
wdenk0aeb8532004-10-10 21:21:55 +0000154 * FIXME: the top 17 bits of BR2.
155 */
156
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200157#define CONFIG_SYS_BR2_PRELIM 0xf0001861
wdenk0aeb8532004-10-10 21:21:55 +0000158
159/*
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200160 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
wdenk0aeb8532004-10-10 21:21:55 +0000161 *
162 * For OR2, need:
163 * 64MB mask for AM, OR2[0:7] = 1111 1100
164 * XAM, OR2[17:18] = 11
165 * 9 columns OR2[19-21] = 010
166 * 13 rows OR2[23-25] = 100
167 * EAD set for extra time OR[31] = 1
168 *
169 * 0 4 8 12 16 20 24 28
170 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
171 */
172
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200173#define CONFIG_SYS_OR2_PRELIM 0xfc006901
wdenk0aeb8532004-10-10 21:21:55 +0000174
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200175#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
176#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
177#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
178#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
wdenk0aeb8532004-10-10 21:21:55 +0000179
180/*
wdenk0aeb8532004-10-10 21:21:55 +0000181 * Common settings for all Local Bus SDRAM commands.
182 * At run time, either BSMA1516 (for CPU 1.1)
183 * or BSMA1617 (for CPU 1.0) (old)
184 * is OR'ed in too.
185 */
Kumar Gala727c6a62009-03-26 01:34:38 -0500186#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
187 | LSDMR_PRETOACT7 \
188 | LSDMR_ACTTORW7 \
189 | LSDMR_BL8 \
190 | LSDMR_WRC4 \
191 | LSDMR_CL3 \
192 | LSDMR_RFEN \
wdenk0aeb8532004-10-10 21:21:55 +0000193 )
194
195/*
196 * The CADMUS registers are connected to CS3 on CDS.
197 * The new memory map places CADMUS at 0xf8000000.
198 *
199 * For BR3, need:
200 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
201 * port-size = 8-bits = BR[19:20] = 01
202 * no parity checking = BR[21:22] = 00
203 * GPMC for MSEL = BR[24:26] = 000
204 * Valid = BR[31] = 1
205 *
206 * 0 4 8 12 16 20 24 28
207 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
208 *
209 * For OR3, need:
210 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
211 * disable buffer ctrl OR[19] = 0
212 * CSNT OR[20] = 1
213 * ACS OR[21:22] = 11
214 * XACS OR[23] = 1
215 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
216 * SETA OR[28] = 0
217 * TRLX OR[29] = 1
218 * EHTR OR[30] = 1
219 * EAD extra time OR[31] = 1
220 *
221 * 0 4 8 12 16 20 24 28
222 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
223 */
224
Jon Loeliger6bcdb402008-03-19 15:02:07 -0500225#define CONFIG_FSL_CADMUS
226
wdenk0aeb8532004-10-10 21:21:55 +0000227#define CADMUS_BASE_ADDR 0xf8000000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200228#define CONFIG_SYS_BR3_PRELIM 0xf8000801
229#define CONFIG_SYS_OR3_PRELIM 0xfff00ff7
wdenk0aeb8532004-10-10 21:21:55 +0000230
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200231#define CONFIG_SYS_INIT_RAM_LOCK 1
232#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200233#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
wdenk0aeb8532004-10-10 21:21:55 +0000234
Wolfgang Denk0191e472010-10-26 14:34:52 +0200235#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200236#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk0aeb8532004-10-10 21:21:55 +0000237
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200238#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
239#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
wdenk0aeb8532004-10-10 21:21:55 +0000240
241/* Serial Port */
242#define CONFIG_CONS_INDEX 2
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200243#define CONFIG_SYS_NS16550_SERIAL
244#define CONFIG_SYS_NS16550_REG_SIZE 1
245#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
wdenk0aeb8532004-10-10 21:21:55 +0000246
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200247#define CONFIG_SYS_BAUDRATE_TABLE \
wdenk0aeb8532004-10-10 21:21:55 +0000248 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
249
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200250#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
251#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
wdenk0aeb8532004-10-10 21:21:55 +0000252
Jon Loeliger43d818f2006-10-20 15:50:15 -0500253/*
254 * I2C
255 */
Heiko Schocherf2850742012-10-24 13:48:22 +0200256#define CONFIG_SYS_I2C
257#define CONFIG_SYS_I2C_FSL
258#define CONFIG_SYS_FSL_I2C_SPEED 400000
259#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
260#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
261#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
wdenk0aeb8532004-10-10 21:21:55 +0000262
Timur Tabi0b87d3f2008-07-18 16:52:23 +0200263/* EEPROM */
264#define CONFIG_ID_EEPROM
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200265#define CONFIG_SYS_I2C_EEPROM_CCID
266#define CONFIG_SYS_ID_EEPROM
267#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
268#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
Timur Tabi0b87d3f2008-07-18 16:52:23 +0200269
wdenk0aeb8532004-10-10 21:21:55 +0000270/*
271 * General PCI
Sergei Shtylyov6ffad932006-12-27 22:07:15 +0300272 * Memory space is mapped 1-1, but I/O space must start from 0.
wdenk0aeb8532004-10-10 21:21:55 +0000273 */
Kumar Galaef43b6e2008-12-02 16:08:39 -0600274#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
Kumar Gala3fe80872008-12-02 16:08:36 -0600275#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
Kumar Galaef43b6e2008-12-02 16:08:39 -0600276#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200277#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
Kumar Gala60ff4642008-12-02 16:08:40 -0600278#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
Kumar Gala64bb6d12008-12-02 16:08:37 -0600279#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200280#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
281#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
wdenk0aeb8532004-10-10 21:21:55 +0000282
Kumar Galaef43b6e2008-12-02 16:08:39 -0600283#define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000
Kumar Gala3fe80872008-12-02 16:08:36 -0600284#define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000
Kumar Galaef43b6e2008-12-02 16:08:39 -0600285#define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200286#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
Kumar Gala60ff4642008-12-02 16:08:40 -0600287#define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000
Kumar Gala64bb6d12008-12-02 16:08:37 -0600288#define CONFIG_SYS_PCI2_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200289#define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000
290#define CONFIG_SYS_PCI2_IO_SIZE 0x100000 /* 1M */
wdenk0aeb8532004-10-10 21:21:55 +0000291
Randy Vinson1dfd6d92007-02-27 19:42:22 -0700292#ifdef CONFIG_LEGACY
293#define BRIDGE_ID 17
294#define VIA_ID 2
295#else
296#define BRIDGE_ID 28
297#define VIA_ID 4
298#endif
wdenk0aeb8532004-10-10 21:21:55 +0000299
300#if defined(CONFIG_PCI)
301
Matthew McClintockaa6dd062006-06-28 10:46:13 -0500302#define CONFIG_MPC85XX_PCI2
wdenk0aeb8532004-10-10 21:21:55 +0000303
304#undef CONFIG_EEPRO100
305#undef CONFIG_TULIP
306
wdenk0aeb8532004-10-10 21:21:55 +0000307#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200308#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
wdenk0aeb8532004-10-10 21:21:55 +0000309
310#endif /* CONFIG_PCI */
311
wdenk0aeb8532004-10-10 21:21:55 +0000312#if defined(CONFIG_TSEC_ENET)
313
wdenk0aeb8532004-10-10 21:21:55 +0000314#define CONFIG_MII 1 /* MII PHY management */
Kim Phillips177e58f2007-05-16 16:52:19 -0500315#define CONFIG_TSEC1 1
316#define CONFIG_TSEC1_NAME "TSEC0"
317#define CONFIG_TSEC2 1
318#define CONFIG_TSEC2_NAME "TSEC1"
wdenk0aeb8532004-10-10 21:21:55 +0000319#define TSEC1_PHY_ADDR 0
320#define TSEC2_PHY_ADDR 1
wdenk0aeb8532004-10-10 21:21:55 +0000321#define TSEC1_PHYIDX 0
322#define TSEC2_PHYIDX 0
Andy Fleming09b88df2007-08-15 20:03:25 -0500323#define TSEC1_FLAGS TSEC_GIGABIT
324#define TSEC2_FLAGS TSEC_GIGABIT
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500325
326/* Options are: TSEC[0-1] */
327#define CONFIG_ETHPRIME "TSEC0"
wdenk0aeb8532004-10-10 21:21:55 +0000328
329#endif /* CONFIG_TSEC_ENET */
330
wdenk0aeb8532004-10-10 21:21:55 +0000331/*
332 * Environment
333 */
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200334#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200335#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200336#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
337#define CONFIG_ENV_SIZE 0x2000
wdenk0aeb8532004-10-10 21:21:55 +0000338
339#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200340#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenk0aeb8532004-10-10 21:21:55 +0000341
Jon Loeligere63319f2007-06-13 13:22:08 -0500342/*
Jon Loeligered26c742007-07-10 09:10:49 -0500343 * BOOTP options
344 */
345#define CONFIG_BOOTP_BOOTFILESIZE
346#define CONFIG_BOOTP_BOOTPATH
347#define CONFIG_BOOTP_GATEWAY
348#define CONFIG_BOOTP_HOSTNAME
349
Jon Loeligered26c742007-07-10 09:10:49 -0500350/*
Jon Loeligere63319f2007-06-13 13:22:08 -0500351 * Command line configuration.
352 */
Kumar Gala489675d2008-09-22 23:40:42 -0500353#define CONFIG_CMD_IRQ
Becky Bruceee888da2010-06-17 11:37:25 -0500354#define CONFIG_CMD_REGINFO
Jon Loeligere63319f2007-06-13 13:22:08 -0500355
wdenk0aeb8532004-10-10 21:21:55 +0000356#if defined(CONFIG_PCI)
Jon Loeligere63319f2007-06-13 13:22:08 -0500357 #define CONFIG_CMD_PCI
wdenk0aeb8532004-10-10 21:21:55 +0000358#endif
Jon Loeligere63319f2007-06-13 13:22:08 -0500359
wdenk0aeb8532004-10-10 21:21:55 +0000360#undef CONFIG_WATCHDOG /* watchdog disabled */
361
362/*
363 * Miscellaneous configurable options
364 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200365#define CONFIG_SYS_LONGHELP /* undef to save memory */
Kim Phillipsf7758c12010-07-14 19:47:18 -0500366#define CONFIG_CMDLINE_EDITING /* Command-line editing */
367#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200368#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Jon Loeligere63319f2007-06-13 13:22:08 -0500369#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200370#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk0aeb8532004-10-10 21:21:55 +0000371#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200372#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk0aeb8532004-10-10 21:21:55 +0000373#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200374#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
375#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
376#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk0aeb8532004-10-10 21:21:55 +0000377
378/*
379 * For booting Linux, the board info and command line data
Kumar Gala39ffcc12011-04-28 10:13:41 -0500380 * have to be in the first 64 MB of memory, since this is
wdenk0aeb8532004-10-10 21:21:55 +0000381 * the maximum mapped by the Linux kernel during initialization.
382 */
Kumar Gala39ffcc12011-04-28 10:13:41 -0500383#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
384#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
wdenk0aeb8532004-10-10 21:21:55 +0000385
Jon Loeligere63319f2007-06-13 13:22:08 -0500386#if defined(CONFIG_CMD_KGDB)
wdenk0aeb8532004-10-10 21:21:55 +0000387#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
wdenk0aeb8532004-10-10 21:21:55 +0000388#endif
389
wdenk0aeb8532004-10-10 21:21:55 +0000390/*
391 * Environment Configuration
392 */
393
394/* The mac addresses for all ethernet interface */
395#if defined(CONFIG_TSEC_ENET)
Andy Fleming458c3892007-08-16 16:35:02 -0500396#define CONFIG_HAS_ETH0
wdenk54070ab2004-12-31 09:32:47 +0000397#define CONFIG_HAS_ETH1
wdenk54070ab2004-12-31 09:32:47 +0000398#define CONFIG_HAS_ETH2
wdenk0aeb8532004-10-10 21:21:55 +0000399#endif
400
401#define CONFIG_IPADDR 192.168.1.253
402
403#define CONFIG_HOSTNAME unknown
Joe Hershberger257ff782011-10-13 13:03:47 +0000404#define CONFIG_ROOTPATH "/nfsroot"
Joe Hershbergere4da2482011-10-13 13:03:48 +0000405#define CONFIG_BOOTFILE "your.uImage"
wdenk0aeb8532004-10-10 21:21:55 +0000406
407#define CONFIG_SERVERIP 192.168.1.1
408#define CONFIG_GATEWAYIP 192.168.1.1
409#define CONFIG_NETMASK 255.255.255.0
410
411#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/
412
wdenk0aeb8532004-10-10 21:21:55 +0000413#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
414
415#define CONFIG_BAUDRATE 115200
416
417#define CONFIG_EXTRA_ENV_SETTINGS \
418 "netdev=eth0\0" \
419 "consoledev=ttyS1\0" \
Andy Fleming7243f972006-09-13 10:33:35 -0500420 "ramdiskaddr=600000\0" \
421 "ramdiskfile=your.ramdisk.u-boot\0" \
422 "fdtaddr=400000\0" \
423 "fdtfile=your.fdt.dtb\0"
wdenk0aeb8532004-10-10 21:21:55 +0000424
425#define CONFIG_NFSBOOTCOMMAND \
426 "setenv bootargs root=/dev/nfs rw " \
427 "nfsroot=$serverip:$rootpath " \
428 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
429 "console=$consoledev,$baudrate $othbootargs;" \
430 "tftp $loadaddr $bootfile;" \
Andy Fleming7243f972006-09-13 10:33:35 -0500431 "tftp $fdtaddr $fdtfile;" \
432 "bootm $loadaddr - $fdtaddr"
wdenk0aeb8532004-10-10 21:21:55 +0000433
434#define CONFIG_RAMBOOTCOMMAND \
435 "setenv bootargs root=/dev/ram rw " \
436 "console=$consoledev,$baudrate $othbootargs;" \
437 "tftp $ramdiskaddr $ramdiskfile;" \
438 "tftp $loadaddr $bootfile;" \
439 "bootm $loadaddr $ramdiskaddr"
440
441#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
442
wdenk0aeb8532004-10-10 21:21:55 +0000443#endif /* __CONFIG_H */