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wdenkc6097192002-11-03 00:24:07 +00001/*
stroesea9484a92004-12-16 18:05:42 +00002 * (C) Copyright 2001-2004
wdenkc6097192002-11-03 00:24:07 +00003 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenkc6097192002-11-03 00:24:07 +00006 */
7
8/*
9 * board/config.h - configuration options, board specific
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/*
16 * High Level Configuration Options
17 * (easy to change)
18 */
19
20#define CONFIG_405GP 1 /* This is a PPC405 CPU */
wdenkc6097192002-11-03 00:24:07 +000021#define CONFIG_CPCI405 1 /* ...on a CPCI405 board */
wdenkda55c6e2004-01-20 23:12:12 +000022#define CONFIG_CPCI405_VER2 1 /* ...version 2 */
Matthias Fuchs196088b2007-06-24 17:41:21 +020023#undef CONFIG_CPCI405_6U /* enable this for 6U boards */
wdenkc6097192002-11-03 00:24:07 +000024
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020025#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
26
wdenkda55c6e2004-01-20 23:12:12 +000027#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
Peter Tyser5c506212009-09-16 22:03:07 -050028#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
wdenkc6097192002-11-03 00:24:07 +000029
stroesea9484a92004-12-16 18:05:42 +000030#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
wdenkc6097192002-11-03 00:24:07 +000031
32#define CONFIG_BAUDRATE 9600
wdenkc6097192002-11-03 00:24:07 +000033
wdenkc6097192002-11-03 00:24:07 +000034#undef CONFIG_BOOTARGS
stroesea9484a92004-12-16 18:05:42 +000035#undef CONFIG_BOOTCOMMAND
36
37#define CONFIG_PREBOOT /* enable preboot variable */
wdenkc6097192002-11-03 00:24:07 +000038
39#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020040#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenkc6097192002-11-03 00:24:07 +000041
Ben Warren3a918a62008-10-27 23:50:15 -070042#define CONFIG_PPC4xx_EMAC
wdenkc6097192002-11-03 00:24:07 +000043#define CONFIG_MII 1 /* MII PHY management */
wdenkda55c6e2004-01-20 23:12:12 +000044#define CONFIG_PHY_ADDR 0 /* PHY address */
stroesea9484a92004-12-16 18:05:42 +000045#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
Matthias Fuchs196088b2007-06-24 17:41:21 +020046#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
47
Matthias Fuchs196088b2007-06-24 17:41:21 +020048#undef CONFIG_HAS_ETH1
wdenkc6097192002-11-03 00:24:07 +000049
50#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
51
Jon Loeliger1cb2cb62007-07-09 21:16:53 -050052/*
53 * BOOTP options
54 */
55#define CONFIG_BOOTP_SUBNETMASK
56#define CONFIG_BOOTP_GATEWAY
57#define CONFIG_BOOTP_HOSTNAME
58#define CONFIG_BOOTP_BOOTPATH
59#define CONFIG_BOOTP_DNS
60#define CONFIG_BOOTP_DNS2
61#define CONFIG_BOOTP_SEND_HOSTNAME
62
Jon Loeliger8c5f4a42007-07-05 19:52:35 -050063/*
64 * Command line configuration.
65 */
Jon Loeliger8c5f4a42007-07-05 19:52:35 -050066#define CONFIG_CMD_PCI
67#define CONFIG_CMD_IRQ
68#define CONFIG_CMD_IDE
Jon Loeliger8c5f4a42007-07-05 19:52:35 -050069#define CONFIG_CMD_DATE
Jon Loeliger8c5f4a42007-07-05 19:52:35 -050070#define CONFIG_CMD_BSP
71#define CONFIG_CMD_EEPROM
72
wdenkc6097192002-11-03 00:24:07 +000073#define CONFIG_MAC_PARTITION
74#define CONFIG_DOS_PARTITION
75
stroesea9484a92004-12-16 18:05:42 +000076#define CONFIG_SUPPORT_VFAT
77
wdenkda55c6e2004-01-20 23:12:12 +000078#undef CONFIG_WATCHDOG /* watchdog disabled */
wdenkc6097192002-11-03 00:24:07 +000079
wdenkda55c6e2004-01-20 23:12:12 +000080#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
wdenkc6097192002-11-03 00:24:07 +000081
82/*
83 * Miscellaneous configurable options
84 */
Tom Rini8dd6f7b2015-06-02 11:12:20 -040085#undef CONFIG_SYS_LONGHELP /* undef to save memory */
wdenkc6097192002-11-03 00:24:07 +000086
Jon Loeliger8c5f4a42007-07-05 19:52:35 -050087#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020088#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkc6097192002-11-03 00:24:07 +000089#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020090#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkc6097192002-11-03 00:24:07 +000091#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020092#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
93#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
94#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkc6097192002-11-03 00:24:07 +000095
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020096#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
wdenkc6097192002-11-03 00:24:07 +000097
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020098#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
wdenkc6097192002-11-03 00:24:07 +000099
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200100#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
101#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenkc6097192002-11-03 00:24:07 +0000102
Stefan Roese3ddce572010-09-20 16:05:31 +0200103#define CONFIG_CONS_INDEX 1 /* Use UART0 */
Stefan Roese3ddce572010-09-20 16:05:31 +0200104#define CONFIG_SYS_NS16550_SERIAL
105#define CONFIG_SYS_NS16550_REG_SIZE 1
106#define CONFIG_SYS_NS16550_CLK get_serial_clock()
107
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200108#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200109#define CONFIG_SYS_BASE_BAUD 691200
wdenkc6097192002-11-03 00:24:07 +0000110
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200111#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
112#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
wdenkc6097192002-11-03 00:24:07 +0000113
Matthias Fuchsf00a1842008-09-05 15:34:04 +0200114#define CONFIG_CMDLINE_EDITING /* add command line history */
115
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200116#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
stroese94ef1cf2003-06-05 15:39:44 +0000117
wdenkc6097192002-11-03 00:24:07 +0000118/*-----------------------------------------------------------------------
119 * PCI stuff
120 *-----------------------------------------------------------------------
121 */
stroesea9484a92004-12-16 18:05:42 +0000122#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
123#define PCI_HOST_FORCE 1 /* configure as pci host */
124#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
wdenkc6097192002-11-03 00:24:07 +0000125
Gabor Juhosb4458732013-05-30 07:06:12 +0000126#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
stroesea9484a92004-12-16 18:05:42 +0000127#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
stroesea9484a92004-12-16 18:05:42 +0000128 /* resource configuration */
wdenkc6097192002-11-03 00:24:07 +0000129
stroesea9484a92004-12-16 18:05:42 +0000130#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
wdenkc6097192002-11-03 00:24:07 +0000131
stroesea9484a92004-12-16 18:05:42 +0000132#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
stroesef5dd4102003-02-14 11:21:23 +0000133
stroesea9484a92004-12-16 18:05:42 +0000134#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
135
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200136#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
137#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
138#define CONFIG_SYS_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */
139#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
140#define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
141#define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
142#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
143#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
144#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
Matthias Fuchse717a502012-11-02 14:30:34 +0100145#define CONFIG_SYS_PCI_PTM2PCI (bd->bi_memsize) /* host use this pci address */
wdenkc6097192002-11-03 00:24:07 +0000146
Matthias Fuchsa9d47992009-09-07 17:00:41 +0200147#define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */
148
wdenkc6097192002-11-03 00:24:07 +0000149/*-----------------------------------------------------------------------
150 * IDE/ATA stuff
151 *-----------------------------------------------------------------------
152 */
wdenkda55c6e2004-01-20 23:12:12 +0000153#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
154#undef CONFIG_IDE_LED /* no led for ide supported */
wdenkc6097192002-11-03 00:24:07 +0000155#define CONFIG_IDE_RESET 1 /* reset for ide supported */
156
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200157#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */
158#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
wdenkc6097192002-11-03 00:24:07 +0000159
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200160#define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000
161#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenkc6097192002-11-03 00:24:07 +0000162
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200163#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
164#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
165#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
wdenkc6097192002-11-03 00:24:07 +0000166
167/*-----------------------------------------------------------------------
168 * Start addresses for the final memory configuration
169 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200170 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkc6097192002-11-03 00:24:07 +0000171 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200172#define CONFIG_SYS_SDRAM_BASE 0x00000000
173#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
174#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
175#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
176#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
wdenkc6097192002-11-03 00:24:07 +0000177
Matthias Fuchs92c91ec2009-01-02 12:18:49 +0100178#define CONFIG_PRAM 0 /* use pram variable to overwrite */
179
wdenkc6097192002-11-03 00:24:07 +0000180/*
181 * For booting Linux, the board info and command line data
182 * have to be in the first 8 MB of memory, since this is
183 * the maximum mapped by the Linux kernel during initialization.
184 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200185#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Matthias Fuchsf00a1842008-09-05 15:34:04 +0200186
wdenkc6097192002-11-03 00:24:07 +0000187/*-----------------------------------------------------------------------
188 * FLASH organization
189 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200190#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
191#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
wdenkc6097192002-11-03 00:24:07 +0000192
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200193#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
194#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenkc6097192002-11-03 00:24:07 +0000195
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200196#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
197#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
198#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
wdenkc6097192002-11-03 00:24:07 +0000199/*
200 * The following defines are added for buggy IOP480 byte interface.
201 * All other boards should use the standard values (CPCI405 etc.)
202 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200203#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
204#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
205#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
wdenkc6097192002-11-03 00:24:07 +0000206
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200207#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
wdenkc6097192002-11-03 00:24:07 +0000208
wdenkc6097192002-11-03 00:24:07 +0000209#if 0 /* Use NVRAM for environment variables */
210/*-----------------------------------------------------------------------
211 * NVRAM organization
212 */
Jean-Christophe PLAGNIOL-VILLARDfdb79c32008-09-10 22:47:59 +0200213#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200214#define CONFIG_ENV_SIZE 0x0ff8 /* Size of Environment vars */
215#define CONFIG_ENV_ADDR \
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200216 (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-(CONFIG_ENV_SIZE+8)) /* Env */
wdenkc6097192002-11-03 00:24:07 +0000217
218#else /* Use EEPROM for environment variables */
219
Jean-Christophe PLAGNIOL-VILLARDe46af642008-09-05 09:19:30 +0200220#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200221#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
222#define CONFIG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/
wdenk57b2d802003-06-27 21:31:46 +0000223 /* total size of a CAT24WC16 is 2048 bytes */
wdenkc6097192002-11-03 00:24:07 +0000224#endif
225
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200226#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */
227#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */
228#define CONFIG_SYS_VXWORKS_MAC_PTR (CONFIG_SYS_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
wdenkc6097192002-11-03 00:24:07 +0000229
230/*-----------------------------------------------------------------------
231 * I2C EEPROM (CAT24WC16) for environment
232 */
Dirk Eibach42b204f2013-04-25 02:40:01 +0000233#define CONFIG_SYS_I2C
234#define CONFIG_SYS_I2C_PPC4XX
235#define CONFIG_SYS_I2C_PPC4XX_CH0
236#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
237#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
wdenkc6097192002-11-03 00:24:07 +0000238
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200239#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
240#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
wdenkda55c6e2004-01-20 23:12:12 +0000241/* mask of address bits that overflow into the "EEPROM chip address" */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200242#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
243#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
wdenkc6097192002-11-03 00:24:07 +0000244 /* 16 byte page write mode using*/
wdenkda55c6e2004-01-20 23:12:12 +0000245 /* last 4 bits of the address */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200246#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
wdenkc6097192002-11-03 00:24:07 +0000247
wdenkc6097192002-11-03 00:24:07 +0000248/*
249 * Init Memory Controller:
250 *
251 * BR0/1 and OR0/1 (FLASH)
252 */
253
254#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
255#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */
256
257/*-----------------------------------------------------------------------
258 * External Bus Controller (EBC) Setup
259 */
260
wdenkda55c6e2004-01-20 23:12:12 +0000261/* Memory Bank 0 (Flash Bank 0) initialization */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200262#define CONFIG_SYS_EBC_PB0AP 0x92015480
263#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
wdenkc6097192002-11-03 00:24:07 +0000264
wdenkda55c6e2004-01-20 23:12:12 +0000265/* Memory Bank 1 (Flash Bank 1) initialization */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200266#define CONFIG_SYS_EBC_PB1AP 0x92015480
267#define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
wdenkc6097192002-11-03 00:24:07 +0000268
wdenkda55c6e2004-01-20 23:12:12 +0000269/* Memory Bank 2 (CAN0, 1) initialization */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200270#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
271#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
272#define CONFIG_SYS_LED_ADDR 0xF0000380
wdenkc6097192002-11-03 00:24:07 +0000273
wdenkda55c6e2004-01-20 23:12:12 +0000274/* Memory Bank 3 (CompactFlash IDE) initialization */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200275#define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
276#define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
wdenkc6097192002-11-03 00:24:07 +0000277
wdenkda55c6e2004-01-20 23:12:12 +0000278/* Memory Bank 4 (NVRAM/RTC) initialization */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200279/*#define CONFIG_SYS_EBC_PB4AP 0x01805280 / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1 */
280#define CONFIG_SYS_EBC_PB4AP 0x01805680 /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1 */
281#define CONFIG_SYS_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
wdenkc6097192002-11-03 00:24:07 +0000282
wdenkda55c6e2004-01-20 23:12:12 +0000283/* Memory Bank 5 (optional Quart) initialization */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200284#define CONFIG_SYS_EBC_PB5AP 0x04005B80 /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
285#define CONFIG_SYS_EBC_PB5CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
wdenkc6097192002-11-03 00:24:07 +0000286
wdenkda55c6e2004-01-20 23:12:12 +0000287/* Memory Bank 6 (FPGA internal) initialization */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200288#define CONFIG_SYS_EBC_PB6AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
289#define CONFIG_SYS_EBC_PB6CR 0xF041A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
290#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0400000
wdenkc6097192002-11-03 00:24:07 +0000291
292/*-----------------------------------------------------------------------
293 * FPGA stuff
294 */
295/* FPGA internal regs */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200296#define CONFIG_SYS_FPGA_MODE 0x00
297#define CONFIG_SYS_FPGA_STATUS 0x02
298#define CONFIG_SYS_FPGA_TS 0x04
299#define CONFIG_SYS_FPGA_TS_LOW 0x06
300#define CONFIG_SYS_FPGA_TS_CAP0 0x10
301#define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12
302#define CONFIG_SYS_FPGA_TS_CAP1 0x14
303#define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16
304#define CONFIG_SYS_FPGA_TS_CAP2 0x18
305#define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a
306#define CONFIG_SYS_FPGA_TS_CAP3 0x1c
307#define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e
wdenkc6097192002-11-03 00:24:07 +0000308
309/* FPGA Mode Reg */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200310#define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001
311#define CONFIG_SYS_FPGA_MODE_DUART_RESET 0x0002
312#define CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT 0x0004 /* only set on CPCI-405 Ver 3 */
313#define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
314#define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR 0x1000
315#define CONFIG_SYS_FPGA_MODE_TS_CLEAR 0x2000
wdenkc6097192002-11-03 00:24:07 +0000316
317/* FPGA Status Reg */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200318#define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001
319#define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002
320#define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004
321#define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008
322#define CONFIG_SYS_FPGA_STATUS_TS_IRQ 0x1000
wdenkc6097192002-11-03 00:24:07 +0000323
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200324#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
325#define CONFIG_SYS_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for XC2S15 */
wdenkc6097192002-11-03 00:24:07 +0000326
327/* FPGA program pin configuration */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200328#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
329#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
330#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
331#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
332#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
wdenkc6097192002-11-03 00:24:07 +0000333
334/*-----------------------------------------------------------------------
335 * Definitions for initial stack pointer and data area (in data cache)
336 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200337#define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
wdenkc6097192002-11-03 00:24:07 +0000338
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200339#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200340#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
Wolfgang Denk0191e472010-10-26 14:34:52 +0200341#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200342#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkc6097192002-11-03 00:24:07 +0000343
wdenkc6097192002-11-03 00:24:07 +0000344#endif /* __CONFIG_H */