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Sedji Gaouaou538566d2009-07-09 10:16:29 +02001/*
2 * Chip-specific header file for the AT91SAM9M1x family
3 *
Reinhard Meyer987d5052011-02-18 09:33:51 +01004 * (C) 2008 Atmel Corporation.
Sedji Gaouaou538566d2009-07-09 10:16:29 +02005 *
Reinhard Meyer987d5052011-02-18 09:33:51 +01006 * Definitions for the SoC:
7 * AT91SAM9G45
Sedji Gaouaou538566d2009-07-09 10:16:29 +02008 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02009 * SPDX-License-Identifier: GPL-2.0+
Sedji Gaouaou538566d2009-07-09 10:16:29 +020010 */
11
12#ifndef AT91SAM9G45_H
13#define AT91SAM9G45_H
14
15/*
Reinhard Meyer987d5052011-02-18 09:33:51 +010016 * defines to be used in other places
Sedji Gaouaou538566d2009-07-09 10:16:29 +020017 */
Reinhard Meyer987d5052011-02-18 09:33:51 +010018#define CONFIG_AT91FAMILY /* it's a member of AT91 */
Jens Scharsig698ad062010-02-03 22:46:01 +010019
Sedji Gaouaou538566d2009-07-09 10:16:29 +020020/*
Reinhard Meyer987d5052011-02-18 09:33:51 +010021 * Peripheral identifiers/interrupts.
Sedji Gaouaou538566d2009-07-09 10:16:29 +020022 */
Reinhard Meyer987d5052011-02-18 09:33:51 +010023#define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
24#define ATMEL_ID_SYS 1 /* System Controller Interrupt */
25#define ATMEL_ID_PIOA 2 /* Parallel I/O Controller A */
26#define ATMEL_ID_PIOB 3 /* Parallel I/O Controller B */
27#define ATMEL_ID_PIOC 4 /* Parallel I/O Controller C */
28#define ATMEL_ID_PIODE 5 /* Parallel I/O Controller D and E */
29#define ATMEL_ID_TRNG 6 /* True Random Number Generator */
30#define ATMEL_ID_USART0 7 /* USART 0 */
31#define ATMEL_ID_USART1 8 /* USART 1 */
32#define ATMEL_ID_USART2 9 /* USART 2 */
33#define ATMEL_ID_USART3 10 /* USART 3 */
34#define ATMEL_ID_MCI0 11 /* High Speed Multimedia Card Interface 0 */
35#define ATMEL_ID_TWI0 12 /* Two-Wire Interface 0 */
36#define ATMEL_ID_TWI1 13 /* Two-Wire Interface 1 */
37#define ATMEL_ID_SPI0 14 /* Serial Peripheral Interface 0 */
38#define ATMEL_ID_SPI1 15 /* Serial Peripheral Interface 1 */
39#define ATMEL_ID_SSC0 16 /* Synchronous Serial Controller 0 */
40#define ATMEL_ID_SSC1 17 /* Synchronous Serial Controller 1 */
41#define ATMEL_ID_TCB 18 /* Timer Counter 0, 1, 2, 3, 4 and 5 */
42#define ATMEL_ID_PWMC 19 /* Pulse Width Modulation Controller */
43#define ATMEL_ID_TSC 20 /* Touch Screen ADC Controller */
44#define ATMEL_ID_DMA 21 /* DMA Controller */
45#define ATMEL_ID_UHPHS 22 /* USB Host High Speed */
46#define ATMEL_ID_LCDC 23 /* LCD Controller */
47#define ATMEL_ID_AC97C 24 /* AC97 Controller */
48#define ATMEL_ID_EMAC 25 /* Ethernet MAC */
49#define ATMEL_ID_ISI 26 /* Image Sensor Interface */
50#define ATMEL_ID_UDPHS 27 /* USB Device High Speed */
51#define ATMEL_ID_AESTDESSHA 28 /* AES + T-DES + SHA */
52#define ATMEL_ID_MCI1 29 /* High Speed Multimedia Card Interface 1 */
53#define ATMEL_ID_VDEC 30 /* Video Decoder */
54#define ATMEL_ID_IRQ0 31 /* Advanced Interrupt Controller */
Sedji Gaouaou538566d2009-07-09 10:16:29 +020055
56/*
Reinhard Meyer987d5052011-02-18 09:33:51 +010057 * User Peripherals physical base addresses.
Sedji Gaouaou538566d2009-07-09 10:16:29 +020058 */
Reinhard Meyer987d5052011-02-18 09:33:51 +010059#define ATMEL_BASE_UDPHS 0xfff78000
60#define ATMEL_BASE_TC0 0xfff7c000
61#define ATMEL_BASE_TC1 0xfff7c040
62#define ATMEL_BASE_TC2 0xfff7c080
63#define ATMEL_BASE_MCI0 0xfff80000
64#define ATMEL_BASE_TWI0 0xfff84000
65#define ATMEL_BASE_TWI1 0xfff88000
66#define ATMEL_BASE_USART0 0xfff8c000
67#define ATMEL_BASE_USART1 0xfff90000
68#define ATMEL_BASE_USART2 0xfff94000
69#define ATMEL_BASE_USART3 0xfff98000
70#define ATMEL_BASE_SSC0 0xfff9c000
71#define ATMEL_BASE_SSC1 0xfffa0000
72#define ATMEL_BASE_SPI0 0xfffa4000
73#define ATMEL_BASE_SPI1 0xfffa8000
74#define ATMEL_BASE_AC97C 0xfffac000
75#define ATMEL_BASE_TSC 0xfffb0000
76#define ATMEL_BASE_ISI 0xfffb4000
77#define ATMEL_BASE_PWMC 0xfffb8000
78#define ATMEL_BASE_EMAC 0xfffbc000
79#define ATMEL_BASE_AES 0xfffc0000
80#define ATMEL_BASE_TDES 0xfffc4000
81#define ATMEL_BASE_SHA 0xfffc8000
82#define ATMEL_BASE_TRNG 0xfffcc000
83#define ATMEL_BASE_MCI1 0xfffd0000
84#define ATMEL_BASE_TC3 0xfffd4000
85#define ATMEL_BASE_TC4 0xfffd4040
86#define ATMEL_BASE_TC5 0xfffd4080
87/* Reserved: 0xfffd8000 - 0xffffe1ff */
Sedji Gaouaou538566d2009-07-09 10:16:29 +020088
Reinhard Meyer987d5052011-02-18 09:33:51 +010089/*
90 * System Peripherals physical base addresses.
91 */
92#define ATMEL_BASE_SYS 0xffffe200
93#define ATMEL_BASE_ECC 0xffffe200
94#define ATMEL_BASE_DDRSDRC1 0xffffe400
95#define ATMEL_BASE_DDRSDRC0 0xffffe600
96#define ATMEL_BASE_SMC 0xffffe800
97#define ATMEL_BASE_MATRIX 0xffffea00
98#define ATMEL_BASE_DMA 0xffffec00
99#define ATMEL_BASE_DBGU 0xffffee00
100#define ATMEL_BASE_AIC 0xfffff000
101#define ATMEL_BASE_PIOA 0xfffff200
102#define ATMEL_BASE_PIOB 0xfffff400
103#define ATMEL_BASE_PIOC 0xfffff600
104#define ATMEL_BASE_PIOD 0xfffff800
105#define ATMEL_BASE_PIOE 0xfffffa00
106#define ATMEL_BASE_PMC 0xfffffc00
107#define ATMEL_BASE_RSTC 0xfffffd00
108#define ATMEL_BASE_SHDWN 0xfffffd10
109#define ATMEL_BASE_RTT 0xfffffd20
110#define ATMEL_BASE_PIT 0xfffffd30
111#define ATMEL_BASE_WDT 0xfffffd40
112#define ATMEL_BASE_GPBR 0xfffffd60
113#define ATMEL_BASE_RTC 0xfffffdb0
114/* Reserved: 0xfffffdc0 - 0xffffffff */
Jens Scharsig698ad062010-02-03 22:46:01 +0100115
Sedji Gaouaou538566d2009-07-09 10:16:29 +0200116/*
117 * Internal Memory.
118 */
Reinhard Meyer987d5052011-02-18 09:33:51 +0100119#define ATMEL_BASE_SRAM 0x00300000 /* Internal SRAM base address */
120#define ATMEL_BASE_ROM 0x00400000 /* Internal ROM base address */
121#define ATMEL_BASE_LCDC 0x00500000 /* LCD Controller */
122#define ATMEL_BASE_UDPHS_FIFO 0x00600000 /* USB Device HS controller */
123#define ATMEL_BASE_HCI 0x00700000 /* USB Host controller (OHCI) */
124#define ATMEL_BASE_EHCI 0x00800000 /* USB Host controller (EHCI) */
125#define ATMEL_BASE_VDEC 0x00900000 /* Video Decoder Controller */
Sedji Gaouaou538566d2009-07-09 10:16:29 +0200126
Reinhard Meyer987d5052011-02-18 09:33:51 +0100127/*
Thomas Petazzonib0263c52011-08-04 08:53:29 +0000128 * External memory
129 */
130#define ATMEL_BASE_CS0 0x10000000
131#define ATMEL_BASE_CS1 0x20000000
132#define ATMEL_BASE_CS2 0x30000000
133#define ATMEL_BASE_CS3 0x40000000
134#define ATMEL_BASE_CS4 0x50000000
135#define ATMEL_BASE_CS5 0x60000000
136#define ATMEL_BASE_CS6 0x70000000
137#define ATMEL_BASE_CS7 0x80000000
138
Bo Shen568079a2015-02-04 15:53:01 +0800139/* Timer */
140#define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c
141
Thomas Petazzonib0263c52011-08-04 08:53:29 +0000142/*
Reinhard Meyer987d5052011-02-18 09:33:51 +0100143 * Other misc defines
144 */
145#define ATMEL_PIO_PORTS 5 /* this SoCs has 5 PIO */
Reinhard Meyer4429e032011-08-04 20:56:11 +0000146#define ATMEL_BASE_PIO ATMEL_BASE_PIOA
147#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
148#define ATMEL_ID_UHP ATMEL_ID_UHPHS
Sedji Gaouaou538566d2009-07-09 10:16:29 +0200149/*
150 * Cpu Name
151 */
Reinhard Meyer987d5052011-02-18 09:33:51 +0100152#define ATMEL_CPU_NAME "AT91SAM9G45"
Sedji Gaouaou538566d2009-07-09 10:16:29 +0200153
154#endif