blob: 1b0420611ed3d11221cf6e84e7af55936a45e36d [file] [log] [blame]
Bo Shenc56e9f42015-03-27 14:23:34 +08001/*
2 * Copyright (C) 2015 Atmel Corporation
3 * Bo Shen <voice.shen@atmel.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE, \
9 LENGTH = CONFIG_SPL_MAX_SIZE }
10MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
11 LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
12
13OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
14OUTPUT_ARCH(arm)
15ENTRY(_start)
16SECTIONS
17{
18 .text :
19 {
20 __start = .;
21 *(.vectors)
22 arch/arm/cpu/arm926ejs/start.o (.text*)
23 *(.text*)
24 } >.sram
25
26 . = ALIGN(4);
27 .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
28
29 . = ALIGN(4);
30 .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
31
32 . = ALIGN(4);
Tom Rini0ed608e2016-03-15 17:56:29 -040033 .u_boot_list : { KEEP(*(SORT(.u_boot_list*))) } > .sram
34
35 . = ALIGN(4);
Bo Shenc56e9f42015-03-27 14:23:34 +080036 __image_copy_end = .;
37
38 .end :
39 {
40 *(.__end)
41 } >.sram
42
43 .bss :
44 {
45 . = ALIGN(4);
46 __bss_start = .;
47 *(.bss*)
48 . = ALIGN(4);
49 __bss_end = .;
50 } >.sdram
51}