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wdenk5d3207d2002-08-21 22:08:56 +00001/*
Wolfgang Denk331dfe82008-03-26 15:38:47 +01002 * (C) Copyright 2001-2008
wdenk5d3207d2002-08-21 22:08:56 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * Keith Outwater, keith_outwater@mvis.com`
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25/*
26 * Date & Time support (no alarms) for Dallas Semiconductor (now Maxim)
27 * DS1337 Real Time Clock (RTC).
28 */
29
30#include <common.h>
31#include <command.h>
32#include <rtc.h>
33#include <i2c.h>
34
Michal Simekc3e6c552008-07-14 19:45:37 +020035#if defined(CONFIG_CMD_DATE)
wdenk5d3207d2002-08-21 22:08:56 +000036
wdenk5d3207d2002-08-21 22:08:56 +000037/*
38 * RTC register addresses
39 */
40#define RTC_SEC_REG_ADDR 0x0
41#define RTC_MIN_REG_ADDR 0x1
42#define RTC_HR_REG_ADDR 0x2
43#define RTC_DAY_REG_ADDR 0x3
44#define RTC_DATE_REG_ADDR 0x4
45#define RTC_MON_REG_ADDR 0x5
46#define RTC_YR_REG_ADDR 0x6
47#define RTC_CTL_REG_ADDR 0x0e
48#define RTC_STAT_REG_ADDR 0x0f
Werner Pfister3563ca42009-09-21 14:49:55 +020049#define RTC_TC_REG_ADDR 0x10
wdenk5d3207d2002-08-21 22:08:56 +000050
51/*
52 * RTC control register bits
53 */
Wolfgang Denk331dfe82008-03-26 15:38:47 +010054#define RTC_CTL_BIT_A1IE 0x1 /* Alarm 1 interrupt enable */
55#define RTC_CTL_BIT_A2IE 0x2 /* Alarm 2 interrupt enable */
56#define RTC_CTL_BIT_INTCN 0x4 /* Interrupt control */
57#define RTC_CTL_BIT_RS1 0x8 /* Rate select 1 */
58#define RTC_CTL_BIT_RS2 0x10 /* Rate select 2 */
59#define RTC_CTL_BIT_DOSC 0x80 /* Disable Oscillator */
wdenk5d3207d2002-08-21 22:08:56 +000060
61/*
62 * RTC status register bits
63 */
Wolfgang Denk331dfe82008-03-26 15:38:47 +010064#define RTC_STAT_BIT_A1F 0x1 /* Alarm 1 flag */
65#define RTC_STAT_BIT_A2F 0x2 /* Alarm 2 flag */
66#define RTC_STAT_BIT_OSF 0x80 /* Oscillator stop flag */
wdenk5d3207d2002-08-21 22:08:56 +000067
68
69static uchar rtc_read (uchar reg);
70static void rtc_write (uchar reg, uchar val);
wdenk5d3207d2002-08-21 22:08:56 +000071
72/*
73 * Get the current time from the RTC
74 */
Yuri Tikhonov9bacd942008-03-20 17:56:04 +030075int rtc_get (struct rtc_time *tmp)
wdenk5d3207d2002-08-21 22:08:56 +000076{
Yuri Tikhonov9bacd942008-03-20 17:56:04 +030077 int rel = 0;
wdenk5d3207d2002-08-21 22:08:56 +000078 uchar sec, min, hour, mday, wday, mon_cent, year, control, status;
79
80 control = rtc_read (RTC_CTL_REG_ADDR);
81 status = rtc_read (RTC_STAT_REG_ADDR);
82 sec = rtc_read (RTC_SEC_REG_ADDR);
83 min = rtc_read (RTC_MIN_REG_ADDR);
84 hour = rtc_read (RTC_HR_REG_ADDR);
85 wday = rtc_read (RTC_DAY_REG_ADDR);
86 mday = rtc_read (RTC_DATE_REG_ADDR);
87 mon_cent = rtc_read (RTC_MON_REG_ADDR);
88 year = rtc_read (RTC_YR_REG_ADDR);
89
Wolfgang Denkc0b15f02011-10-29 09:39:11 +000090 debug("Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x "
wdenk5d3207d2002-08-21 22:08:56 +000091 "hr: %02x min: %02x sec: %02x control: %02x status: %02x\n",
92 year, mon_cent, mday, wday, hour, min, sec, control, status);
93
94 if (status & RTC_STAT_BIT_OSF) {
95 printf ("### Warning: RTC oscillator has stopped\n");
96 /* clear the OSF flag */
97 rtc_write (RTC_STAT_REG_ADDR,
98 rtc_read (RTC_STAT_REG_ADDR) & ~RTC_STAT_BIT_OSF);
Yuri Tikhonov9bacd942008-03-20 17:56:04 +030099 rel = -1;
wdenk5d3207d2002-08-21 22:08:56 +0000100 }
101
102 tmp->tm_sec = bcd2bin (sec & 0x7F);
103 tmp->tm_min = bcd2bin (min & 0x7F);
104 tmp->tm_hour = bcd2bin (hour & 0x3F);
105 tmp->tm_mday = bcd2bin (mday & 0x3F);
106 tmp->tm_mon = bcd2bin (mon_cent & 0x1F);
107 tmp->tm_year = bcd2bin (year) + ((mon_cent & 0x80) ? 2000 : 1900);
108 tmp->tm_wday = bcd2bin ((wday - 1) & 0x07);
109 tmp->tm_yday = 0;
110 tmp->tm_isdst= 0;
111
Wolfgang Denkc0b15f02011-10-29 09:39:11 +0000112 debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
wdenk5d3207d2002-08-21 22:08:56 +0000113 tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
114 tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
Yuri Tikhonov9bacd942008-03-20 17:56:04 +0300115
116 return rel;
wdenk5d3207d2002-08-21 22:08:56 +0000117}
118
119
120/*
121 * Set the RTC
122 */
Jean-Christophe PLAGNIOL-VILLARD97a2e102008-09-01 23:06:23 +0200123int rtc_set (struct rtc_time *tmp)
wdenk5d3207d2002-08-21 22:08:56 +0000124{
125 uchar century;
126
Wolfgang Denkc0b15f02011-10-29 09:39:11 +0000127 debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
wdenk5d3207d2002-08-21 22:08:56 +0000128 tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
129 tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
130
131 rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100));
132
133 century = (tmp->tm_year >= 2000) ? 0x80 : 0;
134 rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon) | century);
135
136 rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday + 1));
137 rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday));
138 rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour));
139 rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min));
140 rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec));
Jean-Christophe PLAGNIOL-VILLARD97a2e102008-09-01 23:06:23 +0200141
142 return 0;
wdenk5d3207d2002-08-21 22:08:56 +0000143}
144
145
146/*
147 * Reset the RTC. We also enable the oscillator output on the
148 * SQW/INTB* pin and program it for 32,768 Hz output. Note that
149 * according to the datasheet, turning on the square wave output
150 * increases the current drain on the backup battery from about
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200151 * 600 nA to 2uA. Define CONFIG_SYS_RTC_DS1337_NOOSC if you wish to turn
Joakim Tjernlund2ef27312008-03-26 13:02:13 +0100152 * off the OSC output.
wdenk5d3207d2002-08-21 22:08:56 +0000153 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200154#ifdef CONFIG_SYS_RTC_DS1337_NOOSC
Joakim Tjernlund2ef27312008-03-26 13:02:13 +0100155 #define RTC_DS1337_RESET_VAL \
Wolfgang Denk331dfe82008-03-26 15:38:47 +0100156 (RTC_CTL_BIT_INTCN | RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2)
Joakim Tjernlund2ef27312008-03-26 13:02:13 +0100157#else
158 #define RTC_DS1337_RESET_VAL (RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2)
159#endif
wdenk5d3207d2002-08-21 22:08:56 +0000160void rtc_reset (void)
161{
Joakim Tjernlund2ef27312008-03-26 13:02:13 +0100162 rtc_write (RTC_CTL_REG_ADDR, RTC_DS1337_RESET_VAL);
Werner Pfister3563ca42009-09-21 14:49:55 +0200163#ifdef CONFIG_SYS_DS1339_TCR_VAL
164 rtc_write (RTC_TC_REG_ADDR, CONFIG_SYS_DS1339_TCR_VAL);
165#endif
wdenk5d3207d2002-08-21 22:08:56 +0000166}
167
168
169/*
170 * Helper functions
171 */
172
173static
174uchar rtc_read (uchar reg)
175{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200176 return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg));
wdenk5d3207d2002-08-21 22:08:56 +0000177}
178
179
180static void rtc_write (uchar reg, uchar val)
181{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200182 i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
wdenk5d3207d2002-08-21 22:08:56 +0000183}
184
Jon Loeliger07efe2a2007-07-10 10:27:39 -0500185#endif