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git01.mediatek.com / filogic / uboot / 2fbd17c701dbf49724b6d20bafa7a936c50f9f68 / . / drivers / gpio / mpc83xx_spisel_boot.c
blob: c7b08404d93b1ded8ec0a2de9913e220e599dd51 [file] [log] [blame]
Klaus H. Sorensene308da02020-02-11 15:20:22 +0000[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2019 DEIF A/S
4 *
5 * GPIO driver to set/clear SPISEL_BOOT pin on mpc83xx.
6 */
7
8#include <common.h>
9#include <dm.h>
10#include <mapmem.h>
11#include <asm/gpio.h>
12
13struct mpc83xx_spisel_boot {
14 u32 __iomem *spi_cs;
15 ulong addr;
16 uint gpio_count;
17 ulong type;
18};
19
20static u32 gpio_mask(uint gpio)
21{
22 return (1U << (31 - (gpio)));
23}
24
25static int mpc83xx_spisel_boot_direction_input(struct udevice *dev, uint gpio)
26{
27 return -EINVAL;
28}
29
30static int mpc83xx_spisel_boot_set_value(struct udevice *dev, uint gpio, int value)
31{
32 struct mpc83xx_spisel_boot *data = dev_get_priv(dev);
33
34 debug("%s: gpio=%d, value=%u, gpio_mask=0x%08x\n", __func__,
35 gpio, value, gpio_mask(gpio));
36
37 if (value)
38 setbits_be32(data->spi_cs, gpio_mask(gpio));
39 else
40 clrbits_be32(data->spi_cs, gpio_mask(gpio));
41
42 return 0;
43}
44
45static int mpc83xx_spisel_boot_direction_output(struct udevice *dev, uint gpio, int value)
46{
47 return 0;
48}
49
50static int mpc83xx_spisel_boot_get_value(struct udevice *dev, uint gpio)
51{
52 struct mpc83xx_spisel_boot *data = dev_get_priv(dev);
53
54 return !!(in_be32(data->spi_cs) & gpio_mask(gpio));
55}
56
57static int mpc83xx_spisel_boot_get_function(struct udevice *dev, uint gpio)
58{
59 return GPIOF_OUTPUT;
60}
61
62#if CONFIG_IS_ENABLED(OF_CONTROL)
63static int mpc83xx_spisel_boot_ofdata_to_platdata(struct udevice *dev)
64{
65 struct mpc8xxx_gpio_plat *plat = dev_get_platdata(dev);
66 fdt_addr_t addr;
67 u32 reg[2];
68
69 dev_read_u32_array(dev, "reg", reg, 2);
70 addr = dev_translate_address(dev, reg);
71
72 plat->addr = addr;
73 plat->size = reg[1];
74 plat->ngpios = dev_read_u32_default(dev, "ngpios", 1);
75
76 return 0;
77}
78#endif
79
80static int mpc83xx_spisel_boot_platdata_to_priv(struct udevice *dev)
81{
82 struct mpc83xx_spisel_boot *priv = dev_get_priv(dev);
83 struct mpc8xxx_gpio_plat *plat = dev_get_platdata(dev);
84 unsigned long size = plat->size;
85 ulong driver_data = dev_get_driver_data(dev);
86
87 if (size == 0)
88 size = 0x04;
89
90 priv->addr = plat->addr;
91 priv->spi_cs = map_sysmem(plat->addr, size);
92
93 if (!priv->spi_cs)
94 return -ENOMEM;
95
96 priv->gpio_count = plat->ngpios;
97
98 priv->type = driver_data;
99
100 return 0;
101}
102
103static int mpc83xx_spisel_boot_probe(struct udevice *dev)
104{
105 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
106 struct mpc83xx_spisel_boot *data = dev_get_priv(dev);
107 char name[32], *str;
108
109 mpc83xx_spisel_boot_platdata_to_priv(dev);
110
111 snprintf(name, sizeof(name), "MPC@%lx_", data->addr);
112 str = strdup(name);
113
114 if (!str)
115 return -ENOMEM;
116
117 uc_priv->bank_name = str;
118 uc_priv->gpio_count = data->gpio_count;
119
120 return 0;
121}
122
123static const struct dm_gpio_ops mpc83xx_spisel_boot_ops = {
124 .direction_input = mpc83xx_spisel_boot_direction_input,
125 .direction_output = mpc83xx_spisel_boot_direction_output,
126 .get_value = mpc83xx_spisel_boot_get_value,
127 .set_value = mpc83xx_spisel_boot_set_value,
128 .get_function = mpc83xx_spisel_boot_get_function,
129};
130
131static const struct udevice_id mpc83xx_spisel_boot_ids[] = {
132 { .compatible = "fsl,mpc8309-spisel-boot" },
133 { .compatible = "fsl,mpc83xx-spisel-boot" },
134 { /* sentinel */ }
135};
136
137U_BOOT_DRIVER(spisel_boot_mpc83xx) = {
138 .name = "spisel_boot_mpc83xx",
139 .id = UCLASS_GPIO,
140 .ops = &mpc83xx_spisel_boot_ops,
141#if CONFIG_IS_ENABLED(OF_CONTROL)
142 .ofdata_to_platdata = mpc83xx_spisel_boot_ofdata_to_platdata,
143 .platdata_auto_alloc_size = sizeof(struct mpc8xxx_gpio_plat),
144 .of_match = mpc83xx_spisel_boot_ids,
145#endif
146 .probe = mpc83xx_spisel_boot_probe,
147 .priv_auto_alloc_size = sizeof(struct mpc83xx_spisel_boot),
148};