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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Nobuhiro Iwamatsu970dc332007-05-13 20:58:00 +09002/*
3 * SuperH SCIF device driver.
Nobuhiro Iwamatsu788b73f2013-07-23 13:58:20 +09004 * Copyright (C) 2013 Renesas Electronics Corporation
Nobuhiro Iwamatsu6d020352015-02-12 13:48:04 +09005 * Copyright (C) 2007,2008,2010, 2014 Nobuhiro Iwamatsu
Nobuhiro Iwamatsua5579ca2010-10-26 03:55:15 +09006 * Copyright (C) 2002 - 2008 Paul Mundt
Nobuhiro Iwamatsu970dc332007-05-13 20:58:00 +09007 */
8
9#include <common.h>
Nobuhiro Iwamatsu6d020352015-02-12 13:48:04 +090010#include <errno.h>
Marek Vasut8fe2ffc2017-07-21 23:19:18 +020011#include <clk.h>
Nobuhiro Iwamatsu6d020352015-02-12 13:48:04 +090012#include <dm.h>
Jean-Christophe PLAGNIOL-VILLARDb27a8e32009-01-11 16:35:16 +010013#include <asm/io.h>
Nobuhiro Iwamatsu970dc332007-05-13 20:58:00 +090014#include <asm/processor.h>
Marek Vasut904d3d72012-09-14 22:40:08 +020015#include <serial.h>
16#include <linux/compiler.h>
Nobuhiro Iwamatsu6d020352015-02-12 13:48:04 +090017#include <dm/platform_data/serial_sh.h>
18#include "serial_sh.h"
Nobuhiro Iwamatsu970dc332007-05-13 20:58:00 +090019
Yoshinori Satoa6eed2b2016-04-18 16:51:04 +090020DECLARE_GLOBAL_DATA_PTR;
21
Nobuhiro Iwamatsua5579ca2010-10-26 03:55:15 +090022#if defined(CONFIG_CPU_SH7760) || \
23 defined(CONFIG_CPU_SH7780) || \
Nobuhiro Iwamatsua5579ca2010-10-26 03:55:15 +090024 defined(CONFIG_CPU_SH7786)
25static int scif_rxfill(struct uart_port *port)
Nobuhiro Iwamatsu970dc332007-05-13 20:58:00 +090026{
Nobuhiro Iwamatsua5579ca2010-10-26 03:55:15 +090027 return sci_in(port, SCRFDR) & 0xff;
28}
29#elif defined(CONFIG_CPU_SH7763)
30static int scif_rxfill(struct uart_port *port)
31{
32 if ((port->mapbase == 0xffe00000) ||
Nobuhiro Iwamatsu6d020352015-02-12 13:48:04 +090033 (port->mapbase == 0xffe08000)) {
Nobuhiro Iwamatsua5579ca2010-10-26 03:55:15 +090034 /* SCIF0/1*/
35 return sci_in(port, SCRFDR) & 0xff;
36 } else {
37 /* SCIF2 */
38 return sci_in(port, SCFDR) & SCIF2_RFDC_MASK;
39 }
40}
41#elif defined(CONFIG_ARCH_SH7372)
42static int scif_rxfill(struct uart_port *port)
43{
44 if (port->type == PORT_SCIFA)
45 return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
46 else
47 return sci_in(port, SCRFDR);
48}
Nobuhiro Iwamatsu1b36beb2008-03-06 14:05:53 +090049#else
Nobuhiro Iwamatsua5579ca2010-10-26 03:55:15 +090050static int scif_rxfill(struct uart_port *port)
51{
52 return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
53}
Nobuhiro Iwamatsu1b36beb2008-03-06 14:05:53 +090054#endif
Nobuhiro Iwamatsua5579ca2010-10-26 03:55:15 +090055
Nobuhiro Iwamatsu6d020352015-02-12 13:48:04 +090056static void sh_serial_init_generic(struct uart_port *port)
Nobuhiro Iwamatsua5579ca2010-10-26 03:55:15 +090057{
Nobuhiro Iwamatsu6d020352015-02-12 13:48:04 +090058 sci_out(port, SCSCR , SCSCR_INIT(port));
59 sci_out(port, SCSCR , SCSCR_INIT(port));
60 sci_out(port, SCSMR, 0);
61 sci_out(port, SCSMR, 0);
62 sci_out(port, SCFCR, SCFCR_RFRST|SCFCR_TFRST);
63 sci_in(port, SCFCR);
64 sci_out(port, SCFCR, 0);
Marek Vasut2d2e3ff2019-05-01 18:20:00 +020065#if defined(CONFIG_RZA1)
66 sci_out(port, SCSPTR, 0x0003);
67#endif
Nobuhiro Iwamatsu970dc332007-05-13 20:58:00 +090068}
69
Nobuhiro Iwamatsu6d020352015-02-12 13:48:04 +090070static void
71sh_serial_setbrg_generic(struct uart_port *port, int clk, int baudrate)
Tetsuyuki Kobayashi5d2b5a22012-11-19 21:37:38 +000072{
Nobuhiro Iwamatsu6d020352015-02-12 13:48:04 +090073 if (port->clk_mode == EXT_CLK) {
74 unsigned short dl = DL_VALUE(baudrate, clk);
75 sci_out(port, DL, dl);
Nobuhiro Iwamatsu17861752014-12-10 14:42:05 +090076 /* Need wait: Clock * 1/dl * 1/16 */
Nobuhiro Iwamatsu6d020352015-02-12 13:48:04 +090077 udelay((1000000 * dl * 16 / clk) * 1000 + 1);
78 } else {
79 sci_out(port, SCBRR, SCBRR_VALUE(baudrate, clk));
80 }
Tetsuyuki Kobayashi5d2b5a22012-11-19 21:37:38 +000081}
82
Nobuhiro Iwamatsu6d020352015-02-12 13:48:04 +090083static void handle_error(struct uart_port *port)
Nobuhiro Iwamatsu970dc332007-05-13 20:58:00 +090084{
Nobuhiro Iwamatsu6d020352015-02-12 13:48:04 +090085 sci_in(port, SCxSR);
86 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
87 sci_in(port, SCLSR);
88 sci_out(port, SCLSR, 0x00);
89}
90
91static int serial_raw_putc(struct uart_port *port, const char c)
92{
93 /* Tx fifo is empty */
94 if (!(sci_in(port, SCxSR) & SCxSR_TEND(port)))
95 return -EAGAIN;
Nobuhiro Iwamatsu970dc332007-05-13 20:58:00 +090096
Nobuhiro Iwamatsu6d020352015-02-12 13:48:04 +090097 sci_out(port, SCxTDR, c);
98 sci_out(port, SCxSR, sci_in(port, SCxSR) & ~SCxSR_TEND(port));
99
100 return 0;
Nobuhiro Iwamatsu970dc332007-05-13 20:58:00 +0900101}
102
Nobuhiro Iwamatsu6d020352015-02-12 13:48:04 +0900103static int serial_rx_fifo_level(struct uart_port *port)
Nobuhiro Iwamatsu970dc332007-05-13 20:58:00 +0900104{
Nobuhiro Iwamatsu6d020352015-02-12 13:48:04 +0900105 return scif_rxfill(port);
Nobuhiro Iwamatsu970dc332007-05-13 20:58:00 +0900106}
107
Nobuhiro Iwamatsu6d020352015-02-12 13:48:04 +0900108static int sh_serial_tstc_generic(struct uart_port *port)
Nobuhiro Iwamatsu970dc332007-05-13 20:58:00 +0900109{
Nobuhiro Iwamatsu6d020352015-02-12 13:48:04 +0900110 if (sci_in(port, SCxSR) & SCIF_ERRORS) {
111 handle_error(port);
Tetsuyuki Kobayashi5d2b5a22012-11-19 21:37:38 +0000112 return 0;
113 }
114
Nobuhiro Iwamatsu6d020352015-02-12 13:48:04 +0900115 return serial_rx_fifo_level(port) ? 1 : 0;
Nobuhiro Iwamatsu970dc332007-05-13 20:58:00 +0900116}
117
Nobuhiro Iwamatsu6d020352015-02-12 13:48:04 +0900118static int serial_getc_check(struct uart_port *port)
Nobuhiro Iwamatsu6564b1a2008-06-06 16:16:08 +0900119{
Nobuhiro Iwamatsu970dc332007-05-13 20:58:00 +0900120 unsigned short status;
121
Nobuhiro Iwamatsu6d020352015-02-12 13:48:04 +0900122 status = sci_in(port, SCxSR);
Nobuhiro Iwamatsu970dc332007-05-13 20:58:00 +0900123
Nobuhiro Iwamatsua5579ca2010-10-26 03:55:15 +0900124 if (status & SCIF_ERRORS)
Nobuhiro Iwamatsu6d020352015-02-12 13:48:04 +0900125 handle_error(port);
126 if (sci_in(port, SCLSR) & SCxSR_ORER(port))
127 handle_error(port);
128 return status & (SCIF_DR | SCxSR_RDxF(port));
Nobuhiro Iwamatsu970dc332007-05-13 20:58:00 +0900129}
130
Nobuhiro Iwamatsu6d020352015-02-12 13:48:04 +0900131static int sh_serial_getc_generic(struct uart_port *port)
Nobuhiro Iwamatsu970dc332007-05-13 20:58:00 +0900132{
Nobuhiro Iwamatsu6564b1a2008-06-06 16:16:08 +0900133 unsigned short status;
Nobuhiro Iwamatsu970dc332007-05-13 20:58:00 +0900134 char ch;
Nobuhiro Iwamatsufcabccc2008-08-22 17:48:51 +0900135
Nobuhiro Iwamatsu6d020352015-02-12 13:48:04 +0900136 if (!serial_getc_check(port))
137 return -EAGAIN;
Nobuhiro Iwamatsu970dc332007-05-13 20:58:00 +0900138
Nobuhiro Iwamatsu6d020352015-02-12 13:48:04 +0900139 ch = sci_in(port, SCxRDR);
140 status = sci_in(port, SCxSR);
Nobuhiro Iwamatsu970dc332007-05-13 20:58:00 +0900141
Nobuhiro Iwamatsu6d020352015-02-12 13:48:04 +0900142 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
Nobuhiro Iwamatsu970dc332007-05-13 20:58:00 +0900143
Nobuhiro Iwamatsua5579ca2010-10-26 03:55:15 +0900144 if (status & SCIF_ERRORS)
Nobuhiro Iwamatsu6d020352015-02-12 13:48:04 +0900145 handle_error(port);
146
147 if (sci_in(port, SCLSR) & SCxSR_ORER(port))
148 handle_error(port);
149
150 return ch;
151}
152
Marek Vasut0dfa9912018-02-16 01:33:27 +0100153#if CONFIG_IS_ENABLED(DM_SERIAL)
Nobuhiro Iwamatsu6d020352015-02-12 13:48:04 +0900154
155static int sh_serial_pending(struct udevice *dev, bool input)
156{
157 struct uart_port *priv = dev_get_priv(dev);
158
159 return sh_serial_tstc_generic(priv);
160}
161
162static int sh_serial_putc(struct udevice *dev, const char ch)
163{
164 struct uart_port *priv = dev_get_priv(dev);
165
166 return serial_raw_putc(priv, ch);
167}
168
169static int sh_serial_getc(struct udevice *dev)
170{
171 struct uart_port *priv = dev_get_priv(dev);
172
173 return sh_serial_getc_generic(priv);
174}
175
176static int sh_serial_setbrg(struct udevice *dev, int baudrate)
177{
178 struct sh_serial_platdata *plat = dev_get_platdata(dev);
179 struct uart_port *priv = dev_get_priv(dev);
180
181 sh_serial_setbrg_generic(priv, plat->clk, baudrate);
182
183 return 0;
184}
185
186static int sh_serial_probe(struct udevice *dev)
187{
188 struct sh_serial_platdata *plat = dev_get_platdata(dev);
189 struct uart_port *priv = dev_get_priv(dev);
190
191 priv->membase = (unsigned char *)plat->base;
192 priv->mapbase = plat->base;
193 priv->type = plat->type;
194 priv->clk_mode = plat->clk_mode;
195
196 sh_serial_init_generic(priv);
197
198 return 0;
199}
200
201static const struct dm_serial_ops sh_serial_ops = {
202 .putc = sh_serial_putc,
203 .pending = sh_serial_pending,
204 .getc = sh_serial_getc,
205 .setbrg = sh_serial_setbrg,
206};
207
Marek Vasut0dfa9912018-02-16 01:33:27 +0100208#if CONFIG_IS_ENABLED(OF_CONTROL)
Yoshinori Satoa6eed2b2016-04-18 16:51:04 +0900209static const struct udevice_id sh_serial_id[] ={
Yoshinori Satoe5669a32016-04-18 16:51:05 +0900210 {.compatible = "renesas,sci", .data = PORT_SCI},
Yoshinori Satoa6eed2b2016-04-18 16:51:04 +0900211 {.compatible = "renesas,scif", .data = PORT_SCIF},
212 {.compatible = "renesas,scifa", .data = PORT_SCIFA},
213 {}
214};
215
216static int sh_serial_ofdata_to_platdata(struct udevice *dev)
217{
218 struct sh_serial_platdata *plat = dev_get_platdata(dev);
Marek Vasut8fe2ffc2017-07-21 23:19:18 +0200219 struct clk sh_serial_clk;
Yoshinori Satoa6eed2b2016-04-18 16:51:04 +0900220 fdt_addr_t addr;
Marek Vasut8fe2ffc2017-07-21 23:19:18 +0200221 int ret;
Yoshinori Satoa6eed2b2016-04-18 16:51:04 +0900222
Marek Vasut48db7762018-01-17 22:36:37 +0100223 addr = devfdt_get_addr(dev);
224 if (!addr)
Yoshinori Satoa6eed2b2016-04-18 16:51:04 +0900225 return -EINVAL;
226
227 plat->base = addr;
Marek Vasut8fe2ffc2017-07-21 23:19:18 +0200228
229 ret = clk_get_by_name(dev, "fck", &sh_serial_clk);
Marek Vasutfd6a4a72017-09-15 21:11:27 +0200230 if (!ret) {
231 ret = clk_enable(&sh_serial_clk);
232 if (!ret)
233 plat->clk = clk_get_rate(&sh_serial_clk);
234 } else {
Marek Vasut8fe2ffc2017-07-21 23:19:18 +0200235 plat->clk = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
236 "clock", 1);
Marek Vasutfd6a4a72017-09-15 21:11:27 +0200237 }
Marek Vasut8fe2ffc2017-07-21 23:19:18 +0200238
Yoshinori Satoa6eed2b2016-04-18 16:51:04 +0900239 plat->type = dev_get_driver_data(dev);
240 return 0;
241}
242#endif
243
Nobuhiro Iwamatsu6d020352015-02-12 13:48:04 +0900244U_BOOT_DRIVER(serial_sh) = {
245 .name = "serial_sh",
246 .id = UCLASS_SERIAL,
Yoshinori Satoa6eed2b2016-04-18 16:51:04 +0900247 .of_match = of_match_ptr(sh_serial_id),
248 .ofdata_to_platdata = of_match_ptr(sh_serial_ofdata_to_platdata),
249 .platdata_auto_alloc_size = sizeof(struct sh_serial_platdata),
Nobuhiro Iwamatsu6d020352015-02-12 13:48:04 +0900250 .probe = sh_serial_probe,
251 .ops = &sh_serial_ops,
Bin Mengbdb33d82018-10-24 06:36:36 -0700252#if !CONFIG_IS_ENABLED(OF_CONTROL)
Nobuhiro Iwamatsu6d020352015-02-12 13:48:04 +0900253 .flags = DM_FLAG_PRE_RELOC,
Bin Mengbdb33d82018-10-24 06:36:36 -0700254#endif
Nobuhiro Iwamatsu6d020352015-02-12 13:48:04 +0900255 .priv_auto_alloc_size = sizeof(struct uart_port),
256};
257
258#else /* CONFIG_DM_SERIAL */
259
260#if defined(CONFIG_CONS_SCIF0)
261# define SCIF_BASE SCIF0_BASE
262#elif defined(CONFIG_CONS_SCIF1)
263# define SCIF_BASE SCIF1_BASE
264#elif defined(CONFIG_CONS_SCIF2)
265# define SCIF_BASE SCIF2_BASE
266#elif defined(CONFIG_CONS_SCIF3)
267# define SCIF_BASE SCIF3_BASE
268#elif defined(CONFIG_CONS_SCIF4)
269# define SCIF_BASE SCIF4_BASE
270#elif defined(CONFIG_CONS_SCIF5)
271# define SCIF_BASE SCIF5_BASE
272#elif defined(CONFIG_CONS_SCIF6)
273# define SCIF_BASE SCIF6_BASE
274#elif defined(CONFIG_CONS_SCIF7)
275# define SCIF_BASE SCIF7_BASE
Marek Vasut1d9756b2018-04-12 15:23:46 +0200276#elif defined(CONFIG_CONS_SCIFA0)
277# define SCIF_BASE SCIFA0_BASE
Nobuhiro Iwamatsu6d020352015-02-12 13:48:04 +0900278#else
279# error "Default SCIF doesn't set....."
280#endif
281
282#if defined(CONFIG_SCIF_A)
283 #define SCIF_BASE_PORT PORT_SCIFA
Yoshinori Satoe5669a32016-04-18 16:51:05 +0900284#elif defined(CONFIG_SCI)
285 #define SCIF_BASE_PORT PORT_SCI
Nobuhiro Iwamatsu6d020352015-02-12 13:48:04 +0900286#else
287 #define SCIF_BASE_PORT PORT_SCIF
288#endif
289
290static struct uart_port sh_sci = {
291 .membase = (unsigned char *)SCIF_BASE,
292 .mapbase = SCIF_BASE,
293 .type = SCIF_BASE_PORT,
294#ifdef CONFIG_SCIF_USE_EXT_CLK
295 .clk_mode = EXT_CLK,
296#endif
297};
298
299static void sh_serial_setbrg(void)
300{
301 DECLARE_GLOBAL_DATA_PTR;
302 struct uart_port *port = &sh_sci;
303
304 sh_serial_setbrg_generic(port, CONFIG_SH_SCIF_CLK_FREQ, gd->baudrate);
305}
306
307static int sh_serial_init(void)
308{
309 struct uart_port *port = &sh_sci;
310
311 sh_serial_init_generic(port);
312 serial_setbrg();
313
314 return 0;
315}
316
317static void sh_serial_putc(const char c)
318{
319 struct uart_port *port = &sh_sci;
320
321 if (c == '\n') {
322 while (1) {
323 if (serial_raw_putc(port, '\r') != -EAGAIN)
324 break;
325 }
326 }
327 while (1) {
328 if (serial_raw_putc(port, c) != -EAGAIN)
329 break;
330 }
331}
332
333static int sh_serial_tstc(void)
334{
335 struct uart_port *port = &sh_sci;
336
337 return sh_serial_tstc_generic(port);
338}
339
340static int sh_serial_getc(void)
341{
342 struct uart_port *port = &sh_sci;
343 int ch;
344
345 while (1) {
346 ch = sh_serial_getc_generic(port);
347 if (ch != -EAGAIN)
348 break;
349 }
Nobuhiro Iwamatsu970dc332007-05-13 20:58:00 +0900350
Nobuhiro Iwamatsu6564b1a2008-06-06 16:16:08 +0900351 return ch;
Nobuhiro Iwamatsu970dc332007-05-13 20:58:00 +0900352}
Marek Vasut904d3d72012-09-14 22:40:08 +0200353
Marek Vasut904d3d72012-09-14 22:40:08 +0200354static struct serial_device sh_serial_drv = {
355 .name = "sh_serial",
356 .start = sh_serial_init,
357 .stop = NULL,
358 .setbrg = sh_serial_setbrg,
359 .putc = sh_serial_putc,
Marek Vasutd9c64492012-10-06 14:07:02 +0000360 .puts = default_serial_puts,
Marek Vasut904d3d72012-09-14 22:40:08 +0200361 .getc = sh_serial_getc,
362 .tstc = sh_serial_tstc,
363};
364
365void sh_serial_initialize(void)
366{
367 serial_register(&sh_serial_drv);
368}
369
370__weak struct serial_device *default_serial_console(void)
371{
372 return &sh_serial_drv;
373}
Nobuhiro Iwamatsu6d020352015-02-12 13:48:04 +0900374#endif /* CONFIG_DM_SERIAL */