| Tom Rini | 8b0c8a1 | 2018-05-06 18:27:01 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause |
| Patrick Delaunay | 8eb3b1e | 2018-03-12 10:46:18 +0100 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2018, STMicroelectronics - All Rights Reserved |
| Patrick Delaunay | 8eb3b1e | 2018-03-12 10:46:18 +0100 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #include <common.h> |
| Patrick Delaunay | 8eb3b1e | 2018-03-12 10:46:18 +0100 | [diff] [blame] | 7 | #include <asm/io.h> |
| Simon Glass | 4dcacfc | 2020-05-10 11:40:13 -0600 | [diff] [blame] | 8 | #include <linux/bitops.h> |
| Simon Glass | dbd7954 | 2020-05-10 11:40:11 -0600 | [diff] [blame] | 9 | #include <linux/delay.h> |
| Patrick Delaunay | 8eb3b1e | 2018-03-12 10:46:18 +0100 | [diff] [blame] | 10 | |
| Patrick Delaunay | 82168e8 | 2018-05-17 14:50:46 +0200 | [diff] [blame] | 11 | #ifdef CONFIG_DEBUG_UART_BOARD_INIT |
| 12 | void board_debug_uart_init(void) |
| 13 | { |
| 14 | #if (CONFIG_DEBUG_UART_BASE == STM32_UART4_BASE) |
| 15 | |
| 16 | #define RCC_MP_APB1ENSETR (STM32_RCC_BASE + 0x0A00) |
| 17 | #define RCC_MP_AHB4ENSETR (STM32_RCC_BASE + 0x0A28) |
| 18 | |
| 19 | /* UART4 clock enable */ |
| 20 | setbits_le32(RCC_MP_APB1ENSETR, BIT(16)); |
| 21 | |
| 22 | #define GPIOG_BASE 0x50008000 |
| 23 | /* GPIOG clock enable */ |
| 24 | writel(BIT(6), RCC_MP_AHB4ENSETR); |
| 25 | /* GPIO configuration for EVAL board |
| 26 | * => Uart4 TX = G11 |
| 27 | */ |
| 28 | writel(0xffbfffff, GPIOG_BASE + 0x00); |
| 29 | writel(0x00006000, GPIOG_BASE + 0x24); |
| 30 | #else |
| 31 | |
| 32 | #error("CONFIG_DEBUG_UART_BASE: not supported value") |
| 33 | |
| 34 | #endif |
| 35 | } |
| 36 | #endif |