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Eran Liberty9095d4a2005-07-28 10:08:46 -05001/*
2 * (C) Copyright 2000-2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Dave Liua46daea2006-11-03 19:33:44 -06005 * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
Eran Liberty9095d4a2005-07-28 10:08:46 -05006 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
Eran Liberty9095d4a2005-07-28 10:08:46 -050024 */
25
26#include <common.h>
27#include <mpc83xx.h>
28#include <asm/processor.h>
29
Wolfgang Denk6405a152006-03-31 18:32:53 +020030DECLARE_GLOBAL_DATA_PTR;
31
Eran Liberty9095d4a2005-07-28 10:08:46 -050032/* ----------------------------------------------------------------- */
33
34typedef enum {
35 _unk,
36 _off,
37 _byp,
38 _x8,
39 _x4,
40 _x2,
41 _x1,
42 _1x,
43 _1_5x,
44 _2x,
45 _2_5x,
46 _3x
47} mult_t;
48
49typedef struct {
50 mult_t core_csb_ratio;
Kim Phillipsbae24792006-11-02 19:47:11 -060051 mult_t vco_divider;
Eran Liberty9095d4a2005-07-28 10:08:46 -050052} corecnf_t;
53
54corecnf_t corecnf_tab[] = {
Kim Phillipsbae24792006-11-02 19:47:11 -060055 {_byp, _byp}, /* 0x00 */
56 {_byp, _byp}, /* 0x01 */
57 {_byp, _byp}, /* 0x02 */
58 {_byp, _byp}, /* 0x03 */
59 {_byp, _byp}, /* 0x04 */
60 {_byp, _byp}, /* 0x05 */
61 {_byp, _byp}, /* 0x06 */
62 {_byp, _byp}, /* 0x07 */
63 {_1x, _x2}, /* 0x08 */
64 {_1x, _x4}, /* 0x09 */
65 {_1x, _x8}, /* 0x0A */
66 {_1x, _x8}, /* 0x0B */
67 {_1_5x, _x2}, /* 0x0C */
68 {_1_5x, _x4}, /* 0x0D */
69 {_1_5x, _x8}, /* 0x0E */
70 {_1_5x, _x8}, /* 0x0F */
71 {_2x, _x2}, /* 0x10 */
72 {_2x, _x4}, /* 0x11 */
73 {_2x, _x8}, /* 0x12 */
74 {_2x, _x8}, /* 0x13 */
75 {_2_5x, _x2}, /* 0x14 */
76 {_2_5x, _x4}, /* 0x15 */
77 {_2_5x, _x8}, /* 0x16 */
78 {_2_5x, _x8}, /* 0x17 */
79 {_3x, _x2}, /* 0x18 */
80 {_3x, _x4}, /* 0x19 */
81 {_3x, _x8}, /* 0x1A */
82 {_3x, _x8}, /* 0x1B */
Eran Liberty9095d4a2005-07-28 10:08:46 -050083};
84
85/* ----------------------------------------------------------------- */
86
87/*
88 *
89 */
Kim Phillipsbae24792006-11-02 19:47:11 -060090int get_clocks(void)
Eran Liberty9095d4a2005-07-28 10:08:46 -050091{
Timur Tabi386a2802006-11-03 12:00:28 -060092 volatile immap_t *im = (immap_t *) CFG_IMMR;
Eran Liberty9095d4a2005-07-28 10:08:46 -050093 u32 pci_sync_in;
Kim Phillipsbae24792006-11-02 19:47:11 -060094 u8 spmf;
95 u8 clkin_div;
Eran Liberty9095d4a2005-07-28 10:08:46 -050096 u32 sccr;
97 u32 corecnf_tab_index;
Kim Phillipsbae24792006-11-02 19:47:11 -060098 u8 corepll;
Eran Liberty9095d4a2005-07-28 10:08:46 -050099 u32 lcrr;
Jon Loeligerebc72242005-08-01 13:20:47 -0500100
Eran Liberty9095d4a2005-07-28 10:08:46 -0500101 u32 csb_clk;
Kumar Galab7870e72007-01-30 14:08:30 -0600102#if defined(CONFIG_MPC834X)
Eran Liberty9095d4a2005-07-28 10:08:46 -0500103 u32 tsec1_clk;
104 u32 tsec2_clk;
Eran Liberty9095d4a2005-07-28 10:08:46 -0500105 u32 usbmph_clk;
106 u32 usbdr_clk;
Dave Liua46daea2006-11-03 19:33:44 -0600107#endif
108 u32 core_clk;
109 u32 i2c1_clk;
Dave Liue740c462006-12-07 21:13:15 +0800110#if !defined(CONFIG_MPC832X)
Dave Liua46daea2006-11-03 19:33:44 -0600111 u32 i2c2_clk;
Dave Liue740c462006-12-07 21:13:15 +0800112#endif
Eran Liberty9095d4a2005-07-28 10:08:46 -0500113 u32 enc_clk;
114 u32 lbiu_clk;
115 u32 lclk_clk;
116 u32 ddr_clk;
Dave Liue740c462006-12-07 21:13:15 +0800117#if defined(CONFIG_MPC8360)
118 u32 ddr_sec_clk;
119#endif
120#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
Dave Liua46daea2006-11-03 19:33:44 -0600121 u32 qepmf;
122 u32 qepdf;
Dave Liua46daea2006-11-03 19:33:44 -0600123 u32 qe_clk;
124 u32 brg_clk;
125#endif
Jon Loeligerebc72242005-08-01 13:20:47 -0500126
Kim Phillipsbae24792006-11-02 19:47:11 -0600127 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
Eran Liberty9095d4a2005-07-28 10:08:46 -0500128 return -1;
Jon Loeligerebc72242005-08-01 13:20:47 -0500129
Dave Liua46daea2006-11-03 19:33:44 -0600130 clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
Marian Balakowicz513b4a12005-10-11 19:09:42 +0200131
Dave Liua46daea2006-11-03 19:33:44 -0600132 if (im->reset.rcwh & HRCWH_PCI_HOST) {
133#if defined(CONFIG_83XX_CLKIN)
134 pci_sync_in = CONFIG_83XX_CLKIN / (1 + clkin_div);
135#else
136 pci_sync_in = 0xDEADBEEF;
137#endif
138 } else {
139#if defined(CONFIG_83XX_PCICLK)
140 pci_sync_in = CONFIG_83XX_PCICLK;
141#else
142 pci_sync_in = 0xDEADBEEF;
143#endif
Eran Liberty9095d4a2005-07-28 10:08:46 -0500144 }
Marian Balakowicz513b4a12005-10-11 19:09:42 +0200145
Dave Liu0b6bc772006-12-07 21:11:58 +0800146 spmf = ((im->reset.rcwl & HRCWL_SPMF) >> HRCWL_SPMF_SHIFT);
Dave Liua46daea2006-11-03 19:33:44 -0600147 csb_clk = pci_sync_in * (1 + clkin_div) * spmf;
Jon Loeligerebc72242005-08-01 13:20:47 -0500148
Eran Liberty9095d4a2005-07-28 10:08:46 -0500149 sccr = im->clk.sccr;
Dave Liua46daea2006-11-03 19:33:44 -0600150
Kumar Galab7870e72007-01-30 14:08:30 -0600151#if defined(CONFIG_MPC834X)
Eran Liberty9095d4a2005-07-28 10:08:46 -0500152 switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
153 case 0:
154 tsec1_clk = 0;
155 break;
156 case 1:
157 tsec1_clk = csb_clk;
158 break;
159 case 2:
160 tsec1_clk = csb_clk / 2;
161 break;
162 case 3:
163 tsec1_clk = csb_clk / 3;
164 break;
165 default:
166 /* unkown SCCR_TSEC1CM value */
167 return -4;
168 }
Jon Loeligerebc72242005-08-01 13:20:47 -0500169
Eran Liberty9095d4a2005-07-28 10:08:46 -0500170 switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
171 case 0:
172 tsec2_clk = 0;
173 break;
174 case 1:
175 tsec2_clk = csb_clk;
176 break;
177 case 2:
178 tsec2_clk = csb_clk / 2;
179 break;
180 case 3:
181 tsec2_clk = csb_clk / 3;
182 break;
183 default:
184 /* unkown SCCR_TSEC2CM value */
185 return -5;
186 }
Jon Loeligerebc72242005-08-01 13:20:47 -0500187
Dave Liua46daea2006-11-03 19:33:44 -0600188 i2c1_clk = tsec2_clk;
Jon Loeligerebc72242005-08-01 13:20:47 -0500189
Eran Liberty9095d4a2005-07-28 10:08:46 -0500190 switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) {
191 case 0:
192 usbmph_clk = 0;
193 break;
194 case 1:
195 usbmph_clk = csb_clk;
196 break;
197 case 2:
198 usbmph_clk = csb_clk / 2;
199 break;
200 case 3:
201 usbmph_clk = csb_clk / 3;
202 break;
203 default:
204 /* unkown SCCR_USBMPHCM value */
205 return -7;
206 }
207
208 switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
209 case 0:
210 usbdr_clk = 0;
211 break;
212 case 1:
213 usbdr_clk = csb_clk;
214 break;
215 case 2:
216 usbdr_clk = csb_clk / 2;
217 break;
218 case 3:
219 usbdr_clk = csb_clk / 3;
220 break;
221 default:
222 /* unkown SCCR_USBDRCM value */
223 return -8;
224 }
Jon Loeligerebc72242005-08-01 13:20:47 -0500225
Kim Phillipsbae24792006-11-02 19:47:11 -0600226 if (usbmph_clk != 0 && usbdr_clk != 0 && usbmph_clk != usbdr_clk) {
227 /* if USB MPH clock is not disabled and
228 * USB DR clock is not disabled then
229 * USB MPH & USB DR must have the same rate
230 */
Eran Liberty9095d4a2005-07-28 10:08:46 -0500231 return -9;
232 }
Dave Liua46daea2006-11-03 19:33:44 -0600233#endif
Dave Liue740c462006-12-07 21:13:15 +0800234#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
Dave Liua46daea2006-11-03 19:33:44 -0600235 i2c1_clk = csb_clk;
236#endif
Dave Liue740c462006-12-07 21:13:15 +0800237#if !defined(CONFIG_MPC832X)
Kim Phillipsbae24792006-11-02 19:47:11 -0600238 i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
Dave Liue740c462006-12-07 21:13:15 +0800239#endif
Jon Loeligerebc72242005-08-01 13:20:47 -0500240
Dave Liua46daea2006-11-03 19:33:44 -0600241 switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
242 case 0:
243 enc_clk = 0;
244 break;
245 case 1:
246 enc_clk = csb_clk;
247 break;
248 case 2:
249 enc_clk = csb_clk / 2;
250 break;
251 case 3:
252 enc_clk = csb_clk / 3;
253 break;
254 default:
255 /* unkown SCCR_ENCCM value */
256 return -6;
257 }
Dave Liue740c462006-12-07 21:13:15 +0800258
Kim Phillipsbae24792006-11-02 19:47:11 -0600259 lbiu_clk = csb_clk *
Dave Liu0b6bc772006-12-07 21:11:58 +0800260 (1 + ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT));
Eran Liberty9095d4a2005-07-28 10:08:46 -0500261 lcrr = (im->lbus.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
262 switch (lcrr) {
263 case 2:
264 case 4:
265 case 8:
266 lclk_clk = lbiu_clk / lcrr;
267 break;
268 default:
269 /* unknown lcrr */
270 return -10;
271 }
Dave Liue740c462006-12-07 21:13:15 +0800272
Kim Phillipsbae24792006-11-02 19:47:11 -0600273 ddr_clk = csb_clk *
Dave Liu0b6bc772006-12-07 21:11:58 +0800274 (1 + ((im->reset.rcwl & HRCWL_DDRCM) >> HRCWL_DDRCM_SHIFT));
275 corepll = (im->reset.rcwl & HRCWL_COREPLL) >> HRCWL_COREPLL_SHIFT;
Dave Liue740c462006-12-07 21:13:15 +0800276#if defined(CONFIG_MPC8360)
Kim Phillipsbae24792006-11-02 19:47:11 -0600277 ddr_sec_clk = csb_clk * (1 +
Dave Liu0b6bc772006-12-07 21:11:58 +0800278 ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT));
Dave Liua46daea2006-11-03 19:33:44 -0600279#endif
Dave Liua46daea2006-11-03 19:33:44 -0600280
Eran Liberty9095d4a2005-07-28 10:08:46 -0500281 corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5);
Kim Phillipsbae24792006-11-02 19:47:11 -0600282 if (corecnf_tab_index > (sizeof(corecnf_tab) / sizeof(corecnf_t))) {
Eran Liberty9095d4a2005-07-28 10:08:46 -0500283 /* corecnf_tab_index is too high, possibly worng value */
284 return -11;
285 }
286 switch (corecnf_tab[corecnf_tab_index].core_csb_ratio) {
287 case _byp:
288 case _x1:
289 case _1x:
290 core_clk = csb_clk;
291 break;
292 case _1_5x:
293 core_clk = (3 * csb_clk) / 2;
294 break;
295 case _2x:
296 core_clk = 2 * csb_clk;
297 break;
298 case _2_5x:
Kim Phillipsbae24792006-11-02 19:47:11 -0600299 core_clk = (5 * csb_clk) / 2;
Eran Liberty9095d4a2005-07-28 10:08:46 -0500300 break;
301 case _3x:
302 core_clk = 3 * csb_clk;
303 break;
304 default:
305 /* unkown core to csb ratio */
306 return -12;
307 }
Jon Loeligerebc72242005-08-01 13:20:47 -0500308
Dave Liue740c462006-12-07 21:13:15 +0800309#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
Dave Liu0b6bc772006-12-07 21:11:58 +0800310 qepmf = (im->reset.rcwl & HRCWL_CEPMF) >> HRCWL_CEPMF_SHIFT;
311 qepdf = (im->reset.rcwl & HRCWL_CEPDF) >> HRCWL_CEPDF_SHIFT;
Kim Phillipsbae24792006-11-02 19:47:11 -0600312 qe_clk = (pci_sync_in * qepmf) / (1 + qepdf);
Dave Liua46daea2006-11-03 19:33:44 -0600313 brg_clk = qe_clk / 2;
314#endif
Jon Loeligerebc72242005-08-01 13:20:47 -0500315
Kim Phillipsbae24792006-11-02 19:47:11 -0600316 gd->csb_clk = csb_clk;
Kumar Galab7870e72007-01-30 14:08:30 -0600317#if defined(CONFIG_MPC834X)
Kim Phillipsbae24792006-11-02 19:47:11 -0600318 gd->tsec1_clk = tsec1_clk;
319 gd->tsec2_clk = tsec2_clk;
320 gd->usbmph_clk = usbmph_clk;
321 gd->usbdr_clk = usbdr_clk;
Dave Liua46daea2006-11-03 19:33:44 -0600322#endif
Kim Phillipsbae24792006-11-02 19:47:11 -0600323 gd->core_clk = core_clk;
324 gd->i2c1_clk = i2c1_clk;
Dave Liue740c462006-12-07 21:13:15 +0800325#if !defined(CONFIG_MPC832X)
Kim Phillipsbae24792006-11-02 19:47:11 -0600326 gd->i2c2_clk = i2c2_clk;
Dave Liue740c462006-12-07 21:13:15 +0800327#endif
Kim Phillipsbae24792006-11-02 19:47:11 -0600328 gd->enc_clk = enc_clk;
329 gd->lbiu_clk = lbiu_clk;
330 gd->lclk_clk = lclk_clk;
331 gd->ddr_clk = ddr_clk;
Dave Liue740c462006-12-07 21:13:15 +0800332#if defined(CONFIG_MPC8360)
Dave Liua46daea2006-11-03 19:33:44 -0600333 gd->ddr_sec_clk = ddr_sec_clk;
Dave Liue740c462006-12-07 21:13:15 +0800334#endif
335#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
Kim Phillipsbae24792006-11-02 19:47:11 -0600336 gd->qe_clk = qe_clk;
337 gd->brg_clk = brg_clk;
Dave Liua46daea2006-11-03 19:33:44 -0600338#endif
Kim Phillipsbae24792006-11-02 19:47:11 -0600339 gd->cpu_clk = gd->core_clk;
340 gd->bus_clk = gd->csb_clk;
Eran Liberty9095d4a2005-07-28 10:08:46 -0500341 return 0;
Dave Liua46daea2006-11-03 19:33:44 -0600342
Eran Liberty9095d4a2005-07-28 10:08:46 -0500343}
344
345/********************************************
346 * get_bus_freq
347 * return system bus freq in Hz
348 *********************************************/
Kim Phillipsbae24792006-11-02 19:47:11 -0600349ulong get_bus_freq(ulong dummy)
Eran Liberty9095d4a2005-07-28 10:08:46 -0500350{
Eran Liberty9095d4a2005-07-28 10:08:46 -0500351 return gd->csb_clk;
352}
353
Kim Phillipsbae24792006-11-02 19:47:11 -0600354int print_clock_conf(void)
Eran Liberty9095d4a2005-07-28 10:08:46 -0500355{
Eran Liberty9095d4a2005-07-28 10:08:46 -0500356 printf("Clock configuration:\n");
Kim Phillipsbae24792006-11-02 19:47:11 -0600357 printf(" Coherent System Bus: %4d MHz\n", gd->csb_clk / 1000000);
358 printf(" Core: %4d MHz\n", gd->core_clk / 1000000);
Dave Liue740c462006-12-07 21:13:15 +0800359#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
Kim Phillipsbae24792006-11-02 19:47:11 -0600360 printf(" QE: %4d MHz\n", gd->qe_clk / 1000000);
Dave Liue740c462006-12-07 21:13:15 +0800361 printf(" BRG: %4d MHz\n", gd->brg_clk / 1000000);
Dave Liua46daea2006-11-03 19:33:44 -0600362#endif
Kim Phillipsbae24792006-11-02 19:47:11 -0600363 printf(" Local Bus Controller:%4d MHz\n", gd->lbiu_clk / 1000000);
364 printf(" Local Bus: %4d MHz\n", gd->lclk_clk / 1000000);
365 printf(" DDR: %4d MHz\n", gd->ddr_clk / 1000000);
Dave Liue740c462006-12-07 21:13:15 +0800366#if defined(CONFIG_MPC8360)
Kim Phillipsbae24792006-11-02 19:47:11 -0600367 printf(" DDR Secondary: %4d MHz\n", gd->ddr_sec_clk / 1000000);
Dave Liua46daea2006-11-03 19:33:44 -0600368#endif
Kim Phillipsbae24792006-11-02 19:47:11 -0600369 printf(" SEC: %4d MHz\n", gd->enc_clk / 1000000);
370 printf(" I2C1: %4d MHz\n", gd->i2c1_clk / 1000000);
Dave Liue740c462006-12-07 21:13:15 +0800371#if !defined(CONFIG_MPC832X)
Kim Phillipsbae24792006-11-02 19:47:11 -0600372 printf(" I2C2: %4d MHz\n", gd->i2c2_clk / 1000000);
Dave Liue740c462006-12-07 21:13:15 +0800373#endif
Kumar Galab7870e72007-01-30 14:08:30 -0600374#if defined(CONFIG_MPC834X)
Kim Phillipsbae24792006-11-02 19:47:11 -0600375 printf(" TSEC1: %4d MHz\n", gd->tsec1_clk / 1000000);
376 printf(" TSEC2: %4d MHz\n", gd->tsec2_clk / 1000000);
377 printf(" USB MPH: %4d MHz\n", gd->usbmph_clk / 1000000);
378 printf(" USB DR: %4d MHz\n", gd->usbdr_clk / 1000000);
Dave Liua46daea2006-11-03 19:33:44 -0600379#endif
Jon Loeligerebc72242005-08-01 13:20:47 -0500380 return 0;
Eran Liberty9095d4a2005-07-28 10:08:46 -0500381}