blob: 505e20bc61c8c4cea9700b5fc5ad49f8610e60f4 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenk1fe2c702003-03-06 21:55:29 +00002/*
3 * (C) Copyright 2002
4 * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
wdenk1fe2c702003-03-06 21:55:29 +00005 */
6
wdenk1fe2c702003-03-06 21:55:29 +00007#include <common.h>
Przemyslaw Marczak2a4f8112015-01-27 13:36:36 +01008#include <errno.h>
9#include <dm.h>
Rajeshwari Shinde53cfac52012-12-26 20:03:12 +000010#include <fdtdec.h>
Tom Rini893cd412022-06-10 22:59:33 -040011#if defined(CONFIG_ARCH_EXYNOS4) || defined(CONFIG_ARCH_EXYNOS5)
Simon Glass0f2af882020-05-10 11:40:05 -060012#include <log.h>
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +000013#include <asm/arch/clk.h>
14#include <asm/arch/cpu.h>
Rajeshwari Shinde53cfac52012-12-26 20:03:12 +000015#include <asm/arch/pinmux.h>
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +000016#else
kevin.morfitt@fearnside-systems.co.uke0d81312009-11-17 18:30:34 +090017#include <asm/arch/s3c24x0_cpu.h>
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +000018#endif
Simon Glass3ba929a2020-10-30 21:38:53 -060019#include <asm/global_data.h>
kevin.morfitt@fearnside-systems.co.uk1464f4d2009-10-10 13:33:11 +090020#include <asm/io.h>
wdenk1fe2c702003-03-06 21:55:29 +000021#include <i2c.h>
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +000022#include "s3c24x0_i2c.h"
wdenk1fe2c702003-03-06 21:55:29 +000023
Przemyslaw Marczak2a4f8112015-01-27 13:36:36 +010024DECLARE_GLOBAL_DATA_PTR;
25
Naveen Krishna Ch40e1e7b2013-10-15 16:01:43 +053026/*
27 * Wait til the byte transfer is completed.
28 *
29 * @param i2c- pointer to the appropriate i2c register bank.
Heinrich Schuchardt47b4c022022-01-19 18:05:50 +010030 * Return: I2C_OK, if transmission was ACKED
Naveen Krishna Ch40e1e7b2013-10-15 16:01:43 +053031 * I2C_NACK, if transmission was NACKED
32 * I2C_NOK_TIMEOUT, if transaction did not complete in I2C_TIMEOUT_MS
33 */
34
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +000035static int WaitForXfer(struct s3c24x0_i2c *i2c)
wdenk1fe2c702003-03-06 21:55:29 +000036{
Naveen Krishna Ch40e1e7b2013-10-15 16:01:43 +053037 ulong start_time = get_timer(0);
wdenk1fe2c702003-03-06 21:55:29 +000038
Naveen Krishna Ch40e1e7b2013-10-15 16:01:43 +053039 do {
40 if (readl(&i2c->iiccon) & I2CCON_IRPND)
41 return (readl(&i2c->iicstat) & I2CSTAT_NACK) ?
42 I2C_NACK : I2C_OK;
43 } while (get_timer(start_time) < I2C_TIMEOUT_MS);
wdenk1fe2c702003-03-06 21:55:29 +000044
Naveen Krishna Ch64a191f2013-10-15 16:02:44 +053045 return I2C_NOK_TOUT;
46}
47
Simon Glass824802d2015-07-02 18:15:46 -060048static void read_write_byte(struct s3c24x0_i2c *i2c)
wdenk1fe2c702003-03-06 21:55:29 +000049{
Simon Glass824802d2015-07-02 18:15:46 -060050 clrbits_le32(&i2c->iiccon, I2CCON_IRPND);
wdenk1fe2c702003-03-06 21:55:29 +000051}
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +000052
53static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd)
54{
55 ulong freq, pres = 16, div;
Tom Rini893cd412022-06-10 22:59:33 -040056#if defined(CONFIG_ARCH_EXYNOS4) || defined(CONFIG_ARCH_EXYNOS5)
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +000057 freq = get_i2c_clk();
58#else
59 freq = get_PCLK();
60#endif
61 /* calculate prescaler and divisor values */
62 if ((freq / pres / (16 + 1)) > speed)
63 /* set prescaler to 512 */
64 pres = 512;
65
66 div = 0;
67 while ((freq / pres / (div + 1)) > speed)
68 div++;
69
70 /* set prescaler, divisor according to freq, also set ACKGEN, IRQ */
71 writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->iiccon);
72
73 /* init to SLAVE REVEIVE and set slaveaddr */
74 writel(0, &i2c->iicstat);
75 writel(slaveadd, &i2c->iicadd);
76 /* program Master Transmit (and implicit STOP) */
77 writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
78}
Naveen Krishna Ch64a191f2013-10-15 16:02:44 +053079
Tom Rinifc917de2021-08-17 17:59:42 -040080#define SYS_I2C_S3C24X0_SLAVE_ADDR 0
81
Przemyslaw Marczak2a4f8112015-01-27 13:36:36 +010082static int s3c24x0_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
Piotr Wilczek58bbd2b2013-11-20 10:43:49 +010083{
Simon Glass365c3da2016-11-23 06:34:42 -070084 struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
Piotr Wilczek58bbd2b2013-11-20 10:43:49 +010085
Piotr Wilczek58bbd2b2013-11-20 10:43:49 +010086 i2c_bus->clock_frequency = speed;
87
Simon Glassb9d7f992016-11-23 06:34:43 -070088 i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency,
Jaehoon Chung9ac1fdf2017-01-09 14:47:51 +090089 SYS_I2C_S3C24X0_SLAVE_ADDR);
Piotr Wilczek58bbd2b2013-11-20 10:43:49 +010090
91 return 0;
92}
93
Naveen Krishna Ch64a191f2013-10-15 16:02:44 +053094/*
wdenk49c3f672003-10-08 22:33:00 +000095 * cmd_type is 0 for write, 1 for read.
96 *
97 * addr_len can take any value from 0-255, it is only limited
98 * by the char, we could make it larger if needed. If it is
99 * 0 we skip the address write cycle.
100 */
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +0000101static int i2c_transfer(struct s3c24x0_i2c *i2c,
102 unsigned char cmd_type,
103 unsigned char chip,
104 unsigned char addr[],
105 unsigned char addr_len,
106 unsigned char data[],
107 unsigned short data_len)
wdenk1fe2c702003-03-06 21:55:29 +0000108{
Naveen Krishna Ch40e1e7b2013-10-15 16:01:43 +0530109 int i = 0, result;
110 ulong start_time = get_timer(0);
wdenk1fe2c702003-03-06 21:55:29 +0000111
wdenk49c3f672003-10-08 22:33:00 +0000112 if (data == 0 || data_len == 0) {
113 /*Don't support data transfer of no length or to address 0 */
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +0000114 debug("i2c_transfer: bad call\n");
wdenk49c3f672003-10-08 22:33:00 +0000115 return I2C_NOK;
116 }
wdenk1fe2c702003-03-06 21:55:29 +0000117
Naveen Krishna Ch40e1e7b2013-10-15 16:01:43 +0530118 while (readl(&i2c->iicstat) & I2CSTAT_BSY) {
119 if (get_timer(start_time) > I2C_TIMEOUT_MS)
120 return I2C_NOK_TOUT;
wdenk49c3f672003-10-08 22:33:00 +0000121 }
wdenk1fe2c702003-03-06 21:55:29 +0000122
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +0000123 writel(readl(&i2c->iiccon) | I2CCON_ACKGEN, &i2c->iiccon);
wdenk1fe2c702003-03-06 21:55:29 +0000124
Naveen Krishna Ch40e1e7b2013-10-15 16:01:43 +0530125 /* Get the slave chip address going */
126 writel(chip, &i2c->iicds);
127 if ((cmd_type == I2C_WRITE) || (addr && addr_len))
128 writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
129 &i2c->iicstat);
130 else
131 writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP,
132 &i2c->iicstat);
133
134 /* Wait for chip address to transmit. */
135 result = WaitForXfer(i2c);
136 if (result != I2C_OK)
137 goto bailout;
wdenk1fe2c702003-03-06 21:55:29 +0000138
Naveen Krishna Ch40e1e7b2013-10-15 16:01:43 +0530139 /* If register address needs to be transmitted - do it now. */
140 if (addr && addr_len) {
141 while ((i < addr_len) && (result == I2C_OK)) {
142 writel(addr[i++], &i2c->iicds);
Simon Glass824802d2015-07-02 18:15:46 -0600143 read_write_byte(i2c);
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +0000144 result = WaitForXfer(i2c);
Naveen Krishna Ch40e1e7b2013-10-15 16:01:43 +0530145 }
146 i = 0;
147 if (result != I2C_OK)
148 goto bailout;
149 }
wdenk1fe2c702003-03-06 21:55:29 +0000150
Naveen Krishna Ch40e1e7b2013-10-15 16:01:43 +0530151 switch (cmd_type) {
152 case I2C_WRITE:
153 while ((i < data_len) && (result == I2C_OK)) {
154 writel(data[i++], &i2c->iicds);
Simon Glass824802d2015-07-02 18:15:46 -0600155 read_write_byte(i2c);
Naveen Krishna Ch40e1e7b2013-10-15 16:01:43 +0530156 result = WaitForXfer(i2c);
157 }
wdenk49c3f672003-10-08 22:33:00 +0000158 break;
wdenk1fe2c702003-03-06 21:55:29 +0000159
wdenk7539dea2003-06-19 23:01:32 +0000160 case I2C_READ:
wdenk49c3f672003-10-08 22:33:00 +0000161 if (addr && addr_len) {
Naveen Krishna Ch40e1e7b2013-10-15 16:01:43 +0530162 /*
163 * Register address has been sent, now send slave chip
164 * address again to start the actual read transaction.
165 */
C Nauman383c43e2010-10-26 23:04:31 +0900166 writel(chip, &i2c->iicds);
wdenk1fe2c702003-03-06 21:55:29 +0000167
Naveen Krishna Ch40e1e7b2013-10-15 16:01:43 +0530168 /* Generate a re-START. */
Rajeshwari Shindee076adf2013-02-19 02:19:45 +0000169 writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP,
170 &i2c->iicstat);
Simon Glass824802d2015-07-02 18:15:46 -0600171 read_write_byte(i2c);
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +0000172 result = WaitForXfer(i2c);
wdenk49c3f672003-10-08 22:33:00 +0000173
Naveen Krishna Ch40e1e7b2013-10-15 16:01:43 +0530174 if (result != I2C_OK)
175 goto bailout;
wdenk1fe2c702003-03-06 21:55:29 +0000176 }
wdenk1fe2c702003-03-06 21:55:29 +0000177
Naveen Krishna Ch40e1e7b2013-10-15 16:01:43 +0530178 while ((i < data_len) && (result == I2C_OK)) {
179 /* disable ACK for final READ */
180 if (i == data_len - 1)
181 writel(readl(&i2c->iiccon)
182 & ~I2CCON_ACKGEN,
183 &i2c->iiccon);
Simon Glass824802d2015-07-02 18:15:46 -0600184 read_write_byte(i2c);
Naveen Krishna Ch40e1e7b2013-10-15 16:01:43 +0530185 result = WaitForXfer(i2c);
186 data[i++] = readl(&i2c->iicds);
187 }
188 if (result == I2C_NACK)
189 result = I2C_OK; /* Normal terminated read. */
wdenk49c3f672003-10-08 22:33:00 +0000190 break;
wdenk1fe2c702003-03-06 21:55:29 +0000191
192 default:
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +0000193 debug("i2c_transfer: bad call\n");
wdenk49c3f672003-10-08 22:33:00 +0000194 result = I2C_NOK;
195 break;
196 }
wdenk1fe2c702003-03-06 21:55:29 +0000197
Naveen Krishna Ch40e1e7b2013-10-15 16:01:43 +0530198bailout:
199 /* Send STOP. */
200 writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
Simon Glass824802d2015-07-02 18:15:46 -0600201 read_write_byte(i2c);
Naveen Krishna Ch40e1e7b2013-10-15 16:01:43 +0530202
Rajeshwari Shinde4b4480a2012-07-23 21:23:53 +0000203 return result;
wdenk1fe2c702003-03-06 21:55:29 +0000204}
205
Przemyslaw Marczak2a4f8112015-01-27 13:36:36 +0100206static int s3c24x0_i2c_probe(struct udevice *dev, uint chip, uint chip_flags)
wdenk1fe2c702003-03-06 21:55:29 +0000207{
Simon Glass365c3da2016-11-23 06:34:42 -0700208 struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
wdenk49c3f672003-10-08 22:33:00 +0000209 uchar buf[1];
Naveen Krishna Ch64a191f2013-10-15 16:02:44 +0530210 int ret;
wdenk1fe2c702003-03-06 21:55:29 +0000211
wdenk49c3f672003-10-08 22:33:00 +0000212 buf[0] = 0;
wdenk1fe2c702003-03-06 21:55:29 +0000213
wdenk49c3f672003-10-08 22:33:00 +0000214 /*
215 * What is needed is to send the chip address and verify that the
216 * address was <ACK>ed (i.e. there was a chip at that address which
217 * drove the data line low).
218 */
Simon Glassb9d7f992016-11-23 06:34:43 -0700219 ret = i2c_transfer(i2c_bus->regs, I2C_READ, chip << 1, 0, 0, buf, 1);
Naveen Krishna Ch64a191f2013-10-15 16:02:44 +0530220
Naveen Krishna Ch64a191f2013-10-15 16:02:44 +0530221 return ret != I2C_OK;
wdenk1fe2c702003-03-06 21:55:29 +0000222}
223
Simon Glasse3b8c862015-07-02 18:15:47 -0600224static int s3c24x0_do_msg(struct s3c24x0_i2c_bus *i2c_bus, struct i2c_msg *msg,
225 int seq)
Przemyslaw Marczak2a4f8112015-01-27 13:36:36 +0100226{
Simon Glasse3b8c862015-07-02 18:15:47 -0600227 struct s3c24x0_i2c *i2c = i2c_bus->regs;
228 bool is_read = msg->flags & I2C_M_RD;
229 uint status;
230 uint addr;
231 int ret, i;
Przemyslaw Marczak2a4f8112015-01-27 13:36:36 +0100232
Simon Glasse3b8c862015-07-02 18:15:47 -0600233 if (!seq)
234 setbits_le32(&i2c->iiccon, I2CCON_ACKGEN);
235
236 /* Get the slave chip address going */
237 addr = msg->addr << 1;
238 writel(addr, &i2c->iicds);
239 status = I2C_TXRX_ENA | I2C_START_STOP;
240 if (is_read)
241 status |= I2C_MODE_MR;
242 else
243 status |= I2C_MODE_MT;
244 writel(status, &i2c->iicstat);
245 if (seq)
246 read_write_byte(i2c);
247
248 /* Wait for chip address to transmit */
249 ret = WaitForXfer(i2c);
250 if (ret)
251 goto err;
252
253 if (is_read) {
254 for (i = 0; !ret && i < msg->len; i++) {
255 /* disable ACK for final READ */
256 if (i == msg->len - 1)
257 clrbits_le32(&i2c->iiccon, I2CCON_ACKGEN);
258 read_write_byte(i2c);
259 ret = WaitForXfer(i2c);
260 msg->buf[i] = readl(&i2c->iicds);
261 }
262 if (ret == I2C_NACK)
263 ret = I2C_OK; /* Normal terminated read */
Przemyslaw Marczak2a4f8112015-01-27 13:36:36 +0100264 } else {
Simon Glasse3b8c862015-07-02 18:15:47 -0600265 for (i = 0; !ret && i < msg->len; i++) {
266 writel(msg->buf[i], &i2c->iicds);
267 read_write_byte(i2c);
268 ret = WaitForXfer(i2c);
269 }
Przemyslaw Marczak2a4f8112015-01-27 13:36:36 +0100270 }
271
Simon Glasse3b8c862015-07-02 18:15:47 -0600272err:
273 return ret;
Przemyslaw Marczak2a4f8112015-01-27 13:36:36 +0100274}
275
276static int s3c24x0_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
277 int nmsgs)
278{
279 struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
Simon Glasse3b8c862015-07-02 18:15:47 -0600280 struct s3c24x0_i2c *i2c = i2c_bus->regs;
281 ulong start_time;
282 int ret, i;
Przemyslaw Marczak2a4f8112015-01-27 13:36:36 +0100283
Simon Glasse3b8c862015-07-02 18:15:47 -0600284 start_time = get_timer(0);
285 while (readl(&i2c->iicstat) & I2CSTAT_BSY) {
286 if (get_timer(start_time) > I2C_TIMEOUT_MS) {
287 debug("Timeout\n");
288 return -ETIMEDOUT;
Przemyslaw Marczak2a4f8112015-01-27 13:36:36 +0100289 }
Przemyslaw Marczak2a4f8112015-01-27 13:36:36 +0100290 }
291
Simon Glasse3b8c862015-07-02 18:15:47 -0600292 for (ret = 0, i = 0; !ret && i < nmsgs; i++)
293 ret = s3c24x0_do_msg(i2c_bus, &msg[i], i);
294
295 /* Send STOP */
296 writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat);
297 read_write_byte(i2c);
298
299 return ret ? -EREMOTEIO : 0;
Przemyslaw Marczak2a4f8112015-01-27 13:36:36 +0100300}
301
Simon Glassaad29ae2020-12-03 16:55:21 -0700302static int s3c_i2c_of_to_plat(struct udevice *dev)
Przemyslaw Marczak2a4f8112015-01-27 13:36:36 +0100303{
304 const void *blob = gd->fdt_blob;
305 struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
Simon Glassb9d7f992016-11-23 06:34:43 -0700306 int node;
Przemyslaw Marczak2a4f8112015-01-27 13:36:36 +0100307
Simon Glassdd79d6e2017-01-17 16:52:55 -0700308 node = dev_of_offset(dev);
Przemyslaw Marczak2a4f8112015-01-27 13:36:36 +0100309
Masahiro Yamada1096ae12020-07-17 14:36:46 +0900310 i2c_bus->regs = dev_read_addr_ptr(dev);
Przemyslaw Marczak2a4f8112015-01-27 13:36:36 +0100311
312 i2c_bus->id = pinmux_decode_periph_id(blob, node);
313
Simon Glassf0c99c52020-01-23 11:48:22 -0700314 i2c_bus->clock_frequency =
315 dev_read_u32_default(dev, "clock-frequency",
316 I2C_SPEED_STANDARD_RATE);
Przemyslaw Marczak2a4f8112015-01-27 13:36:36 +0100317 i2c_bus->node = node;
Simon Glass75e534b2020-12-16 21:20:07 -0700318 i2c_bus->bus_num = dev_seq(dev);
Przemyslaw Marczak2a4f8112015-01-27 13:36:36 +0100319
Simon Glassb9d7f992016-11-23 06:34:43 -0700320 exynos_pinmux_config(i2c_bus->id, 0);
Przemyslaw Marczak2a4f8112015-01-27 13:36:36 +0100321
322 i2c_bus->active = true;
323
324 return 0;
325}
326
327static const struct dm_i2c_ops s3c_i2c_ops = {
328 .xfer = s3c24x0_i2c_xfer,
329 .probe_chip = s3c24x0_i2c_probe,
330 .set_bus_speed = s3c24x0_i2c_set_bus_speed,
331};
332
333static const struct udevice_id s3c_i2c_ids[] = {
Simon Glassb9d7f992016-11-23 06:34:43 -0700334 { .compatible = "samsung,s3c2440-i2c" },
Przemyslaw Marczak2a4f8112015-01-27 13:36:36 +0100335 { }
336};
337
338U_BOOT_DRIVER(i2c_s3c) = {
339 .name = "i2c_s3c",
340 .id = UCLASS_I2C,
341 .of_match = s3c_i2c_ids,
Simon Glassaad29ae2020-12-03 16:55:21 -0700342 .of_to_plat = s3c_i2c_of_to_plat,
Simon Glass8a2b47f2020-12-03 16:55:17 -0700343 .priv_auto = sizeof(struct s3c24x0_i2c_bus),
Przemyslaw Marczak2a4f8112015-01-27 13:36:36 +0100344 .ops = &s3c_i2c_ops,
345};