blob: 86b9fb57c832cb78250aabe79b2bbb307650b379 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Sascha Hauer15ea70f2008-03-26 20:40:49 +01002/*
Marek Vasut94cb8422011-09-22 09:22:12 +00003 * i2c driver for Freescale i.MX series
Sascha Hauer15ea70f2008-03-26 20:40:49 +01004 *
5 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
Marek Vasut94cb8422011-09-22 09:22:12 +00006 * (c) 2011 Marek Vasut <marek.vasut@gmail.com>
Biwen Li70a81582020-07-02 11:13:00 +08007 * Copyright 2020 NXP
Marek Vasut94cb8422011-09-22 09:22:12 +00008 *
9 * Based on i2c-imx.c from linux kernel:
10 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de>
11 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de>
12 * Copyright (C) 2007 RightHand Technologies, Inc.
13 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
14 *
Sascha Hauer15ea70f2008-03-26 20:40:49 +010015 */
16
17#include <common.h>
Simon Glass0f2af882020-05-10 11:40:05 -060018#include <log.h>
Liu Hui-R64343447beb12011-01-03 22:27:39 +000019#include <asm/arch/clock.h>
Stefano Babic78129d92011-03-14 15:43:56 +010020#include <asm/arch/imx-regs.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060021#include <asm/global_data.h>
Simon Glass9bc15642020-02-03 07:36:16 -070022#include <dm/device_compat.h>
Simon Glassdbd79542020-05-10 11:40:11 -060023#include <linux/delay.h>
Masahiro Yamada56a931c2016-09-21 11:28:55 +090024#include <linux/errno.h>
Stefano Babic33731bc2017-06-29 10:16:06 +020025#include <asm/mach-imx/mxc_i2c.h>
Peng Fan23d4ee32020-05-01 22:08:35 +080026#include <asm/mach-imx/sys_proto.h>
Troy Kisky2254b7f2012-07-19 08:18:03 +000027#include <asm/io.h>
Marek Vasut5f1291e2011-10-26 00:05:44 +000028#include <i2c.h>
Troy Kiskyf024a3b2012-07-19 08:18:09 +000029#include <watchdog.h>
Peng Fan8262cb12015-05-15 07:29:12 +080030#include <dm.h>
Peng Fan4f1a5812016-03-11 16:47:50 +080031#include <dm/pinctrl.h>
Peng Fan8262cb12015-05-15 07:29:12 +080032#include <fdtdec.h>
Sascha Hauer15ea70f2008-03-26 20:40:49 +010033
York Suna4c02662014-02-10 14:02:52 -080034DECLARE_GLOBAL_DATA_PTR;
35
Peng Fan8262cb12015-05-15 07:29:12 +080036#define I2C_QUIRK_FLAG (1 << 0)
37
38#define IMX_I2C_REGSHIFT 2
39#define VF610_I2C_REGSHIFT 0
Yuan Yaod40c8852016-06-08 18:24:51 +080040
41#define I2C_EARLY_INIT_INDEX 0
Tom Rini6a5dccc2022-11-16 13:10:41 -050042#ifdef CFG_SYS_I2C_IFDR_DIV
43#define I2C_IFDR_DIV_CONSERVATIVE CFG_SYS_I2C_IFDR_DIV
Yuan Yaod40c8852016-06-08 18:24:51 +080044#else
45#define I2C_IFDR_DIV_CONSERVATIVE 0x7e
46#endif
47
Peng Fan8262cb12015-05-15 07:29:12 +080048/* Register index */
49#define IADR 0
50#define IFDR 1
51#define I2CR 2
52#define I2SR 3
53#define I2DR 4
Sascha Hauer15ea70f2008-03-26 20:40:49 +010054
Sascha Hauer15ea70f2008-03-26 20:40:49 +010055#define I2CR_IIEN (1 << 6)
56#define I2CR_MSTA (1 << 5)
57#define I2CR_MTX (1 << 4)
58#define I2CR_TX_NO_AK (1 << 3)
59#define I2CR_RSTA (1 << 2)
60
61#define I2SR_ICF (1 << 7)
62#define I2SR_IBB (1 << 5)
Troy Kisky8ff683a2012-07-19 08:18:15 +000063#define I2SR_IAL (1 << 4)
Sascha Hauer15ea70f2008-03-26 20:40:49 +010064#define I2SR_IIF (1 << 1)
65#define I2SR_RX_NO_AK (1 << 0)
66
Alison Wangcf508002013-06-17 15:30:39 +080067#ifdef I2C_QUIRK_REG
68#define I2CR_IEN (0 << 7)
69#define I2CR_IDIS (1 << 7)
70#define I2SR_IIF_CLEAR (1 << 1)
71#else
72#define I2CR_IEN (1 << 7)
73#define I2CR_IDIS (0 << 7)
74#define I2SR_IIF_CLEAR (0 << 1)
75#endif
76
Alison Wangcf508002013-06-17 15:30:39 +080077#ifdef I2C_QUIRK_REG
78static u16 i2c_clk_div[60][2] = {
79 { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
80 { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },
81 { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },
82 { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 },
83 { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 },
84 { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
85 { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
86 { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
87 { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
88 { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
89 { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
90 { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
91 { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
92 { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
93 { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
94};
95#else
Marek Vasut94cb8422011-09-22 09:22:12 +000096static u16 i2c_clk_div[50][2] = {
97 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
98 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
99 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
100 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
101 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
102 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
103 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
104 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
105 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
106 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
107 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
108 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
109 { 3072, 0x1E }, { 3840, 0x1F }
110};
Alison Wangcf508002013-06-17 15:30:39 +0800111#endif
Sascha Hauer15ea70f2008-03-26 20:40:49 +0100112
Marek Vasut94cb8422011-09-22 09:22:12 +0000113/*
114 * Calculate and set proper clock divider
115 */
Peng Fan8262cb12015-05-15 07:29:12 +0800116static uint8_t i2c_imx_get_clk(struct mxc_i2c_bus *i2c_bus, unsigned int rate)
Sascha Hauer15ea70f2008-03-26 20:40:49 +0100117{
Marek Vasut94cb8422011-09-22 09:22:12 +0000118 unsigned int i2c_clk_rate;
119 unsigned int div;
Marek Vasut5f1291e2011-10-26 00:05:44 +0000120 u8 clk_div;
Sascha Hauer15ea70f2008-03-26 20:40:49 +0100121
Liu Hui-R64343447beb12011-01-03 22:27:39 +0000122#if defined(CONFIG_MX31)
Stefano Babic22121722011-01-20 07:50:44 +0000123 struct clock_control_regs *sc_regs =
124 (struct clock_control_regs *)CCM_BASE;
Marek Vasut94cb8422011-09-22 09:22:12 +0000125
Guennadi Liakhovetski3314fc62009-02-13 09:23:36 +0100126 /* start the required I2C clock */
Troy Kisky8462c632012-04-24 17:33:25 +0000127 writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET),
Stefano Babic22121722011-01-20 07:50:44 +0000128 &sc_regs->cgr0);
Liu Hui-R64343447beb12011-01-03 22:27:39 +0000129#endif
Guennadi Liakhovetski3314fc62009-02-13 09:23:36 +0100130
Marek Vasut94cb8422011-09-22 09:22:12 +0000131 /* Divider value calculation */
Peng Fan87ea5622019-08-08 01:43:30 +0000132#if CONFIG_IS_ENABLED(CLK)
133 i2c_clk_rate = clk_get_rate(&i2c_bus->per_clk);
134#else
Matthias Weisser99ba3422012-09-24 02:46:53 +0000135 i2c_clk_rate = mxc_get_clock(MXC_I2C_CLK);
Peng Fan87ea5622019-08-08 01:43:30 +0000136#endif
137
Marek Vasut94cb8422011-09-22 09:22:12 +0000138 div = (i2c_clk_rate + rate - 1) / rate;
139 if (div < i2c_clk_div[0][0])
Marek Vasut4f274442011-09-27 06:34:11 +0000140 clk_div = 0;
Marek Vasut94cb8422011-09-22 09:22:12 +0000141 else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
Marek Vasut4f274442011-09-27 06:34:11 +0000142 clk_div = ARRAY_SIZE(i2c_clk_div) - 1;
Marek Vasut94cb8422011-09-22 09:22:12 +0000143 else
Marek Vasut4f274442011-09-27 06:34:11 +0000144 for (clk_div = 0; i2c_clk_div[clk_div][0] < div; clk_div++)
Marek Vasut94cb8422011-09-22 09:22:12 +0000145 ;
146
147 /* Store divider value */
Marek Vasut5f1291e2011-10-26 00:05:44 +0000148 return clk_div;
Marek Vasut94cb8422011-09-22 09:22:12 +0000149}
Sascha Hauer15ea70f2008-03-26 20:40:49 +0100150
Marek Vasut94cb8422011-09-22 09:22:12 +0000151/*
Troy Kiskyae447602012-07-19 08:18:18 +0000152 * Set I2C Bus speed
Marek Vasut94cb8422011-09-22 09:22:12 +0000153 */
Peng Fan8262cb12015-05-15 07:29:12 +0800154static int bus_i2c_set_bus_speed(struct mxc_i2c_bus *i2c_bus, int speed)
Marek Vasut94cb8422011-09-22 09:22:12 +0000155{
Peng Fan8262cb12015-05-15 07:29:12 +0800156 ulong base = i2c_bus->base;
157 bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
158 u8 clk_idx = i2c_imx_get_clk(i2c_bus, speed);
Marek Vasut5f1291e2011-10-26 00:05:44 +0000159 u8 idx = i2c_clk_div[clk_idx][1];
Peng Fan8262cb12015-05-15 07:29:12 +0800160 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
Marek Vasut5f1291e2011-10-26 00:05:44 +0000161
Heiko Schocher24ebcf22015-05-18 10:58:12 +0200162 if (!base)
Simon Glassf44b4bf2017-09-17 16:54:53 -0600163 return -EINVAL;
Heiko Schocher24ebcf22015-05-18 10:58:12 +0200164
Marek Vasut5f1291e2011-10-26 00:05:44 +0000165 /* Store divider value */
Peng Fan8262cb12015-05-15 07:29:12 +0800166 writeb(idx, base + (IFDR << reg_shift));
Marek Vasut5f1291e2011-10-26 00:05:44 +0000167
Troy Kiskye6fa4d72012-07-19 08:18:12 +0000168 /* Reset module */
Peng Fan8262cb12015-05-15 07:29:12 +0800169 writeb(I2CR_IDIS, base + (I2CR << reg_shift));
170 writeb(0, base + (I2SR << reg_shift));
Marek Vasut4f274442011-09-27 06:34:11 +0000171 return 0;
172}
173
Troy Kiskyf024a3b2012-07-19 08:18:09 +0000174#define ST_BUS_IDLE (0 | (I2SR_IBB << 8))
175#define ST_BUS_BUSY (I2SR_IBB | (I2SR_IBB << 8))
176#define ST_IIF (I2SR_IIF | (I2SR_IIF << 8))
Stefano Babic848bb992011-01-20 07:51:31 +0000177
Peng Fan8262cb12015-05-15 07:29:12 +0800178static int wait_for_sr_state(struct mxc_i2c_bus *i2c_bus, unsigned state)
Sascha Hauer15ea70f2008-03-26 20:40:49 +0100179{
Troy Kiskyf024a3b2012-07-19 08:18:09 +0000180 unsigned sr;
181 ulong elapsed;
Peng Fan8262cb12015-05-15 07:29:12 +0800182 bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
183 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
184 ulong base = i2c_bus->base;
Troy Kiskyf024a3b2012-07-19 08:18:09 +0000185 ulong start_time = get_timer(0);
186 for (;;) {
Peng Fan8262cb12015-05-15 07:29:12 +0800187 sr = readb(base + (I2SR << reg_shift));
Troy Kisky8ff683a2012-07-19 08:18:15 +0000188 if (sr & I2SR_IAL) {
Peng Fan8262cb12015-05-15 07:29:12 +0800189 if (quirk)
190 writeb(sr | I2SR_IAL, base +
191 (I2SR << reg_shift));
192 else
193 writeb(sr & ~I2SR_IAL, base +
194 (I2SR << reg_shift));
Troy Kisky8ff683a2012-07-19 08:18:15 +0000195 printf("%s: Arbitration lost sr=%x cr=%x state=%x\n",
Peng Fan8262cb12015-05-15 07:29:12 +0800196 __func__, sr, readb(base + (I2CR << reg_shift)),
197 state);
Troy Kisky8ff683a2012-07-19 08:18:15 +0000198 return -ERESTART;
199 }
Troy Kiskyf024a3b2012-07-19 08:18:09 +0000200 if ((sr & (state >> 8)) == (unsigned char)state)
201 return sr;
Stefan Roese80877fa2022-09-02 14:10:46 +0200202 schedule();
Troy Kiskyf024a3b2012-07-19 08:18:09 +0000203 elapsed = get_timer(start_time);
204 if (elapsed > (CONFIG_SYS_HZ / 10)) /* .1 seconds */
205 break;
Marek Vasut94cb8422011-09-22 09:22:12 +0000206 }
Troy Kiskyf024a3b2012-07-19 08:18:09 +0000207 printf("%s: failed sr=%x cr=%x state=%x\n", __func__,
Peng Fan8262cb12015-05-15 07:29:12 +0800208 sr, readb(base + (I2CR << reg_shift)), state);
Troy Kisky752ac8f2012-07-19 08:18:04 +0000209 return -ETIMEDOUT;
Sascha Hauer15ea70f2008-03-26 20:40:49 +0100210}
211
Peng Fan8262cb12015-05-15 07:29:12 +0800212static int tx_byte(struct mxc_i2c_bus *i2c_bus, u8 byte)
Stefano Babic848bb992011-01-20 07:51:31 +0000213{
Troy Kisky752ac8f2012-07-19 08:18:04 +0000214 int ret;
Peng Fan8262cb12015-05-15 07:29:12 +0800215 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
216 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
217 ulong base = i2c_bus->base;
Stefano Babic848bb992011-01-20 07:51:31 +0000218
Peng Fan8262cb12015-05-15 07:29:12 +0800219 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
220 writeb(byte, base + (I2DR << reg_shift));
221
222 ret = wait_for_sr_state(i2c_bus, ST_IIF);
Troy Kisky752ac8f2012-07-19 08:18:04 +0000223 if (ret < 0)
224 return ret;
Troy Kisky752ac8f2012-07-19 08:18:04 +0000225 if (ret & I2SR_RX_NO_AK)
Simon Glassf44b4bf2017-09-17 16:54:53 -0600226 return -EREMOTEIO;
Troy Kisky752ac8f2012-07-19 08:18:04 +0000227 return 0;
Marek Vasut94cb8422011-09-22 09:22:12 +0000228}
Peng Fan8262cb12015-05-15 07:29:12 +0800229
230/*
231 * Stub implementations for outer i2c slave operations.
232 */
233void __i2c_force_reset_slave(void)
234{
235}
236void i2c_force_reset_slave(void)
237 __attribute__((weak, alias("__i2c_force_reset_slave")));
Stefano Babic848bb992011-01-20 07:51:31 +0000238
Marek Vasut94cb8422011-09-22 09:22:12 +0000239/*
Troy Kiskyfef163f2012-07-19 08:18:13 +0000240 * Stop I2C transaction
Marek Vasut94cb8422011-09-22 09:22:12 +0000241 */
Peng Fan8262cb12015-05-15 07:29:12 +0800242static void i2c_imx_stop(struct mxc_i2c_bus *i2c_bus)
Sascha Hauer15ea70f2008-03-26 20:40:49 +0100243{
Troy Kiskyf024a3b2012-07-19 08:18:09 +0000244 int ret;
Peng Fan8262cb12015-05-15 07:29:12 +0800245 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
246 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
247 ulong base = i2c_bus->base;
248 unsigned int temp = readb(base + (I2CR << reg_shift));
Sascha Hauer15ea70f2008-03-26 20:40:49 +0100249
Troy Kisky1ac1e452012-07-19 08:18:02 +0000250 temp &= ~(I2CR_MSTA | I2CR_MTX);
Peng Fan8262cb12015-05-15 07:29:12 +0800251 writeb(temp, base + (I2CR << reg_shift));
252 ret = wait_for_sr_state(i2c_bus, ST_BUS_IDLE);
Troy Kiskyf024a3b2012-07-19 08:18:09 +0000253 if (ret < 0)
254 printf("%s:trigger stop failed\n", __func__);
Sascha Hauer15ea70f2008-03-26 20:40:49 +0100255}
256
Marek Vasut94cb8422011-09-22 09:22:12 +0000257/*
Troy Kisky14db6f22012-07-19 08:18:06 +0000258 * Send start signal, chip address and
259 * write register address
Marek Vasut94cb8422011-09-22 09:22:12 +0000260 */
Peng Fan8262cb12015-05-15 07:29:12 +0800261static int i2c_init_transfer_(struct mxc_i2c_bus *i2c_bus, u8 chip,
262 u32 addr, int alen)
Sascha Hauer15ea70f2008-03-26 20:40:49 +0100263{
Troy Kiskya974bcc2012-07-19 08:18:11 +0000264 unsigned int temp;
265 int ret;
Peng Fan8262cb12015-05-15 07:29:12 +0800266 bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
267 ulong base = i2c_bus->base;
268 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
269
270 /* Reset i2c slave */
271 i2c_force_reset_slave();
Troy Kiskya974bcc2012-07-19 08:18:11 +0000272
273 /* Enable I2C controller */
Peng Fan8262cb12015-05-15 07:29:12 +0800274 if (quirk)
275 ret = readb(base + (I2CR << reg_shift)) & I2CR_IDIS;
276 else
277 ret = !(readb(base + (I2CR << reg_shift)) & I2CR_IEN);
278
279 if (ret) {
280 writeb(I2CR_IEN, base + (I2CR << reg_shift));
Troy Kiskyfef163f2012-07-19 08:18:13 +0000281 /* Wait for controller to be stable */
282 udelay(50);
283 }
Peng Fan8262cb12015-05-15 07:29:12 +0800284
285 if (readb(base + (IADR << reg_shift)) == (chip << 1))
286 writeb((chip << 1) ^ 2, base + (IADR << reg_shift));
287 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
288 ret = wait_for_sr_state(i2c_bus, ST_BUS_IDLE);
Troy Kiskyfef163f2012-07-19 08:18:13 +0000289 if (ret < 0)
Troy Kiskyeca037a2012-07-19 08:18:16 +0000290 return ret;
Troy Kiskya974bcc2012-07-19 08:18:11 +0000291
292 /* Start I2C transaction */
Peng Fan8262cb12015-05-15 07:29:12 +0800293 temp = readb(base + (I2CR << reg_shift));
Troy Kiskya974bcc2012-07-19 08:18:11 +0000294 temp |= I2CR_MSTA;
Peng Fan8262cb12015-05-15 07:29:12 +0800295 writeb(temp, base + (I2CR << reg_shift));
Troy Kiskya974bcc2012-07-19 08:18:11 +0000296
Peng Fan8262cb12015-05-15 07:29:12 +0800297 ret = wait_for_sr_state(i2c_bus, ST_BUS_BUSY);
Troy Kiskya974bcc2012-07-19 08:18:11 +0000298 if (ret < 0)
Troy Kiskyeca037a2012-07-19 08:18:16 +0000299 return ret;
Troy Kisky14db6f22012-07-19 08:18:06 +0000300
Troy Kiskya974bcc2012-07-19 08:18:11 +0000301 temp |= I2CR_MTX | I2CR_TX_NO_AK;
Peng Fan8262cb12015-05-15 07:29:12 +0800302 writeb(temp, base + (I2CR << reg_shift));
Troy Kiskya974bcc2012-07-19 08:18:11 +0000303
Nandor Hana51f9da2017-11-08 15:35:09 +0000304 if (alen >= 0) {
305 /* write slave address */
306 ret = tx_byte(i2c_bus, chip << 1);
Troy Kisky752ac8f2012-07-19 08:18:04 +0000307 if (ret < 0)
Troy Kiskyeca037a2012-07-19 08:18:16 +0000308 return ret;
Nandor Hana51f9da2017-11-08 15:35:09 +0000309
310 while (alen--) {
311 ret = tx_byte(i2c_bus, (addr >> (alen * 8)) & 0xff);
312 if (ret < 0)
313 return ret;
314 }
Stefano Babic848bb992011-01-20 07:51:31 +0000315 }
Nandor Hana51f9da2017-11-08 15:35:09 +0000316
Troy Kisky14db6f22012-07-19 08:18:06 +0000317 return 0;
Troy Kiskyeca037a2012-07-19 08:18:16 +0000318}
319
Biwen Li70a81582020-07-02 11:13:00 +0800320#if !defined(I2C2_BASE_ADDR)
321#define I2C2_BASE_ADDR 0
322#endif
323
324#if !defined(I2C3_BASE_ADDR)
325#define I2C3_BASE_ADDR 0
326#endif
327
328#if !defined(I2C4_BASE_ADDR)
329#define I2C4_BASE_ADDR 0
330#endif
331
332#if !defined(I2C5_BASE_ADDR)
333#define I2C5_BASE_ADDR 0
334#endif
335
336#if !defined(I2C6_BASE_ADDR)
337#define I2C6_BASE_ADDR 0
338#endif
339
340#if !defined(I2C7_BASE_ADDR)
341#define I2C7_BASE_ADDR 0
342#endif
343
344#if !defined(I2C8_BASE_ADDR)
345#define I2C8_BASE_ADDR 0
346#endif
347
348static struct mxc_i2c_bus mxc_i2c_buses[] = {
349#if defined(CONFIG_ARCH_LS1021A) || defined(CONFIG_VF610) || \
350 defined(CONFIG_FSL_LAYERSCAPE)
351 { 0, I2C1_BASE_ADDR, I2C_QUIRK_FLAG },
352 { 1, I2C2_BASE_ADDR, I2C_QUIRK_FLAG },
353 { 2, I2C3_BASE_ADDR, I2C_QUIRK_FLAG },
354 { 3, I2C4_BASE_ADDR, I2C_QUIRK_FLAG },
355 { 4, I2C5_BASE_ADDR, I2C_QUIRK_FLAG },
356 { 5, I2C6_BASE_ADDR, I2C_QUIRK_FLAG },
357 { 6, I2C7_BASE_ADDR, I2C_QUIRK_FLAG },
358 { 7, I2C8_BASE_ADDR, I2C_QUIRK_FLAG },
359#else
360 { 0, I2C1_BASE_ADDR, 0 },
361 { 1, I2C2_BASE_ADDR, 0 },
362 { 2, I2C3_BASE_ADDR, 0 },
363 { 3, I2C4_BASE_ADDR, 0 },
364 { 4, I2C5_BASE_ADDR, 0 },
365 { 5, I2C6_BASE_ADDR, 0 },
366 { 6, I2C7_BASE_ADDR, 0 },
367 { 7, I2C8_BASE_ADDR, 0 },
368#endif
369};
370
Igor Opaniukf7c91762021-02-09 13:52:45 +0200371#if !CONFIG_IS_ENABLED(DM_I2C)
Peng Fan8262cb12015-05-15 07:29:12 +0800372int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
373{
374 if (i2c_bus && i2c_bus->idle_bus_fn)
375 return i2c_bus->idle_bus_fn(i2c_bus->idle_bus_data);
376 return 0;
377}
378#else
379/*
Peng Fan4f1a5812016-03-11 16:47:50 +0800380 * See Linux Documentation/devicetree/bindings/i2c/i2c-imx.txt
381 * "
382 * scl-gpios: specify the gpio related to SCL pin
383 * sda-gpios: specify the gpio related to SDA pin
384 * add pinctrl to configure i2c pins to gpio function for i2c
385 * bus recovery, call it "gpio" state
386 * "
387 *
388 * The i2c_idle_bus is an implementation following Linux Kernel.
Peng Fan8262cb12015-05-15 07:29:12 +0800389 */
Peng Fan4f1a5812016-03-11 16:47:50 +0800390int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
Peng Fan8262cb12015-05-15 07:29:12 +0800391{
Peng Fan4f1a5812016-03-11 16:47:50 +0800392 struct udevice *bus = i2c_bus->bus;
Lukasz Majewskibc9aad62019-04-04 12:35:34 +0200393 struct dm_i2c_bus *i2c = dev_get_uclass_priv(bus);
Peng Fan4f1a5812016-03-11 16:47:50 +0800394 struct gpio_desc *scl_gpio = &i2c_bus->scl_gpio;
395 struct gpio_desc *sda_gpio = &i2c_bus->sda_gpio;
Lukasz Majewskibc9aad62019-04-04 12:35:34 +0200396 int sda, scl, idle_sclks;
Peng Fan4f1a5812016-03-11 16:47:50 +0800397 int i, ret = 0;
398 ulong elapsed, start_time;
Peng Fan8262cb12015-05-15 07:29:12 +0800399
Peng Fan4f1a5812016-03-11 16:47:50 +0800400 if (pinctrl_select_state(bus, "gpio")) {
401 dev_dbg(bus, "Can not to switch to use gpio pinmux\n");
402 /*
403 * GPIO pinctrl for i2c force idle is not a must,
404 * but it is strongly recommended to be used.
405 * Because it can help you to recover from bad
406 * i2c bus state. Do not return failure, because
407 * it is not a must.
408 */
409 return 0;
410 }
411
412 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
413 dm_gpio_set_dir_flags(sda_gpio, GPIOD_IS_IN);
414 scl = dm_gpio_get_value(scl_gpio);
415 sda = dm_gpio_get_value(sda_gpio);
416
417 if ((sda & scl) == 1)
418 goto exit; /* Bus is idle already */
419
Lukasz Majewskibc9aad62019-04-04 12:35:34 +0200420 /*
421 * In most cases it is just enough to generate 8 + 1 SCLK
422 * clocks to recover I2C slave device from 'stuck' state
423 * (when for example SW reset was performed, in the middle of
424 * I2C transmission).
425 *
426 * However, there are devices which send data in packets of
427 * N bytes (N > 1). In such case we do need N * 8 + 1 SCLK
428 * clocks.
429 */
430 idle_sclks = 8 + 1;
431
432 if (i2c->max_transaction_bytes > 0)
433 idle_sclks = i2c->max_transaction_bytes * 8 + 1;
Peng Fan4f1a5812016-03-11 16:47:50 +0800434 /* Send high and low on the SCL line */
Lukasz Majewskibc9aad62019-04-04 12:35:34 +0200435 for (i = 0; i < idle_sclks; i++) {
Peng Fan4f1a5812016-03-11 16:47:50 +0800436 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_OUT);
437 dm_gpio_set_value(scl_gpio, 0);
438 udelay(50);
439 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
440 udelay(50);
441 }
442 start_time = get_timer(0);
443 for (;;) {
444 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
445 dm_gpio_set_dir_flags(sda_gpio, GPIOD_IS_IN);
446 scl = dm_gpio_get_value(scl_gpio);
447 sda = dm_gpio_get_value(sda_gpio);
448 if ((sda & scl) == 1)
449 break;
Stefan Roese80877fa2022-09-02 14:10:46 +0200450 schedule();
Peng Fan4f1a5812016-03-11 16:47:50 +0800451 elapsed = get_timer(start_time);
452 if (elapsed > (CONFIG_SYS_HZ / 5)) { /* .2 seconds */
453 ret = -EBUSY;
454 printf("%s: failed to clear bus, sda=%d scl=%d\n", __func__, sda, scl);
455 break;
456 }
457 }
458
459exit:
460 pinctrl_select_state(bus, "default");
461 return ret;
462}
Peng Fan8262cb12015-05-15 07:29:12 +0800463#endif
Biwen Li70a81582020-07-02 11:13:00 +0800464/*
465 * Early init I2C for prepare read the clk through I2C.
466 */
467void i2c_early_init_f(void)
468{
469 ulong base = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].base;
470 bool quirk = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].driver_data
471 & I2C_QUIRK_FLAG ? true : false;
472 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
473
474 /* Set I2C divider value */
475 writeb(I2C_IFDR_DIV_CONSERVATIVE, base + (IFDR << reg_shift));
476 /* Reset module */
477 writeb(I2CR_IDIS, base + (I2CR << reg_shift));
478 writeb(0, base + (I2SR << reg_shift));
479 /* Enable I2C */
480 writeb(I2CR_IEN, base + (I2CR << reg_shift));
481}
Troy Kiskya23ab222012-07-19 08:18:19 +0000482
Peng Fan8262cb12015-05-15 07:29:12 +0800483static int i2c_init_transfer(struct mxc_i2c_bus *i2c_bus, u8 chip,
484 u32 addr, int alen)
Troy Kiskyeca037a2012-07-19 08:18:16 +0000485{
486 int retry;
487 int ret;
Peng Fan8262cb12015-05-15 07:29:12 +0800488 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
489 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
Heiko Schocher24ebcf22015-05-18 10:58:12 +0200490
491 if (!i2c_bus->base)
Simon Glassf44b4bf2017-09-17 16:54:53 -0600492 return -EINVAL;
Heiko Schocher24ebcf22015-05-18 10:58:12 +0200493
Troy Kiskyeca037a2012-07-19 08:18:16 +0000494 for (retry = 0; retry < 3; retry++) {
Peng Fan8262cb12015-05-15 07:29:12 +0800495 ret = i2c_init_transfer_(i2c_bus, chip, addr, alen);
Troy Kiskyeca037a2012-07-19 08:18:16 +0000496 if (ret >= 0)
497 return 0;
Peng Fan8262cb12015-05-15 07:29:12 +0800498 i2c_imx_stop(i2c_bus);
Simon Glassf44b4bf2017-09-17 16:54:53 -0600499 if (ret == -EREMOTEIO)
Troy Kiskyeca037a2012-07-19 08:18:16 +0000500 return ret;
501
502 printf("%s: failed for chip 0x%x retry=%d\n", __func__, chip,
503 retry);
504 if (ret != -ERESTART)
Alison Wangcf508002013-06-17 15:30:39 +0800505 /* Disable controller */
Peng Fan8262cb12015-05-15 07:29:12 +0800506 writeb(I2CR_IDIS, i2c_bus->base + (I2CR << reg_shift));
Troy Kiskyeca037a2012-07-19 08:18:16 +0000507 udelay(100);
Peng Fan8262cb12015-05-15 07:29:12 +0800508 if (i2c_idle_bus(i2c_bus) < 0)
Troy Kiskya23ab222012-07-19 08:18:19 +0000509 break;
Troy Kiskyeca037a2012-07-19 08:18:16 +0000510 }
Peng Fan8262cb12015-05-15 07:29:12 +0800511 printf("%s: give up i2c_regs=0x%lx\n", __func__, i2c_bus->base);
Marek Vasut94cb8422011-09-22 09:22:12 +0000512 return ret;
Sascha Hauer15ea70f2008-03-26 20:40:49 +0100513}
514
Peng Fan8262cb12015-05-15 07:29:12 +0800515
516static int i2c_write_data(struct mxc_i2c_bus *i2c_bus, u8 chip, const u8 *buf,
517 int len)
518{
519 int i, ret = 0;
520
521 debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip, len);
522 debug("write_data: ");
523 /* use rc for counter */
524 for (i = 0; i < len; ++i)
525 debug(" 0x%02x", buf[i]);
526 debug("\n");
527
528 for (i = 0; i < len; i++) {
529 ret = tx_byte(i2c_bus, buf[i]);
530 if (ret < 0) {
531 debug("i2c_write_data(): rc=%d\n", ret);
532 break;
533 }
534 }
535
536 return ret;
537}
538
Trent Piepho9c896a92019-04-30 16:08:19 +0000539/* Will generate a STOP after the last byte if "last" is true, i.e. this is the
540 * final message of a transaction. If not, it switches the bus back to TX mode
541 * and does not send a STOP, leaving the bus in a state where a repeated start
542 * and address can be sent for another message.
543 */
Peng Fan8262cb12015-05-15 07:29:12 +0800544static int i2c_read_data(struct mxc_i2c_bus *i2c_bus, uchar chip, uchar *buf,
Trent Piepho9c896a92019-04-30 16:08:19 +0000545 int len, bool last)
Sascha Hauer15ea70f2008-03-26 20:40:49 +0100546{
Sascha Hauer15ea70f2008-03-26 20:40:49 +0100547 int ret;
Marek Vasut94cb8422011-09-22 09:22:12 +0000548 unsigned int temp;
549 int i;
Peng Fan8262cb12015-05-15 07:29:12 +0800550 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
551 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
552 ulong base = i2c_bus->base;
Sascha Hauer15ea70f2008-03-26 20:40:49 +0100553
Peng Fan8262cb12015-05-15 07:29:12 +0800554 debug("i2c_read_data: chip=0x%x, len=0x%x\n", chip, len);
Sascha Hauer15ea70f2008-03-26 20:40:49 +0100555
Marek Vasut94cb8422011-09-22 09:22:12 +0000556 /* setup bus to read data */
Peng Fan8262cb12015-05-15 07:29:12 +0800557 temp = readb(base + (I2CR << reg_shift));
Marek Vasut94cb8422011-09-22 09:22:12 +0000558 temp &= ~(I2CR_MTX | I2CR_TX_NO_AK);
559 if (len == 1)
560 temp |= I2CR_TX_NO_AK;
Peng Fan8262cb12015-05-15 07:29:12 +0800561 writeb(temp, base + (I2CR << reg_shift));
562 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
563 /* dummy read to clear ICF */
564 readb(base + (I2DR << reg_shift));
Sascha Hauer15ea70f2008-03-26 20:40:49 +0100565
Marek Vasut94cb8422011-09-22 09:22:12 +0000566 /* read data */
567 for (i = 0; i < len; i++) {
Peng Fan8262cb12015-05-15 07:29:12 +0800568 ret = wait_for_sr_state(i2c_bus, ST_IIF);
Troy Kiskyf024a3b2012-07-19 08:18:09 +0000569 if (ret < 0) {
Peng Fan8262cb12015-05-15 07:29:12 +0800570 debug("i2c_read_data(): ret=%d\n", ret);
571 i2c_imx_stop(i2c_bus);
Marek Vasut94cb8422011-09-22 09:22:12 +0000572 return ret;
Troy Kisky0ce898d2012-07-19 08:18:07 +0000573 }
Sascha Hauer15ea70f2008-03-26 20:40:49 +0100574
Marek Vasut94cb8422011-09-22 09:22:12 +0000575 if (i == (len - 1)) {
Trent Piepho9c896a92019-04-30 16:08:19 +0000576 /* Final byte has already been received by master! When
577 * we read it from I2DR, the master will start another
578 * cycle. We must program it first to send a STOP or
579 * switch to TX to avoid this.
580 */
581 if (last) {
582 i2c_imx_stop(i2c_bus);
583 } else {
584 /* Final read, no stop, switch back to tx */
585 temp = readb(base + (I2CR << reg_shift));
586 temp |= I2CR_MTX | I2CR_TX_NO_AK;
587 writeb(temp, base + (I2CR << reg_shift));
588 }
Marek Vasut94cb8422011-09-22 09:22:12 +0000589 } else if (i == (len - 2)) {
Trent Piepho9c896a92019-04-30 16:08:19 +0000590 /* Master has already recevied penultimate byte. When
591 * we read it from I2DR, master will start RX of final
592 * byte. We must set TX_NO_AK now so it does not ACK
593 * that final byte.
594 */
Peng Fan8262cb12015-05-15 07:29:12 +0800595 temp = readb(base + (I2CR << reg_shift));
Marek Vasut94cb8422011-09-22 09:22:12 +0000596 temp |= I2CR_TX_NO_AK;
Peng Fan8262cb12015-05-15 07:29:12 +0800597 writeb(temp, base + (I2CR << reg_shift));
Marek Vasut94cb8422011-09-22 09:22:12 +0000598 }
Trent Piepho9c896a92019-04-30 16:08:19 +0000599
Peng Fan8262cb12015-05-15 07:29:12 +0800600 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
601 buf[i] = readb(base + (I2DR << reg_shift));
Marek Vasut94cb8422011-09-22 09:22:12 +0000602 }
Peng Fan8262cb12015-05-15 07:29:12 +0800603
604 /* reuse ret for counter*/
605 for (ret = 0; ret < len; ++ret)
606 debug(" 0x%02x", buf[ret]);
607 debug("\n");
608
Trent Piepho9c896a92019-04-30 16:08:19 +0000609 /* It is not clear to me that this is necessary */
610 if (last)
611 i2c_imx_stop(i2c_bus);
Troy Kiskyf024a3b2012-07-19 08:18:09 +0000612 return 0;
Sascha Hauer15ea70f2008-03-26 20:40:49 +0100613}
614
Chuanhua Hand24d2d92019-07-10 21:00:22 +0800615int __enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
616{
617 return 1;
618}
619
620int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
621 __attribute__((weak, alias("__enable_i2c_clk")));
622
Igor Opaniukf7c91762021-02-09 13:52:45 +0200623#if !CONFIG_IS_ENABLED(DM_I2C)
Marek Vasut94cb8422011-09-22 09:22:12 +0000624/*
Peng Fan8262cb12015-05-15 07:29:12 +0800625 * Read data from I2C device
Trent Piepho15410ba2019-04-30 16:08:18 +0000626 *
627 * The transactions use the syntax defined in the Linux kernel I2C docs.
628 *
629 * If alen is > 0, then this function will send a transaction of the form:
630 * S Chip Wr [A] Addr [A] S Chip Rd [A] [data] A ... NA P
631 * This is a normal I2C register read: writing the register address, then doing
632 * a repeated start and reading the data.
633 *
634 * If alen == 0, then we get this transaction:
635 * S Chip Wr [A] S Chip Rd [A] [data] A ... NA P
636 * This is somewhat unusual, though valid, transaction. It addresses the chip
637 * in write mode, but doesn't actually write any register address or data, then
638 * does a repeated start and reads data.
639 *
640 * If alen < 0, then we get this transaction:
641 * S Chip Rd [A] [data] A ... NA P
642 * The chip is addressed in read mode and then data is read. No register
643 * address is written first. This is perfectly valid on most devices and
644 * required on some (usually those that don't act like an array of registers).
Marek Vasut94cb8422011-09-22 09:22:12 +0000645 */
Peng Fan8262cb12015-05-15 07:29:12 +0800646static int bus_i2c_read(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
647 int alen, u8 *buf, int len)
Sascha Hauer15ea70f2008-03-26 20:40:49 +0100648{
Peng Fan8262cb12015-05-15 07:29:12 +0800649 int ret = 0;
650 u32 temp;
651 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
652 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
653 ulong base = i2c_bus->base;
Sascha Hauer15ea70f2008-03-26 20:40:49 +0100654
Peng Fan8262cb12015-05-15 07:29:12 +0800655 ret = i2c_init_transfer(i2c_bus, chip, addr, alen);
Troy Kisky752ac8f2012-07-19 08:18:04 +0000656 if (ret < 0)
Marek Vasut94cb8422011-09-22 09:22:12 +0000657 return ret;
Sascha Hauer15ea70f2008-03-26 20:40:49 +0100658
Nandor Hana51f9da2017-11-08 15:35:09 +0000659 if (alen >= 0) {
660 temp = readb(base + (I2CR << reg_shift));
661 temp |= I2CR_RSTA;
662 writeb(temp, base + (I2CR << reg_shift));
663 }
Peng Fan8262cb12015-05-15 07:29:12 +0800664
665 ret = tx_byte(i2c_bus, (chip << 1) | 1);
666 if (ret < 0) {
667 i2c_imx_stop(i2c_bus);
668 return ret;
Marek Vasut94cb8422011-09-22 09:22:12 +0000669 }
Peng Fan8262cb12015-05-15 07:29:12 +0800670
Trent Piepho9c896a92019-04-30 16:08:19 +0000671 ret = i2c_read_data(i2c_bus, chip, buf, len, true);
Peng Fan8262cb12015-05-15 07:29:12 +0800672
673 i2c_imx_stop(i2c_bus);
674 return ret;
675}
676
677/*
678 * Write data to I2C device
Trent Piepho15410ba2019-04-30 16:08:18 +0000679 *
680 * If alen > 0, we get this transaction:
681 * S Chip Wr [A] addr [A] data [A] ... [A] P
682 * An ordinary write register command.
683 *
684 * If alen == 0, then we get this:
685 * S Chip Wr [A] data [A] ... [A] P
686 * This is a simple I2C write.
687 *
688 * If alen < 0, then we get this:
689 * S data [A] ... [A] P
690 * This is most likely NOT something that should be used. It doesn't send the
691 * chip address first, so in effect, the first byte of data will be used as the
692 * address.
Peng Fan8262cb12015-05-15 07:29:12 +0800693 */
694static int bus_i2c_write(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
695 int alen, const u8 *buf, int len)
696{
697 int ret = 0;
698
699 ret = i2c_init_transfer(i2c_bus, chip, addr, alen);
700 if (ret < 0)
701 return ret;
702
703 ret = i2c_write_data(i2c_bus, chip, buf, len);
704
705 i2c_imx_stop(i2c_bus);
706
Marek Vasut94cb8422011-09-22 09:22:12 +0000707 return ret;
708}
Troy Kisky321a42b2012-07-19 08:18:08 +0000709
Peng Fan8262cb12015-05-15 07:29:12 +0800710struct mxc_i2c_bus *i2c_get_base(struct i2c_adapter *adap)
Troy Kiskya23ab222012-07-19 08:18:19 +0000711{
Peng Fan8262cb12015-05-15 07:29:12 +0800712 return &mxc_i2c_buses[adap->hwadapnr];
Troy Kiskya23ab222012-07-19 08:18:19 +0000713}
Troy Kiskyb6f98262012-07-19 08:18:20 +0000714
trema49f40a2013-09-21 18:13:35 +0200715static int mxc_i2c_read(struct i2c_adapter *adap, uint8_t chip,
716 uint addr, int alen, uint8_t *buffer,
717 int len)
Troy Kiskyae447602012-07-19 08:18:18 +0000718{
trema49f40a2013-09-21 18:13:35 +0200719 return bus_i2c_read(i2c_get_base(adap), chip, addr, alen, buffer, len);
Troy Kiskyae447602012-07-19 08:18:18 +0000720}
721
trema49f40a2013-09-21 18:13:35 +0200722static int mxc_i2c_write(struct i2c_adapter *adap, uint8_t chip,
723 uint addr, int alen, uint8_t *buffer,
724 int len)
Troy Kiskyae447602012-07-19 08:18:18 +0000725{
trema49f40a2013-09-21 18:13:35 +0200726 return bus_i2c_write(i2c_get_base(adap), chip, addr, alen, buffer, len);
Troy Kiskyae447602012-07-19 08:18:18 +0000727}
728
729/*
Troy Kisky321a42b2012-07-19 08:18:08 +0000730 * Test if a chip at a given address responds (probe the chip)
731 */
trema49f40a2013-09-21 18:13:35 +0200732static int mxc_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
Troy Kisky321a42b2012-07-19 08:18:08 +0000733{
trema49f40a2013-09-21 18:13:35 +0200734 return bus_i2c_write(i2c_get_base(adap), chip, 0, 0, NULL, 0);
Troy Kiskyae447602012-07-19 08:18:18 +0000735}
Peng Fan8262cb12015-05-15 07:29:12 +0800736
Peng Fan8262cb12015-05-15 07:29:12 +0800737void bus_i2c_init(int index, int speed, int unused,
738 int (*idle_bus_fn)(void *p), void *idle_bus_data)
Troy Kiskyae447602012-07-19 08:18:18 +0000739{
Peng Fan8262cb12015-05-15 07:29:12 +0800740 int ret;
741
742 if (index >= ARRAY_SIZE(mxc_i2c_buses)) {
743 debug("Error i2c index\n");
Troy Kiskyae447602012-07-19 08:18:18 +0000744 return;
Peng Fan8262cb12015-05-15 07:29:12 +0800745 }
746
Simon Glass34d37a62023-02-05 15:40:11 -0700747 if (IS_ENABLED(CONFIG_IMX_MODULE_FUSE)) {
Peng Fan23d4ee32020-05-01 22:08:35 +0800748 if (i2c_fused((ulong)mxc_i2c_buses[index].base)) {
749 printf("SoC fuse indicates I2C@0x%lx is unavailable.\n",
750 (ulong)mxc_i2c_buses[index].base);
751 return;
752 }
753 }
754
Gong Qianyufd999082015-12-18 17:38:01 +0800755 /*
756 * Warning: Be careful to allow the assignment to a static
757 * variable here. This function could be called while U-Boot is
758 * still running in flash memory. So such assignment is equal
759 * to write data to flash without erasing.
760 */
761 if (idle_bus_fn)
762 mxc_i2c_buses[index].idle_bus_fn = idle_bus_fn;
763 if (idle_bus_data)
764 mxc_i2c_buses[index].idle_bus_data = idle_bus_data;
Peng Fan8262cb12015-05-15 07:29:12 +0800765
766 ret = enable_i2c_clk(1, index);
767 if (ret < 0) {
768 debug("I2C-%d clk fail to enable.\n", index);
769 return;
Troy Kiskyae447602012-07-19 08:18:18 +0000770 }
Peng Fan8262cb12015-05-15 07:29:12 +0800771
772 bus_i2c_set_bus_speed(&mxc_i2c_buses[index], speed);
Troy Kiskyae447602012-07-19 08:18:18 +0000773}
774
Yuan Yaod40c8852016-06-08 18:24:51 +0800775/*
Troy Kiskyae447602012-07-19 08:18:18 +0000776 * Init I2C Bus
777 */
trema49f40a2013-09-21 18:13:35 +0200778static void mxc_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
Troy Kiskyae447602012-07-19 08:18:18 +0000779{
Peng Fan8262cb12015-05-15 07:29:12 +0800780 bus_i2c_init(adap->hwadapnr, speed, slaveaddr, NULL, NULL);
Troy Kiskyae447602012-07-19 08:18:18 +0000781}
782
783/*
784 * Set I2C Speed
785 */
Peng Fan8262cb12015-05-15 07:29:12 +0800786static u32 mxc_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
Troy Kiskyae447602012-07-19 08:18:18 +0000787{
trema49f40a2013-09-21 18:13:35 +0200788 return bus_i2c_set_bus_speed(i2c_get_base(adap), speed);
Troy Kiskyae447602012-07-19 08:18:18 +0000789}
790
791/*
trema49f40a2013-09-21 18:13:35 +0200792 * Register mxc i2c adapters
Troy Kiskyae447602012-07-19 08:18:18 +0000793 */
Albert ARIBAUD \\(3ADEV\\)eb943872015-09-21 22:43:38 +0200794#ifdef CONFIG_SYS_I2C_MXC_I2C1
trema49f40a2013-09-21 18:13:35 +0200795U_BOOT_I2C_ADAP_COMPLETE(mxc0, mxc_i2c_init, mxc_i2c_probe,
796 mxc_i2c_read, mxc_i2c_write,
797 mxc_i2c_set_bus_speed,
798 CONFIG_SYS_MXC_I2C1_SPEED,
799 CONFIG_SYS_MXC_I2C1_SLAVE, 0)
Albert ARIBAUD \\(3ADEV\\)eb943872015-09-21 22:43:38 +0200800#endif
801
802#ifdef CONFIG_SYS_I2C_MXC_I2C2
trema49f40a2013-09-21 18:13:35 +0200803U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe,
804 mxc_i2c_read, mxc_i2c_write,
805 mxc_i2c_set_bus_speed,
806 CONFIG_SYS_MXC_I2C2_SPEED,
807 CONFIG_SYS_MXC_I2C2_SLAVE, 1)
Albert ARIBAUD \\(3ADEV\\)eb943872015-09-21 22:43:38 +0200808#endif
809
York Sunf1a52162015-03-20 10:20:40 -0700810#ifdef CONFIG_SYS_I2C_MXC_I2C3
trema49f40a2013-09-21 18:13:35 +0200811U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe,
812 mxc_i2c_read, mxc_i2c_write,
813 mxc_i2c_set_bus_speed,
814 CONFIG_SYS_MXC_I2C3_SPEED,
815 CONFIG_SYS_MXC_I2C3_SLAVE, 2)
816#endif
Peng Fan8262cb12015-05-15 07:29:12 +0800817
York Sunf1a52162015-03-20 10:20:40 -0700818#ifdef CONFIG_SYS_I2C_MXC_I2C4
819U_BOOT_I2C_ADAP_COMPLETE(mxc3, mxc_i2c_init, mxc_i2c_probe,
820 mxc_i2c_read, mxc_i2c_write,
821 mxc_i2c_set_bus_speed,
822 CONFIG_SYS_MXC_I2C4_SPEED,
823 CONFIG_SYS_MXC_I2C4_SLAVE, 3)
824#endif
Peng Fan8262cb12015-05-15 07:29:12 +0800825
Sriram Dasha64aa192018-02-06 11:26:31 +0530826#ifdef CONFIG_SYS_I2C_MXC_I2C5
827U_BOOT_I2C_ADAP_COMPLETE(mxc4, mxc_i2c_init, mxc_i2c_probe,
828 mxc_i2c_read, mxc_i2c_write,
829 mxc_i2c_set_bus_speed,
830 CONFIG_SYS_MXC_I2C5_SPEED,
831 CONFIG_SYS_MXC_I2C5_SLAVE, 4)
832#endif
833
834#ifdef CONFIG_SYS_I2C_MXC_I2C6
835U_BOOT_I2C_ADAP_COMPLETE(mxc5, mxc_i2c_init, mxc_i2c_probe,
836 mxc_i2c_read, mxc_i2c_write,
837 mxc_i2c_set_bus_speed,
838 CONFIG_SYS_MXC_I2C6_SPEED,
839 CONFIG_SYS_MXC_I2C6_SLAVE, 5)
840#endif
841
842#ifdef CONFIG_SYS_I2C_MXC_I2C7
843U_BOOT_I2C_ADAP_COMPLETE(mxc6, mxc_i2c_init, mxc_i2c_probe,
844 mxc_i2c_read, mxc_i2c_write,
845 mxc_i2c_set_bus_speed,
846 CONFIG_SYS_MXC_I2C7_SPEED,
847 CONFIG_SYS_MXC_I2C7_SLAVE, 6)
848#endif
849
850#ifdef CONFIG_SYS_I2C_MXC_I2C8
851U_BOOT_I2C_ADAP_COMPLETE(mxc7, mxc_i2c_init, mxc_i2c_probe,
852 mxc_i2c_read, mxc_i2c_write,
853 mxc_i2c_set_bus_speed,
854 CONFIG_SYS_MXC_I2C8_SPEED,
855 CONFIG_SYS_MXC_I2C8_SLAVE, 7)
856#endif
857
Peng Fan8262cb12015-05-15 07:29:12 +0800858#else
859
860static int mxc_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
861{
862 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
863
864 return bus_i2c_set_bus_speed(i2c_bus, speed);
865}
866
867static int mxc_i2c_probe(struct udevice *bus)
868{
869 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
Peng Fan4f1a5812016-03-11 16:47:50 +0800870 const void *fdt = gd->fdt_blob;
Simon Glassdd79d6e2017-01-17 16:52:55 -0700871 int node = dev_of_offset(bus);
Peng Fan8262cb12015-05-15 07:29:12 +0800872 fdt_addr_t addr;
Peng Fan4f1a5812016-03-11 16:47:50 +0800873 int ret, ret2;
Peng Fan8262cb12015-05-15 07:29:12 +0800874
875 i2c_bus->driver_data = dev_get_driver_data(bus);
876
Masahiro Yamadaa89b4de2020-07-17 14:36:48 +0900877 addr = dev_read_addr(bus);
Peng Fan8262cb12015-05-15 07:29:12 +0800878 if (addr == FDT_ADDR_T_NONE)
Simon Glassf44b4bf2017-09-17 16:54:53 -0600879 return -EINVAL;
Peng Fan8262cb12015-05-15 07:29:12 +0800880
Simon Glass34d37a62023-02-05 15:40:11 -0700881 if (IS_ENABLED(CONFIG_IMX_MODULE_FUSE)) {
Peng Fan23d4ee32020-05-01 22:08:35 +0800882 if (i2c_fused((ulong)addr)) {
883 printf("SoC fuse indicates I2C@0x%lx is unavailable.\n",
884 (ulong)addr);
885 return -ENODEV;
886 }
887 }
888
Peng Fan8262cb12015-05-15 07:29:12 +0800889 i2c_bus->base = addr;
Simon Glass75e534b2020-12-16 21:20:07 -0700890 i2c_bus->index = dev_seq(bus);
Peng Fan4f1a5812016-03-11 16:47:50 +0800891 i2c_bus->bus = bus;
Peng Fan8262cb12015-05-15 07:29:12 +0800892
893 /* Enable clk */
Peng Fan87ea5622019-08-08 01:43:30 +0000894#if CONFIG_IS_ENABLED(CLK)
895 ret = clk_get_by_index(bus, 0, &i2c_bus->per_clk);
896 if (ret) {
897 printf("Failed to get i2c clk\n");
898 return ret;
899 }
900 ret = clk_enable(&i2c_bus->per_clk);
901 if (ret) {
902 printf("Failed to enable i2c clk\n");
903 return ret;
904 }
905#else
Simon Glass75e534b2020-12-16 21:20:07 -0700906 ret = enable_i2c_clk(1, dev_seq(bus));
Peng Fan8262cb12015-05-15 07:29:12 +0800907 if (ret < 0)
908 return ret;
Peng Fan87ea5622019-08-08 01:43:30 +0000909#endif
Peng Fan8262cb12015-05-15 07:29:12 +0800910
Peng Fan4f1a5812016-03-11 16:47:50 +0800911 /*
912 * See Documentation/devicetree/bindings/i2c/i2c-imx.txt
913 * Use gpio to force bus idle when necessary.
914 */
Simon Glassb0ea7402016-10-02 17:59:28 -0600915 ret = fdt_stringlist_search(fdt, node, "pinctrl-names", "gpio");
Peng Fan4f1a5812016-03-11 16:47:50 +0800916 if (ret < 0) {
Sean Andersonfbba69f2020-09-15 10:44:39 -0400917 debug("i2c bus %d at 0x%2lx, no gpio pinctrl state.\n",
Simon Glass75e534b2020-12-16 21:20:07 -0700918 dev_seq(bus), i2c_bus->base);
Peng Fan4f1a5812016-03-11 16:47:50 +0800919 } else {
Simon Glass1d9af1f2017-05-30 21:47:09 -0600920 ret = gpio_request_by_name_nodev(offset_to_ofnode(node),
921 "scl-gpios", 0, &i2c_bus->scl_gpio,
922 GPIOD_IS_OUT);
923 ret2 = gpio_request_by_name_nodev(offset_to_ofnode(node),
924 "sda-gpios", 0, &i2c_bus->sda_gpio,
925 GPIOD_IS_OUT);
Peng Fan08eaa832017-12-29 15:06:08 +0800926 if (!dm_gpio_is_valid(&i2c_bus->sda_gpio) ||
927 !dm_gpio_is_valid(&i2c_bus->scl_gpio) ||
928 ret || ret2) {
Sean Andersonfbba69f2020-09-15 10:44:39 -0400929 dev_err(bus,
Marc Ferland323069e2020-12-21 09:50:16 -0500930 "i2c bus %d at 0x%2lx, fail to request scl/sda gpio\n",
Simon Glass75e534b2020-12-16 21:20:07 -0700931 dev_seq(bus), i2c_bus->base);
Simon Glassf44b4bf2017-09-17 16:54:53 -0600932 return -EINVAL;
Peng Fan4f1a5812016-03-11 16:47:50 +0800933 }
934 }
935
Peng Fan8262cb12015-05-15 07:29:12 +0800936 /*
937 * Pinmux settings are in board file now, until pinmux is supported,
938 * we can set pinmux here in probe function.
939 */
940
941 debug("i2c : controller bus %d at %lu , speed %d: ",
Simon Glass75e534b2020-12-16 21:20:07 -0700942 dev_seq(bus), i2c_bus->base,
Peng Fan8262cb12015-05-15 07:29:12 +0800943 i2c_bus->speed);
944
945 return 0;
946}
947
Trent Piepho15410ba2019-04-30 16:08:18 +0000948/* Sends: S Addr Wr [A|NA] P */
Peng Fan8262cb12015-05-15 07:29:12 +0800949static int mxc_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
950 u32 chip_flags)
951{
952 int ret;
953 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
954
955 ret = i2c_init_transfer(i2c_bus, chip_addr, 0, 0);
956 if (ret < 0) {
957 debug("%s failed, ret = %d\n", __func__, ret);
958 return ret;
959 }
960
961 i2c_imx_stop(i2c_bus);
962
963 return 0;
964}
965
966static int mxc_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
967{
968 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
969 int ret = 0;
970 ulong base = i2c_bus->base;
971 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
972 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
Trent Piepho9c896a92019-04-30 16:08:19 +0000973 int read_mode;
Peng Fan8262cb12015-05-15 07:29:12 +0800974
Trent Piepho9c896a92019-04-30 16:08:19 +0000975 /* Here address len is set to -1 to not send any address at first.
976 * Otherwise i2c_init_transfer will send the chip address with write
977 * mode set. This is wrong if the 1st message is read.
Peng Fan8262cb12015-05-15 07:29:12 +0800978 */
Trent Piepho9c896a92019-04-30 16:08:19 +0000979 ret = i2c_init_transfer(i2c_bus, msg->addr, 0, -1);
Peng Fan8262cb12015-05-15 07:29:12 +0800980 if (ret < 0) {
981 debug("i2c_init_transfer error: %d\n", ret);
982 return ret;
983 }
984
Trent Piepho9c896a92019-04-30 16:08:19 +0000985 read_mode = -1; /* So it's always different on the first message */
Peng Fan8262cb12015-05-15 07:29:12 +0800986 for (; nmsgs > 0; nmsgs--, msg++) {
Trent Piepho9c896a92019-04-30 16:08:19 +0000987 const int msg_is_read = !!(msg->flags & I2C_M_RD);
988
989 debug("i2c_xfer: chip=0x%x, len=0x%x, dir=%c\n", msg->addr,
990 msg->len, msg_is_read ? 'R' : 'W');
991
992 if (msg_is_read != read_mode) {
993 /* Send repeated start if not 1st message */
994 if (read_mode != -1) {
995 debug("i2c_xfer: [RSTART]\n");
Peng Fan8262cb12015-05-15 07:29:12 +0800996 ret = readb(base + (I2CR << reg_shift));
997 ret |= I2CR_RSTA;
998 writeb(ret, base + (I2CR << reg_shift));
Peng Fan8262cb12015-05-15 07:29:12 +0800999 }
Trent Piepho9c896a92019-04-30 16:08:19 +00001000 debug("i2c_xfer: [ADDR %02x | %c]\n", msg->addr,
1001 msg_is_read ? 'R' : 'W');
1002 ret = tx_byte(i2c_bus, (msg->addr << 1) | msg_is_read);
1003 if (ret < 0) {
1004 debug("i2c_xfer: [STOP]\n");
1005 i2c_imx_stop(i2c_bus);
1006 break;
1007 }
1008 read_mode = msg_is_read;
Peng Fan8262cb12015-05-15 07:29:12 +08001009 }
Trent Piepho9c896a92019-04-30 16:08:19 +00001010
1011 if (msg->flags & I2C_M_RD)
1012 ret = i2c_read_data(i2c_bus, msg->addr, msg->buf,
1013 msg->len, nmsgs == 1 ||
1014 (msg->flags & I2C_M_STOP));
1015 else
1016 ret = i2c_write_data(i2c_bus, msg->addr, msg->buf,
1017 msg->len);
1018
1019 if (ret < 0)
1020 break;
Peng Fan8262cb12015-05-15 07:29:12 +08001021 }
1022
1023 if (ret)
1024 debug("i2c_write: error sending\n");
1025
1026 i2c_imx_stop(i2c_bus);
1027
1028 return ret;
1029}
1030
1031static const struct dm_i2c_ops mxc_i2c_ops = {
1032 .xfer = mxc_i2c_xfer,
1033 .probe_chip = mxc_i2c_probe_chip,
1034 .set_bus_speed = mxc_i2c_set_bus_speed,
1035};
1036
1037static const struct udevice_id mxc_i2c_ids[] = {
1038 { .compatible = "fsl,imx21-i2c", },
1039 { .compatible = "fsl,vf610-i2c", .data = I2C_QUIRK_FLAG, },
1040 {}
1041};
1042
1043U_BOOT_DRIVER(i2c_mxc) = {
1044 .name = "i2c_mxc",
1045 .id = UCLASS_I2C,
1046 .of_match = mxc_i2c_ids,
1047 .probe = mxc_i2c_probe,
Simon Glass8a2b47f2020-12-03 16:55:17 -07001048 .priv_auto = sizeof(struct mxc_i2c_bus),
Peng Fan8262cb12015-05-15 07:29:12 +08001049 .ops = &mxc_i2c_ops,
Biwen Li41a5abc2019-12-31 15:33:39 +08001050 .flags = DM_FLAG_PRE_RELOC,
Peng Fan8262cb12015-05-15 07:29:12 +08001051};
1052#endif