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git01.mediatek.com / filogic / uboot / 2f6462ad01635d02f276380ca9f749f76a0c96f9 / . / drivers / pinctrl / mscc / pinctrl-servalt.c
blob: 592b7c547b7c7028309e5ba4cc6bd2ba8116b251 [file] [log] [blame]
Horatiu Vultur2f6462a2019-01-17 15:33:26 +0100[diff] [blame^]1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Microsemi SoCs pinctrl driver
4 *
5 * Author: <horatiu.vultur@microchip.com>
6 * Copyright (c) 2019 Microsemi Corporation
7 */
8
9#include <common.h>
10#include <config.h>
11#include <dm.h>
12#include <dm/device-internal.h>
13#include <dm/lists.h>
14#include <dm/pinctrl.h>
15#include <dm/root.h>
16#include <errno.h>
17#include <fdtdec.h>
18#include <linux/io.h>
19#include <asm/gpio.h>
20#include <asm/system.h>
21#include "mscc-common.h"
22
23enum {
24 FUNC_NONE,
25 FUNC_GPIO,
26 FUNC_IRQ0_IN,
27 FUNC_IRQ0_OUT,
28 FUNC_IRQ1_IN,
29 FUNC_IRQ1_OUT,
30 FUNC_MIIM1,
31 FUNC_MIIM2,
32 FUNC_PCI_WAKE,
33 FUNC_PTP0,
34 FUNC_PTP1,
35 FUNC_PTP2,
36 FUNC_PTP3,
37 FUNC_PWM,
38 FUNC_RCVRD_CLK0,
39 FUNC_RCVRD_CLK1,
40 FUNC_RCVRD_CLK2,
41 FUNC_RCVRD_CLK3,
42 FUNC_REF_CLK0,
43 FUNC_REF_CLK1,
44 FUNC_REF_CLK2,
45 FUNC_REF_CLK3,
46 FUNC_SFP0,
47 FUNC_SFP1,
48 FUNC_SFP2,
49 FUNC_SFP3,
50 FUNC_SFP4,
51 FUNC_SFP5,
52 FUNC_SFP6,
53 FUNC_SFP7,
54 FUNC_SFP8,
55 FUNC_SFP9,
56 FUNC_SFP10,
57 FUNC_SFP11,
58 FUNC_SFP12,
59 FUNC_SFP13,
60 FUNC_SFP14,
61 FUNC_SFP15,
62 FUNC_SIO,
63 FUNC_SPI,
64 FUNC_TACHO,
65 FUNC_TWI,
66 FUNC_TWI2,
67 FUNC_TWI_SCL_M,
68 FUNC_UART,
69 FUNC_UART2,
70 FUNC_MAX
71};
72
73static char * const servalt_function_names[] = {
74 [FUNC_NONE] = "none",
75 [FUNC_GPIO] = "gpio",
76 [FUNC_IRQ0_IN] = "irq0_in",
77 [FUNC_IRQ0_OUT] = "irq0_out",
78 [FUNC_IRQ1_IN] = "irq1_in",
79 [FUNC_IRQ1_OUT] = "irq1_out",
80 [FUNC_MIIM1] = "miim1",
81 [FUNC_MIIM2] = "miim2",
82 [FUNC_PCI_WAKE] = "pci_wake",
83 [FUNC_PTP0] = "ptp0",
84 [FUNC_PTP1] = "ptp1",
85 [FUNC_PTP2] = "ptp2",
86 [FUNC_PTP3] = "ptp3",
87 [FUNC_PWM] = "pwm",
88 [FUNC_RCVRD_CLK0] = "rcvrd_clk0",
89 [FUNC_RCVRD_CLK1] = "rcvrd_clk1",
90 [FUNC_RCVRD_CLK2] = "rcvrd_clk2",
91 [FUNC_RCVRD_CLK3] = "rcvrd_clk3",
92 [FUNC_REF_CLK0] = "ref_clk0",
93 [FUNC_REF_CLK1] = "ref_clk1",
94 [FUNC_REF_CLK2] = "ref_clk2",
95 [FUNC_REF_CLK3] = "ref_clk3",
96 [FUNC_SFP0] = "sfp0",
97 [FUNC_SFP1] = "sfp1",
98 [FUNC_SFP2] = "sfp2",
99 [FUNC_SFP3] = "sfp3",
100 [FUNC_SFP4] = "sfp4",
101 [FUNC_SFP5] = "sfp5",
102 [FUNC_SFP6] = "sfp6",
103 [FUNC_SFP7] = "sfp7",
104 [FUNC_SFP8] = "sfp8",
105 [FUNC_SFP9] = "sfp9",
106 [FUNC_SFP10] = "sfp10",
107 [FUNC_SFP11] = "sfp11",
108 [FUNC_SFP12] = "sfp12",
109 [FUNC_SFP13] = "sfp13",
110 [FUNC_SFP14] = "sfp14",
111 [FUNC_SFP15] = "sfp15",
112 [FUNC_SIO] = "sio",
113 [FUNC_SPI] = "spi",
114 [FUNC_TACHO] = "tacho",
115 [FUNC_TWI] = "twi",
116 [FUNC_TWI2] = "twi2",
117 [FUNC_TWI_SCL_M] = "twi_scl_m",
118 [FUNC_UART] = "uart",
119 [FUNC_UART2] = "uart2",
120};
121
122MSCC_P(0, SIO, NONE, NONE);
123MSCC_P(1, SIO, NONE, NONE);
124MSCC_P(2, SIO, NONE, NONE);
125MSCC_P(3, SIO, NONE, NONE);
126MSCC_P(4, IRQ0_IN, IRQ0_OUT, TWI_SCL_M);
127MSCC_P(5, IRQ1_IN, IRQ1_OUT, TWI_SCL_M);
128MSCC_P(6, UART, NONE, NONE);
129MSCC_P(7, UART, NONE, NONE);
130MSCC_P(8, SPI, SFP0, TWI_SCL_M);
131MSCC_P(9, PCI_WAKE, SFP1, SPI);
132MSCC_P(10, PTP0, SFP2, TWI_SCL_M);
133MSCC_P(11, PTP1, SFP3, TWI_SCL_M);
134MSCC_P(12, REF_CLK0, SFP4, TWI_SCL_M);
135MSCC_P(13, REF_CLK1, SFP5, TWI_SCL_M);
136MSCC_P(14, REF_CLK2, IRQ0_OUT, SPI);
137MSCC_P(15, REF_CLK3, IRQ1_OUT, SPI);
138MSCC_P(16, TACHO, SFP6, SPI);
139MSCC_P(17, PWM, NONE, TWI_SCL_M);
140MSCC_P(18, PTP2, SFP7, SPI);
141MSCC_P(19, PTP3, SFP8, SPI);
142MSCC_P(20, UART2, SFP9, SPI);
143MSCC_P(21, UART2, NONE, NONE);
144MSCC_P(22, MIIM1, SFP10, TWI2);
145MSCC_P(23, MIIM1, SFP11, TWI2);
146MSCC_P(24, TWI, NONE, NONE);
147MSCC_P(25, TWI, SFP12, TWI_SCL_M);
148MSCC_P(26, TWI_SCL_M, SFP13, SPI);
149MSCC_P(27, TWI_SCL_M, SFP14, SPI);
150MSCC_P(28, TWI_SCL_M, SFP15, SPI);
151MSCC_P(29, TWI_SCL_M, NONE, NONE);
152MSCC_P(30, TWI_SCL_M, NONE, NONE);
153MSCC_P(31, TWI_SCL_M, NONE, NONE);
154MSCC_P(32, TWI_SCL_M, NONE, NONE);
155MSCC_P(33, RCVRD_CLK0, NONE, NONE);
156MSCC_P(34, RCVRD_CLK1, NONE, NONE);
157MSCC_P(35, RCVRD_CLK2, NONE, NONE);
158MSCC_P(36, RCVRD_CLK3, NONE, NONE);
159
160#define SERVALT_PIN(n) { \
161 .name = "GPIO_"#n, \
162 .drv_data = &mscc_pin_##n \
163}
164
165static const struct mscc_pin_data servalt_pins[] = {
166 SERVALT_PIN(0),
167 SERVALT_PIN(1),
168 SERVALT_PIN(2),
169 SERVALT_PIN(3),
170 SERVALT_PIN(4),
171 SERVALT_PIN(5),
172 SERVALT_PIN(6),
173 SERVALT_PIN(7),
174 SERVALT_PIN(8),
175 SERVALT_PIN(9),
176 SERVALT_PIN(10),
177 SERVALT_PIN(11),
178 SERVALT_PIN(12),
179 SERVALT_PIN(13),
180 SERVALT_PIN(14),
181 SERVALT_PIN(15),
182 SERVALT_PIN(16),
183 SERVALT_PIN(17),
184 SERVALT_PIN(18),
185 SERVALT_PIN(19),
186 SERVALT_PIN(20),
187 SERVALT_PIN(21),
188 SERVALT_PIN(22),
189 SERVALT_PIN(23),
190 SERVALT_PIN(24),
191 SERVALT_PIN(25),
192 SERVALT_PIN(26),
193 SERVALT_PIN(27),
194 SERVALT_PIN(28),
195 SERVALT_PIN(29),
196 SERVALT_PIN(30),
197 SERVALT_PIN(31),
198 SERVALT_PIN(32),
199 SERVALT_PIN(33),
200 SERVALT_PIN(34),
201 SERVALT_PIN(35),
202 SERVALT_PIN(36),
203};
204
205static const unsigned long servalt_gpios[] = {
206 [MSCC_GPIO_OUT_SET] = 0x00,
207 [MSCC_GPIO_OUT_CLR] = 0x08,
208 [MSCC_GPIO_OUT] = 0x10,
209 [MSCC_GPIO_IN] = 0x18,
210 [MSCC_GPIO_OE] = 0x20,
211 [MSCC_GPIO_INTR] = 0x28,
212 [MSCC_GPIO_INTR_ENA] = 0x30,
213 [MSCC_GPIO_INTR_IDENT] = 0x38,
214 [MSCC_GPIO_ALT0] = 0x40,
215 [MSCC_GPIO_ALT1] = 0x48,
216};
217
218static int servalt_gpio_probe(struct udevice *dev)
219{
220 struct gpio_dev_priv *uc_priv;
221
222 uc_priv = dev_get_uclass_priv(dev);
223 uc_priv->bank_name = "servalt-gpio";
224 uc_priv->gpio_count = ARRAY_SIZE(servalt_pins);
225
226 return 0;
227}
228
229static struct driver servalt_gpio_driver = {
230 .name = "servalt-gpio",
231 .id = UCLASS_GPIO,
232 .probe = servalt_gpio_probe,
233 .ops = &mscc_gpio_ops,
234};
235
236static int servalt_pinctrl_probe(struct udevice *dev)
237{
238 int ret;
239
240 ret = mscc_pinctrl_probe(dev, FUNC_MAX, servalt_pins,
241 ARRAY_SIZE(servalt_pins),
242 servalt_function_names,
243 servalt_gpios);
244
245 if (ret)
246 return ret;
247
248 ret = device_bind(dev, &servalt_gpio_driver, "servalt-gpio", NULL,
249 dev_of_offset(dev), NULL);
250
251 if (ret)
252 return ret;
253
254 return 0;
255}
256
257static const struct udevice_id servalt_pinctrl_of_match[] = {
258 { .compatible = "mscc,servalt-pinctrl" },
259 {},
260};
261
262U_BOOT_DRIVER(servalt_pinctrl) = {
263 .name = "servalt-pinctrl",
264 .id = UCLASS_PINCTRL,
265 .of_match = of_match_ptr(servalt_pinctrl_of_match),
266 .probe = servalt_pinctrl_probe,
267 .priv_auto_alloc_size = sizeof(struct mscc_pinctrl),
268 .ops = &mscc_pinctrl_ops,
269};