blob: a1c43f8331787c7cf84e0eabcf0d373ae1ebabe4 [file] [log] [blame]
Simon Glass08d6ec22012-02-27 10:52:49 +00001/*
Jim Lin5a057e32012-06-24 20:40:57 +00002 * Copyright (c) 2009-2012 NVIDIA Corporation
Simon Glass08d6ec22012-02-27 10:52:49 +00003 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#include <common.h>
24#include <usb.h>
25
26#include "ehci.h"
Simon Glass08d6ec22012-02-27 10:52:49 +000027
28#include <asm/errno.h>
29#include <asm/arch/usb.h>
30
Jim Lin5a057e32012-06-24 20:40:57 +000031/*
32 * A known hardware issue where Connect Status Change bit of PORTSC register
33 * of USB1 controller will be set after Port Reset.
34 * We have to clear it in order for later device enumeration to proceed.
35 * This ehci_powerup_fixup overrides the weak function ehci_powerup_fixup
36 * in "ehci-hcd.c".
37 */
38void ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg)
39{
40 mdelay(50);
41 if (((u32) status_reg & TEGRA_USB_ADDR_MASK) != TEGRA_USB1_BASE)
42 return;
43 /* For EHCI_PS_CSC to be cleared in ehci_hcd.c */
44 if (ehci_readl(status_reg) & EHCI_PS_CSC)
45 *reg |= EHCI_PS_CSC;
46}
Simon Glass08d6ec22012-02-27 10:52:49 +000047
48/*
49 * Create the appropriate control structures to manage
50 * a new EHCI host controller.
51 */
Lucas Stach3494a4c2012-09-26 00:14:35 +020052int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
Simon Glass08d6ec22012-02-27 10:52:49 +000053{
54 u32 our_hccr, our_hcor;
55
56 /*
57 * Select the first port, as we don't have a way of selecting others
58 * yet
59 */
Lucas Stachc1275eb2012-09-26 00:14:37 +020060 if (tegrausb_start_port(index, &our_hccr, &our_hcor))
Simon Glass08d6ec22012-02-27 10:52:49 +000061 return -1;
62
Lucas Stach3494a4c2012-09-26 00:14:35 +020063 *hccr = (struct ehci_hccr *)our_hccr;
64 *hcor = (struct ehci_hcor *)our_hcor;
Simon Glass08d6ec22012-02-27 10:52:49 +000065
66 return 0;
67}
68
69/*
70 * Destroy the appropriate control structures corresponding
71 * the the EHCI host controller.
72 */
Lucas Stach3494a4c2012-09-26 00:14:35 +020073int ehci_hcd_stop(int index)
Simon Glass08d6ec22012-02-27 10:52:49 +000074{
Lucas Stachc1275eb2012-09-26 00:14:37 +020075 return tegrausb_stop_port(index);
Simon Glass08d6ec22012-02-27 10:52:49 +000076}