Simon Glass | 08d6ec2 | 2012-02-27 10:52:49 +0000 | [diff] [blame] | 1 | /* |
Jim Lin | 5a057e3 | 2012-06-24 20:40:57 +0000 | [diff] [blame] | 2 | * Copyright (c) 2009-2012 NVIDIA Corporation |
Simon Glass | 08d6ec2 | 2012-02-27 10:52:49 +0000 | [diff] [blame] | 3 | * |
| 4 | * See file CREDITS for list of people who contributed to this |
| 5 | * project. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; either version 2 of |
| 10 | * the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 20 | * MA 02111-1307 USA |
| 21 | */ |
| 22 | |
| 23 | #include <common.h> |
| 24 | #include <usb.h> |
| 25 | |
| 26 | #include "ehci.h" |
Simon Glass | 08d6ec2 | 2012-02-27 10:52:49 +0000 | [diff] [blame] | 27 | |
| 28 | #include <asm/errno.h> |
| 29 | #include <asm/arch/usb.h> |
| 30 | |
Jim Lin | 5a057e3 | 2012-06-24 20:40:57 +0000 | [diff] [blame] | 31 | /* |
| 32 | * A known hardware issue where Connect Status Change bit of PORTSC register |
| 33 | * of USB1 controller will be set after Port Reset. |
| 34 | * We have to clear it in order for later device enumeration to proceed. |
| 35 | * This ehci_powerup_fixup overrides the weak function ehci_powerup_fixup |
| 36 | * in "ehci-hcd.c". |
| 37 | */ |
| 38 | void ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg) |
| 39 | { |
| 40 | mdelay(50); |
| 41 | if (((u32) status_reg & TEGRA_USB_ADDR_MASK) != TEGRA_USB1_BASE) |
| 42 | return; |
| 43 | /* For EHCI_PS_CSC to be cleared in ehci_hcd.c */ |
| 44 | if (ehci_readl(status_reg) & EHCI_PS_CSC) |
| 45 | *reg |= EHCI_PS_CSC; |
| 46 | } |
Simon Glass | 08d6ec2 | 2012-02-27 10:52:49 +0000 | [diff] [blame] | 47 | |
| 48 | /* |
| 49 | * Create the appropriate control structures to manage |
| 50 | * a new EHCI host controller. |
| 51 | */ |
Lucas Stach | 3494a4c | 2012-09-26 00:14:35 +0200 | [diff] [blame] | 52 | int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) |
Simon Glass | 08d6ec2 | 2012-02-27 10:52:49 +0000 | [diff] [blame] | 53 | { |
| 54 | u32 our_hccr, our_hcor; |
| 55 | |
| 56 | /* |
| 57 | * Select the first port, as we don't have a way of selecting others |
| 58 | * yet |
| 59 | */ |
Lucas Stach | c1275eb | 2012-09-26 00:14:37 +0200 | [diff] [blame] | 60 | if (tegrausb_start_port(index, &our_hccr, &our_hcor)) |
Simon Glass | 08d6ec2 | 2012-02-27 10:52:49 +0000 | [diff] [blame] | 61 | return -1; |
| 62 | |
Lucas Stach | 3494a4c | 2012-09-26 00:14:35 +0200 | [diff] [blame] | 63 | *hccr = (struct ehci_hccr *)our_hccr; |
| 64 | *hcor = (struct ehci_hcor *)our_hcor; |
Simon Glass | 08d6ec2 | 2012-02-27 10:52:49 +0000 | [diff] [blame] | 65 | |
| 66 | return 0; |
| 67 | } |
| 68 | |
| 69 | /* |
| 70 | * Destroy the appropriate control structures corresponding |
| 71 | * the the EHCI host controller. |
| 72 | */ |
Lucas Stach | 3494a4c | 2012-09-26 00:14:35 +0200 | [diff] [blame] | 73 | int ehci_hcd_stop(int index) |
Simon Glass | 08d6ec2 | 2012-02-27 10:52:49 +0000 | [diff] [blame] | 74 | { |
Lucas Stach | c1275eb | 2012-09-26 00:14:37 +0200 | [diff] [blame] | 75 | return tegrausb_stop_port(index); |
Simon Glass | 08d6ec2 | 2012-02-27 10:52:49 +0000 | [diff] [blame] | 76 | } |