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git01.mediatek.com / filogic / uboot / 2f4b6424cfc561140092cdc6b66c864a960b75a7 / . / arch / arm / dts / stm32f429.dtsi
blob: c5c029b9e36c8240d698654b476b71ac64450156 [file] [log] [blame]
Patrice Chotardf13ff072017-12-12 09:49:32 +0100[diff] [blame]1/*
Patrice Chotard2f4b6422019-02-18 22:54:35 +0100[diff] [blame^]2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
Patrice Chotardf13ff072017-12-12 09:49:32 +0100[diff] [blame]3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43#include "skeleton.dtsi"
44#include "armv7-m.dtsi"
45#include <dt-bindings/clock/stm32fx-clock.h>
46#include <dt-bindings/mfd/stm32f4-rcc.h>
47
48/ {
49 clocks {
50 clk_hse: clk-hse {
51 #clock-cells = <0>;
52 compatible = "fixed-clock";
53 clock-frequency = <0>;
54 };
55
56 clk_lse: clk-lse {
57 #clock-cells = <0>;
58 compatible = "fixed-clock";
59 clock-frequency = <32768>;
60 };
61
62 clk_lsi: clk-lsi {
63 #clock-cells = <0>;
64 compatible = "fixed-clock";
65 clock-frequency = <32000>;
66 };
67
68 clk_i2s_ckin: i2s-ckin {
69 #clock-cells = <0>;
70 compatible = "fixed-clock";
71 clock-frequency = <0>;
72 };
73 };
74
75 soc {
76 timer2: timer@40000000 {
77 compatible = "st,stm32-timer";
78 reg = <0x40000000 0x400>;
79 interrupts = <28>;
80 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
81 status = "disabled";
82 };
83
84 timers2: timers@40000000 {
85 #address-cells = <1>;
86 #size-cells = <0>;
87 compatible = "st,stm32-timers";
88 reg = <0x40000000 0x400>;
89 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
90 clock-names = "int";
91 status = "disabled";
92
93 pwm {
94 compatible = "st,stm32-pwm";
95 status = "disabled";
96 };
97
98 timer@1 {
99 compatible = "st,stm32-timer-trigger";
100 reg = <1>;
101 status = "disabled";
102 };
103 };
104
105 timer3: timer@40000400 {
106 compatible = "st,stm32-timer";
107 reg = <0x40000400 0x400>;
108 interrupts = <29>;
109 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
110 status = "disabled";
111 };
112
113 timers3: timers@40000400 {
114 #address-cells = <1>;
115 #size-cells = <0>;
116 compatible = "st,stm32-timers";
117 reg = <0x40000400 0x400>;
118 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
119 clock-names = "int";
120 status = "disabled";
121
122 pwm {
123 compatible = "st,stm32-pwm";
124 status = "disabled";
125 };
126
127 timer@2 {
128 compatible = "st,stm32-timer-trigger";
129 reg = <2>;
130 status = "disabled";
131 };
132 };
133
134 timer4: timer@40000800 {
135 compatible = "st,stm32-timer";
136 reg = <0x40000800 0x400>;
137 interrupts = <30>;
138 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
139 status = "disabled";
140 };
141
142 timers4: timers@40000800 {
143 #address-cells = <1>;
144 #size-cells = <0>;
145 compatible = "st,stm32-timers";
146 reg = <0x40000800 0x400>;
147 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
148 clock-names = "int";
149 status = "disabled";
150
151 pwm {
152 compatible = "st,stm32-pwm";
153 status = "disabled";
154 };
155
156 timer@3 {
157 compatible = "st,stm32-timer-trigger";
158 reg = <3>;
159 status = "disabled";
160 };
161 };
162
163 timer5: timer@40000c00 {
164 compatible = "st,stm32-timer";
165 reg = <0x40000c00 0x400>;
166 interrupts = <50>;
167 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
168 };
169
170 timers5: timers@40000c00 {
171 #address-cells = <1>;
172 #size-cells = <0>;
173 compatible = "st,stm32-timers";
174 reg = <0x40000C00 0x400>;
175 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
176 clock-names = "int";
177 status = "disabled";
178
179 pwm {
180 compatible = "st,stm32-pwm";
181 status = "disabled";
182 };
183
184 timer@4 {
185 compatible = "st,stm32-timer-trigger";
186 reg = <4>;
187 status = "disabled";
188 };
189 };
190
191 timer6: timer@40001000 {
192 compatible = "st,stm32-timer";
193 reg = <0x40001000 0x400>;
194 interrupts = <54>;
195 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
196 status = "disabled";
197 };
198
199 timers6: timers@40001000 {
200 #address-cells = <1>;
201 #size-cells = <0>;
202 compatible = "st,stm32-timers";
203 reg = <0x40001000 0x400>;
204 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
205 clock-names = "int";
206 status = "disabled";
207
208 timer@5 {
209 compatible = "st,stm32-timer-trigger";
210 reg = <5>;
211 status = "disabled";
212 };
213 };
214
215 timer7: timer@40001400 {
216 compatible = "st,stm32-timer";
217 reg = <0x40001400 0x400>;
218 interrupts = <55>;
219 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
220 status = "disabled";
221 };
222
223 timers7: timers@40001400 {
224 #address-cells = <1>;
225 #size-cells = <0>;
226 compatible = "st,stm32-timers";
227 reg = <0x40001400 0x400>;
228 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
229 clock-names = "int";
230 status = "disabled";
231
232 timer@6 {
233 compatible = "st,stm32-timer-trigger";
234 reg = <6>;
235 status = "disabled";
236 };
237 };
238
239 timers12: timers@40001800 {
240 #address-cells = <1>;
241 #size-cells = <0>;
242 compatible = "st,stm32-timers";
243 reg = <0x40001800 0x400>;
244 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
245 clock-names = "int";
246 status = "disabled";
247
248 pwm {
249 compatible = "st,stm32-pwm";
250 status = "disabled";
251 };
252
253 timer@11 {
254 compatible = "st,stm32-timer-trigger";
255 reg = <11>;
256 status = "disabled";
257 };
258 };
259
260 timers13: timers@40001c00 {
Patrice Chotard2f4b6422019-02-18 22:54:35 +0100[diff] [blame^]261 #address-cells = <1>;
Patrice Chotardf13ff072017-12-12 09:49:32 +0100[diff] [blame]262 #size-cells = <0>;
263 compatible = "st,stm32-timers";
264 reg = <0x40001C00 0x400>;
265 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
266 clock-names = "int";
267 status = "disabled";
268
269 pwm {
270 compatible = "st,stm32-pwm";
271 status = "disabled";
272 };
273 };
274
275 timers14: timers@40002000 {
Patrice Chotard2f4b6422019-02-18 22:54:35 +0100[diff] [blame^]276 #address-cells = <1>;
Patrice Chotardf13ff072017-12-12 09:49:32 +0100[diff] [blame]277 #size-cells = <0>;
278 compatible = "st,stm32-timers";
279 reg = <0x40002000 0x400>;
280 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
281 clock-names = "int";
282 status = "disabled";
283
284 pwm {
285 compatible = "st,stm32-pwm";
286 status = "disabled";
287 };
288 };
289
290 rtc: rtc@40002800 {
291 compatible = "st,stm32-rtc";
292 reg = <0x40002800 0x400>;
293 clocks = <&rcc 1 CLK_RTC>;
294 clock-names = "ck_rtc";
295 assigned-clocks = <&rcc 1 CLK_RTC>;
296 assigned-clock-parents = <&rcc 1 CLK_LSE>;
297 interrupt-parent = <&exti>;
298 interrupts = <17 1>;
299 interrupt-names = "alarm";
Patrice Chotard2f4b6422019-02-18 22:54:35 +0100[diff] [blame^]300 st,syscfg = <&pwrcfg 0x00 0x100>;
Patrice Chotardf13ff072017-12-12 09:49:32 +0100[diff] [blame]301 status = "disabled";
302 };
303
304 iwdg: watchdog@40003000 {
305 compatible = "st,stm32-iwdg";
306 reg = <0x40003000 0x400>;
307 clocks = <&clk_lsi>;
Patrice Chotard2f4b6422019-02-18 22:54:35 +0100[diff] [blame^]308 clock-names = "lsi";
Patrice Chotardf13ff072017-12-12 09:49:32 +0100[diff] [blame]309 status = "disabled";
310 };
311
312 usart2: serial@40004400 {
313 compatible = "st,stm32-uart";
314 reg = <0x40004400 0x400>;
315 interrupts = <38>;
316 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>;
317 status = "disabled";
318 };
319
320 usart3: serial@40004800 {
321 compatible = "st,stm32-uart";
322 reg = <0x40004800 0x400>;
323 interrupts = <39>;
324 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>;
325 status = "disabled";
326 dmas = <&dma1 1 4 0x400 0x0>,
327 <&dma1 3 4 0x400 0x0>;
328 dma-names = "rx", "tx";
329 };
330
331 usart4: serial@40004c00 {
332 compatible = "st,stm32-uart";
333 reg = <0x40004c00 0x400>;
334 interrupts = <52>;
335 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>;
336 status = "disabled";
337 };
338
339 usart5: serial@40005000 {
340 compatible = "st,stm32-uart";
341 reg = <0x40005000 0x400>;
342 interrupts = <53>;
343 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>;
344 status = "disabled";
345 };
346
347 i2c1: i2c@40005400 {
348 compatible = "st,stm32f4-i2c";
349 reg = <0x40005400 0x400>;
350 interrupts = <31>,
351 <32>;
352 resets = <&rcc STM32F4_APB1_RESET(I2C1)>;
353 clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>;
354 #address-cells = <1>;
355 #size-cells = <0>;
356 status = "disabled";
357 };
358
359 dac: dac@40007400 {
360 compatible = "st,stm32f4-dac-core";
361 reg = <0x40007400 0x400>;
362 resets = <&rcc STM32F4_APB1_RESET(DAC)>;
363 clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>;
364 clock-names = "pclk";
365 #address-cells = <1>;
366 #size-cells = <0>;
367 status = "disabled";
368
369 dac1: dac@1 {
370 compatible = "st,stm32-dac";
371 #io-channels-cells = <1>;
372 reg = <1>;
373 status = "disabled";
374 };
375
376 dac2: dac@2 {
377 compatible = "st,stm32-dac";
378 #io-channels-cells = <1>;
379 reg = <2>;
380 status = "disabled";
381 };
382 };
383
384 usart7: serial@40007800 {
385 compatible = "st,stm32-uart";
386 reg = <0x40007800 0x400>;
387 interrupts = <82>;
388 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>;
389 status = "disabled";
390 };
391
392 usart8: serial@40007c00 {
393 compatible = "st,stm32-uart";
394 reg = <0x40007c00 0x400>;
395 interrupts = <83>;
396 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>;
397 status = "disabled";
398 };
399
400 timers1: timers@40010000 {
401 #address-cells = <1>;
402 #size-cells = <0>;
403 compatible = "st,stm32-timers";
404 reg = <0x40010000 0x400>;
405 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>;
406 clock-names = "int";
407 status = "disabled";
408
409 pwm {
410 compatible = "st,stm32-pwm";
411 status = "disabled";
412 };
413
414 timer@0 {
415 compatible = "st,stm32-timer-trigger";
416 reg = <0>;
417 status = "disabled";
418 };
419 };
420
421 timers8: timers@40010400 {
422 #address-cells = <1>;
423 #size-cells = <0>;
424 compatible = "st,stm32-timers";
425 reg = <0x40010400 0x400>;
426 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>;
427 clock-names = "int";
428 status = "disabled";
429
430 pwm {
431 compatible = "st,stm32-pwm";
432 status = "disabled";
433 };
434
435 timer@7 {
436 compatible = "st,stm32-timer-trigger";
437 reg = <7>;
438 status = "disabled";
439 };
440 };
441
442 usart1: serial@40011000 {
443 compatible = "st,stm32-uart";
444 reg = <0x40011000 0x400>;
445 interrupts = <37>;
446 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>;
447 status = "disabled";
448 dmas = <&dma2 2 4 0x400 0x0>,
449 <&dma2 7 4 0x400 0x0>;
450 dma-names = "rx", "tx";
451 };
452
453 usart6: serial@40011400 {
454 compatible = "st,stm32-uart";
455 reg = <0x40011400 0x400>;
456 interrupts = <71>;
457 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>;
458 status = "disabled";
459 };
460
461 adc: adc@40012000 {
462 compatible = "st,stm32f4-adc-core";
463 reg = <0x40012000 0x400>;
464 interrupts = <18>;
465 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
466 clock-names = "adc";
467 interrupt-controller;
468 #interrupt-cells = <1>;
469 #address-cells = <1>;
470 #size-cells = <0>;
471 status = "disabled";
472
473 adc1: adc@0 {
474 compatible = "st,stm32f4-adc";
475 #io-channel-cells = <1>;
476 reg = <0x0>;
477 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
478 interrupt-parent = <&adc>;
479 interrupts = <0>;
480 dmas = <&dma2 0 0 0x400 0x0>;
481 dma-names = "rx";
482 status = "disabled";
483 };
484
485 adc2: adc@100 {
486 compatible = "st,stm32f4-adc";
487 #io-channel-cells = <1>;
488 reg = <0x100>;
489 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>;
490 interrupt-parent = <&adc>;
491 interrupts = <1>;
492 dmas = <&dma2 3 1 0x400 0x0>;
493 dma-names = "rx";
494 status = "disabled";
495 };
496
497 adc3: adc@200 {
498 compatible = "st,stm32f4-adc";
499 #io-channel-cells = <1>;
500 reg = <0x200>;
501 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>;
502 interrupt-parent = <&adc>;
503 interrupts = <2>;
504 dmas = <&dma2 1 2 0x400 0x0>;
505 dma-names = "rx";
506 status = "disabled";
507 };
508 };
509
Patrice Chotard2f4b6422019-02-18 22:54:35 +0100[diff] [blame^]510 sdio: sdio@40012c00 {
511 compatible = "arm,pl180", "arm,primecell";
512 arm,primecell-periphid = <0x00880180>;
513 reg = <0x40012c00 0x400>;
514 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>;
515 clock-names = "apb_pclk";
516 interrupts = <49>;
517 max-frequency = <48000000>;
518 status = "disabled";
519 };
520
Patrice Chotardf13ff072017-12-12 09:49:32 +0100[diff] [blame]521 syscfg: system-config@40013800 {
522 compatible = "syscon";
523 reg = <0x40013800 0x400>;
524 };
525
526 exti: interrupt-controller@40013c00 {
527 compatible = "st,stm32-exti";
528 interrupt-controller;
529 #interrupt-cells = <2>;
530 reg = <0x40013C00 0x400>;
531 interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
532 };
533
534 timers9: timers@40014000 {
535 #address-cells = <1>;
536 #size-cells = <0>;
537 compatible = "st,stm32-timers";
538 reg = <0x40014000 0x400>;
539 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>;
540 clock-names = "int";
541 status = "disabled";
542
543 pwm {
544 compatible = "st,stm32-pwm";
545 status = "disabled";
546 };
547
548 timer@8 {
549 compatible = "st,stm32-timer-trigger";
550 reg = <8>;
551 status = "disabled";
552 };
553 };
554
555 timers10: timers@40014400 {
Patrice Chotard2f4b6422019-02-18 22:54:35 +0100[diff] [blame^]556 #address-cells = <1>;
Patrice Chotardf13ff072017-12-12 09:49:32 +0100[diff] [blame]557 #size-cells = <0>;
558 compatible = "st,stm32-timers";
559 reg = <0x40014400 0x400>;
560 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
561 clock-names = "int";
562 status = "disabled";
563
564 pwm {
565 compatible = "st,stm32-pwm";
566 status = "disabled";
567 };
568 };
569
570 timers11: timers@40014800 {
Patrice Chotard2f4b6422019-02-18 22:54:35 +0100[diff] [blame^]571 #address-cells = <1>;
Patrice Chotardf13ff072017-12-12 09:49:32 +0100[diff] [blame]572 #size-cells = <0>;
573 compatible = "st,stm32-timers";
574 reg = <0x40014800 0x400>;
575 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
576 clock-names = "int";
577 status = "disabled";
578
579 pwm {
580 compatible = "st,stm32-pwm";
581 status = "disabled";
582 };
583 };
584
585 pwrcfg: power-config@40007000 {
586 compatible = "syscon";
587 reg = <0x40007000 0x400>;
588 };
589
Patrice Chotardf13ff072017-12-12 09:49:32 +0100[diff] [blame]590 ltdc: display-controller@40016800 {
591 compatible = "st,stm32-ltdc";
592 reg = <0x40016800 0x200>;
593 interrupts = <88>, <89>;
594 resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
595 clocks = <&rcc 1 CLK_LCD>;
596 clock-names = "lcd";
597 status = "disabled";
598 };
599
600 crc: crc@40023000 {
601 compatible = "st,stm32f4-crc";
602 reg = <0x40023000 0x400>;
603 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>;
604 status = "disabled";
605 };
606
607 rcc: rcc@40023810 {
608 #reset-cells = <1>;
609 #clock-cells = <2>;
610 compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
611 reg = <0x40023800 0x400>;
612 clocks = <&clk_hse>, <&clk_i2s_ckin>;
613 st,syscfg = <&pwrcfg>;
614 assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
615 assigned-clock-rates = <1000000>;
616 };
617
618 dma1: dma-controller@40026000 {
619 compatible = "st,stm32-dma";
620 reg = <0x40026000 0x400>;
621 interrupts = <11>,
622 <12>,
623 <13>,
624 <14>,
625 <15>,
626 <16>,
627 <17>,
628 <47>;
629 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>;
630 #dma-cells = <4>;
631 };
632
633 dma2: dma-controller@40026400 {
634 compatible = "st,stm32-dma";
635 reg = <0x40026400 0x400>;
636 interrupts = <56>,
637 <57>,
638 <58>,
639 <59>,
640 <60>,
641 <68>,
642 <69>,
643 <70>;
644 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>;
645 #dma-cells = <4>;
646 st,mem2mem;
647 };
648
649 mac: ethernet@40028000 {
650 compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
651 reg = <0x40028000 0x8000>;
652 reg-names = "stmmaceth";
653 interrupts = <61>;
654 interrupt-names = "macirq";
655 clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
656 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>,
657 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>,
658 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>;
659 st,syscon = <&syscfg 0x4>;
660 snps,pbl = <8>;
661 snps,mixed-burst;
662 status = "disabled";
663 };
664
665 usbotg_hs: usb@40040000 {
666 compatible = "snps,dwc2";
667 reg = <0x40040000 0x40000>;
668 interrupts = <77>;
669 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>;
670 clock-names = "otg";
671 status = "disabled";
672 };
673
674 usbotg_fs: usb@50000000 {
675 compatible = "st,stm32f4x9-fsotg";
676 reg = <0x50000000 0x40000>;
677 interrupts = <67>;
678 clocks = <&rcc 0 39>;
679 clock-names = "otg";
680 status = "disabled";
681 };
682
683 dcmi: dcmi@50050000 {
684 compatible = "st,stm32-dcmi";
685 reg = <0x50050000 0x400>;
686 interrupts = <78>;
687 resets = <&rcc STM32F4_AHB2_RESET(DCMI)>;
688 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>;
689 clock-names = "mclk";
690 pinctrl-names = "default";
691 pinctrl-0 = <&dcmi_pins>;
692 dmas = <&dma2 1 1 0x414 0x3>;
693 dma-names = "tx";
694 status = "disabled";
695 };
696
697 rng: rng@50060800 {
698 compatible = "st,stm32-rng";
699 reg = <0x50060800 0x400>;
700 interrupts = <80>;
701 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;
702
703 };
704 };
705};
706
707&systick {
708 clocks = <&rcc 1 SYSTICK>;
709 status = "okay";
710};