Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 2f41d924fc9dbc2698a2ef4428f4f01c8ff28d4a / . / arch / arm / dts / imx6ull-colibri.dtsi
blob: 56ee2895ae564d42d06677e1b11eca84317c5b76 [file] [log] [blame]
Igor Opaniuk1ec7c002019-10-16 13:39:35 +0300[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
Max Krummenacher1f6668a2021-10-06 18:55:36 +0200[diff] [blame]3 * Copyright 2019-2021 Toradex AG
Igor Opaniuk1ec7c002019-10-16 13:39:35 +0300[diff] [blame]4 */
5
6/dts-v1/;
7#include <dt-bindings/gpio/gpio.h>
8#include "imx6ull.dtsi"
9
10/ {
Francesco Dolcini2f41d922021-09-23 09:55:21 +0200[diff] [blame^]11 /* Ethernet aliases to ensure correct MAC addresses */
12 aliases {
13 ethernet0 = &fec2;
14 ethernet1 = &fec1;
15 };
16
Igor Opaniuk1ec7c002019-10-16 13:39:35 +0300[diff] [blame]17 chosen {
18 stdout-path = &uart1;
19 };
20
21 reg_module_3v3: regulator-module-3v3 {
22 compatible = "regulator-fixed";
23 regulator-always-on;
24 regulator-name = "+V3.3";
25 regulator-min-microvolt = <3300000>;
26 regulator-max-microvolt = <3300000>;
27 };
28
29 reg_module_3v3_avdd: regulator-module-3v3-avdd {
30 compatible = "regulator-fixed";
31 regulator-always-on;
32 regulator-name = "+V3.3_AVDD_AUDIO";
33 regulator-min-microvolt = <3300000>;
34 regulator-max-microvolt = <3300000>;
35 };
36
37 reg_5v0: regulator-5v0 {
38 compatible = "regulator-fixed";
39 regulator-name = "5V";
40 regulator-min-microvolt = <5000000>;
41 regulator-max-microvolt = <5000000>;
42 };
43
44 reg_sd1_vmmc: regulator-sd1-vmmc {
45 compatible = "regulator-gpio";
46 gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>;
47 pinctrl-names = "default";
48 pinctrl-0 = <&pinctrl_snvs_reg_sd>;
49 regulator-always-on;
50 regulator-name = "+V3.3_1.8_SD";
51 regulator-min-microvolt = <1800000>;
52 regulator-max-microvolt = <3300000>;
53 states = <1800000 0x1 3300000 0x0>;
54 vin-supply = <&reg_module_3v3>;
55 };
56
57 reg_usbh_vbus: regulator-usbh-vbus {
58 compatible = "regulator-fixed";
59 pinctrl-names = "default";
60 pinctrl-0 = <&pinctrl_usbh_reg>;
61 regulator-name = "VCC_USB[1-4]";
62 regulator-min-microvolt = <5000000>;
63 regulator-max-microvolt = <5000000>;
64 gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; /* USBH_PEN */
65 vin-supply = <&reg_5v0>;
66 };
67};
68
69&adc1 {
70 num-channels = <10>;
71 vref-supply = <&reg_module_3v3_avdd>;
72};
73
74/* Colibri SPI */
75&ecspi1 {
76 cs-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>;
77 pinctrl-names = "default";
78 pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
79};
80
81/* Ethernet */
82&fec2 {
83 pinctrl-names = "default";
84 pinctrl-0 = <&pinctrl_enet2>;
85 phy-mode = "rmii";
86 phy-handle = <&ethphy1>;
87 status = "okay";
88
89 mdio {
90 #address-cells = <1>;
91 #size-cells = <0>;
92
93 ethphy1: ethernet-phy@2 {
94 compatible = "ethernet-phy-ieee802.3-c22";
95 max-speed = <100>;
96 reg = <2>;
97 };
98 };
99};
100
Igor Opaniuk1ec7c002019-10-16 13:39:35 +0300[diff] [blame]101/*
102 * I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board)
103 */
104&i2c1 {
105 pinctrl-names = "default", "gpio";
106 pinctrl-0 = <&pinctrl_i2c1>;
107 pinctrl-1 = <&pinctrl_i2c1_gpio>;
108 sda-gpios = <&gpio1 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
109 scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
110 status = "okay";
111};
112
113/*
114 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
115 * touch screen controller
116 */
117&i2c2 {
118 pinctrl-names = "default", "gpio";
119 pinctrl-0 = <&pinctrl_i2c2>;
120 pinctrl-1 = <&pinctrl_i2c2_gpio>;
121 sda-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
122 scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
123 status = "okay";
124
125 ad7879@2c {
126 compatible = "adi,ad7879-1";
127 pinctrl-names = "default";
128 pinctrl-0 = <&pinctrl_snvs_ad7879_int>;
129 reg = <0x2c>;
130 interrupt-parent = <&gpio5>;
131 interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
132 touchscreen-max-pressure = <4096>;
133 adi,resistance-plate-x = <120>;
134 adi,first-conversion-delay = /bits/ 8 <3>;
135 adi,acquisition-time = /bits/ 8 <1>;
136 adi,median-filter-size = /bits/ 8 <2>;
137 adi,averaging = /bits/ 8 <1>;
138 adi,conversion-interval = /bits/ 8 <255>;
139 };
140};
141
Igor Opaniuk1ec7c002019-10-16 13:39:35 +0300[diff] [blame]142/* PWM <A> */
143&pwm4 {
144 pinctrl-names = "default";
145 pinctrl-0 = <&pinctrl_pwm4>;
146 #pwm-cells = <3>;
147};
148
149/* PWM <B> */
150&pwm5 {
151 pinctrl-names = "default";
152 pinctrl-0 = <&pinctrl_pwm5>;
153 #pwm-cells = <3>;
154};
155
156/* PWM <C> */
157&pwm6 {
158 pinctrl-names = "default";
159 pinctrl-0 = <&pinctrl_pwm6>;
160 #pwm-cells = <3>;
161};
162
163/* PWM <D> */
164&pwm7 {
165 pinctrl-names = "default";
166 pinctrl-0 = <&pinctrl_pwm7>;
167 #pwm-cells = <3>;
168};
169
170&sdma {
171 status = "okay";
172};
173
174&snvs_pwrkey {
175 status = "disabled";
176};
177
178/* Colibri UART_A */
179&uart1 {
180 pinctrl-names = "default";
181 pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>;
182 uart-has-rtscts;
183 fsl,dte-mode;
184 status = "okay";
185};
186
187/* Colibri UART_B */
188&uart2 {
189 pinctrl-names = "default";
190 pinctrl-0 = <&pinctrl_uart2>;
191 uart-has-rtscts;
192 fsl,dte-mode;
193};
194
195/* Colibri UART_C */
196&uart5 {
197 pinctrl-names = "default";
198 pinctrl-0 = <&pinctrl_uart5>;
199 fsl,dte-mode;
200};
201
202/* Colibri USBC */
203&usbotg1 {
204 dr_mode = "host";
205 srp-disable;
206 hnp-disable;
207 adp-disable;
208 status = "okay";
209};
210
211/* Colibri USBH */
212&usbotg2 {
213 dr_mode = "host";
214 vbus-supply = <&reg_usbh_vbus>;
215 status = "okay";
216};
217
218/* Colibri MMC */
219&usdhc1 {
220 assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>;
221 assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
222 assigned-clock-rates = <0>, <198000000>;
223 cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; /* MMC_CD */
224 pinctrl-names = "default", "state_100mhz", "state_200mhz";
225 pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>;
226 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
227 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
228 vmmc-supply = <&reg_sd1_vmmc>;
229 status = "okay";
230};
231
232&iomuxc {
233 pinctrl_can_int: canint-grp {
234 fsl,pins = <
235 /* SODIMM 73 */
236 MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0X14
237 >;
238 };
239
240 pinctrl_enet2: enet2-grp {
241 fsl,pins = <
242 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
243 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
244 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
245 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
246 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
247 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
248 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
249 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
250 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
251 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
252 >;
253 };
254
255 pinctrl_ecspi1_cs: ecspi1-cs-grp {
256 fsl,pins = <
257 MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x000a0
258 >;
259 };
260
261 pinctrl_ecspi1: ecspi1-grp {
262 fsl,pins = <
263 MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x000a0
264 MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x000a0
265 MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x100a0
266 >;
267 };
268
269 pinctrl_flexcan2: flexcan2-grp {
270 fsl,pins = <
271 MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x1b020
272 MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x1b020
273 >;
274 };
275
276 pinctrl_gpio_bl_on: gpio-bl-on-grp {
277 fsl,pins = <
278 MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x000a0
279 >;
280 };
281
282 pinctrl_gpio1: gpio1-grp {
283 fsl,pins = <
284 MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0x74 /* SODIMM 55 */
285 MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0x74 /* SODIMM 63 */
286 MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0X14 /* SODIMM 77 */
287 MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x14 /* SODIMM 99 */
288 MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x14 /* SODIMM 133 */
289 MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x14 /* SODIMM 135 */
290 MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x14 /* SODIMM 100 */
291 MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x14 /* SODIMM 102 */
292 MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07 0x14 /* SODIMM 104 */
293 MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x14 /* SODIMM 186 */
294 >;
295 };
296
297 pinctrl_gpio2: gpio2-grp { /* Camera */
298 fsl,pins = <
299 MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x74 /* SODIMM 69 */
300 MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x14 /* SODIMM 75 */
301 MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x14 /* SODIMM 85 */
302 MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x14 /* SODIMM 96 */
303 MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x14 /* SODIMM 98 */
304 >;
305 };
306
307 pinctrl_gpio3: gpio3-grp { /* CAN2 */
308 fsl,pins = <
309 MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02 0x14 /* SODIMM 178 */
310 MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x14 /* SODIMM 188 */
311 >;
312 };
313
314 pinctrl_gpio4: gpio4-grp {
315 fsl,pins = <
316 MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x74 /* SODIMM 65 */
317 >;
318 };
319
320 pinctrl_gpio5: gpio5-grp { /* ATMEL MXT TOUCH */
321 fsl,pins = <
322 MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x74 /* SODIMM 106 */
323 >;
324 };
325
326 pinctrl_gpio6: gpio6-grp { /* Wifi pins */
327 fsl,pins = <
328 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x14 /* SODIMM 89 */
329 MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x14 /* SODIMM 79 */
330 MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x14 /* SODIMM 81 */
331 MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x14 /* SODIMM 97 */
332 MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x14 /* SODIMM 101 */
333 MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x14 /* SODIMM 103 */
334 MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x14 /* SODIMM 94 */
335 >;
336 };
337
Igor Opaniuk1ec7c002019-10-16 13:39:35 +0300[diff] [blame]338 pinctrl_i2c1: i2c1-grp {
339 fsl,pins = <
340 MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
341 MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
342 >;
343 };
344
345 pinctrl_i2c1_gpio: i2c1-gpio-grp {
346 fsl,pins = <
347 MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0
348 MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0
349 >;
350 };
351
352 pinctrl_i2c2: i2c2-grp {
353 fsl,pins = <
354 MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
355 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
356 >;
357 };
358
359 pinctrl_i2c2_gpio: i2c2-gpio-grp {
360 fsl,pins = <
361 MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001b8b0
362 MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001b8b0
363 >;
364 };
365
366 pinctrl_lcdif_dat: lcdif-dat-grp {
367 fsl,pins = <
368 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x00079
369 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x00079
370 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x00079
371 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x00079
372 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x00079
373 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x00079
374 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x00079
375 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x00079
376 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x00079
377 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x00079
378 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x00079
379 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x00079
380 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x00079
381 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x00079
382 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x00079
383 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x00079
384 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x00079
385 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x00079
386 >;
387 };
388
389 pinctrl_lcdif_ctrl: lcdif-ctrl-grp {
390 fsl,pins = <
391 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x00079
392 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x00079
393 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x00079
394 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x00079
395 >;
396 };
397
398 pinctrl_pwm4: pwm4-grp {
399 fsl,pins = <
400 MX6UL_PAD_NAND_WP_B__PWM4_OUT 0x00079
401 >;
402 };
403
404 pinctrl_pwm5: pwm5-grp {
405 fsl,pins = <
406 MX6UL_PAD_NAND_DQS__PWM5_OUT 0x00079
407 >;
408 };
409
410 pinctrl_pwm6: pwm6-grp {
411 fsl,pins = <
412 MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 0x00079
413 >;
414 };
415
416 pinctrl_pwm7: pwm7-grp {
417 fsl,pins = <
418 MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x00079
419 >;
420 };
421
422 pinctrl_uart1: uart1-grp {
423 fsl,pins = <
424 MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX 0x1b0b1
425 MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX 0x1b0b1
426 MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS 0x1b0b1
427 MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS 0x1b0b1
428 >;
429 };
430
431 pinctrl_uart1_ctrl1: uart1-ctrl1-grp { /* Additional DTR, DCD */
432 fsl,pins = <
433 MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x1b0b1 /* DCD */
434 MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x1b0b1 /* DSR */
435 MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x1b0b1 /* DTR */
436 MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x1b0b1 /* RI */
437 >;
438 };
439
440 pinctrl_uart2: uart2-grp {
441 fsl,pins = <
442 MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1
443 MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1
444 MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x1b0b1
445 MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x1b0b1
446 >;
447 };
448 pinctrl_uart5: uart5-grp {
449 fsl,pins = <
450 MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX 0x1b0b1
451 MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX 0x1b0b1
452 >;
453 };
454
455 pinctrl_usbh_reg: gpio-usbh-reg {
456 fsl,pins = <
457 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x1b0b1 /* SODIMM 129 USBH PEN */
458 >;
459 };
460
461 pinctrl_usdhc1: usdhc1-grp {
462 fsl,pins = <
463 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17059
464 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x10059
465 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
466 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
467 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
468 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
469 >;
470 };
471
472 pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
473 fsl,pins = <
474 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x170b9
475 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x100b9
476 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
477 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
478 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
479 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
480 >;
481 };
482
483 pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
484 fsl,pins = <
485 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x170f9
486 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x100f9
487 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
488 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
489 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
490 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
491 >;
492 };
493
494 pinctrl_usdhc2: usdhc2-grp {
495 fsl,pins = <
496 MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17059
497 MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17059
498 MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17059
499 MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17059
500 MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059
501 MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x17059
502
503 MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x14
504 >;
505 };
506};
507
508&iomuxc_snvs {
509 pinctrl_snvs_gpio1: snvs-gpio1-grp {
510 fsl,pins = <
511 MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x14 /* SODIMM 93 */
512 MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x14 /* SODIMM 95 */
513 MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x74 /* SODIMM 105 */
514 MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x14 /* SODIMM 131 USBH OC */
515 MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x74 /* SODIMM 138 */
516 >;
517 };
518
519 pinctrl_snvs_gpio2: snvs-gpio2-grp { /* ATMEL MXT TOUCH */
520 fsl,pins = <
521 MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x74 /* SODIMM 107 */
522 >;
523 };
524
525 pinctrl_snvs_gpio3: snvs-gpio3-grp { /* Wifi pins */
526 fsl,pins = <
527 MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x14 /* SODIMM 127 */
528 >;
529 };
530
531 pinctrl_snvs_ad7879_int: snvs-ad7879-int-grp { /* TOUCH Interrupt */
532 fsl,pins = <
533 MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b0b0
534 >;
535 };
536
537 pinctrl_snvs_reg_sd: snvs-reg-sd-grp {
538 fsl,pins = <
539 MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x4001b8b0
540 >;
541 };
542
543 pinctrl_snvs_usbc_det: snvs-usbc-det-grp {
544 fsl,pins = <
545 MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0
546 >;
547 };
548
549 pinctrl_snvs_gpiokeys: snvs-gpiokeys-grp {
550 fsl,pins = <
551 MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x130b0
552 >;
553 };
554
555 pinctrl_snvs_usdhc1_cd: snvs-usdhc1-cd-grp {
556 fsl,pins = <
557 MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* CD */
558 >;
559 };
560
561 pinctrl_snvs_wifi_pdn: snvs-wifi-pdn-grp {
562 fsl,pins = <
563 MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x14
564 >;
565 };
566};