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goda.yusukefd768072008-01-25 20:46:36 +09001/*
2 * Configuation settings for the Renesas Solutions Migo-R board
3 *
4 * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
5 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
goda.yusukefd768072008-01-25 20:46:36 +09007 */
8
9#ifndef __MIGO_R_H
10#define __MIGO_R_H
11
goda.yusukefd768072008-01-25 20:46:36 +090012#define CONFIG_CPU_SH7722 1
13#define CONFIG_MIGO_R 1
14
goda.yusukefd768072008-01-25 20:46:36 +090015#define CONFIG_CMD_SDRAM
goda.yusukefd768072008-01-25 20:46:36 +090016
goda.yusukefd768072008-01-25 20:46:36 +090017#define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01"
goda.yusukefd768072008-01-25 20:46:36 +090018
Vladimir Zapolskiy5e72b842016-11-28 00:15:30 +020019#define CONFIG_DISPLAY_BOARDINFO
goda.yusukefd768072008-01-25 20:46:36 +090020#undef CONFIG_SHOW_BOOT_PROGRESS
21
22/* SMC9111 */
Ben Warren0fd6aae2009-10-04 22:37:03 -070023#define CONFIG_SMC91111
goda.yusukefd768072008-01-25 20:46:36 +090024#define CONFIG_SMC91111_BASE (0xB0000000)
25
26/* MEMORY */
27#define MIGO_R_SDRAM_BASE (0x8C000000)
28#define MIGO_R_FLASH_BASE_1 (0xA0000000)
29#define MIGO_R_FLASH_BANK_SIZE (64 * 1024 * 1024)
30
Nobuhiro Iwamatsu66a5a382011-01-17 20:43:40 +090031#define CONFIG_SYS_TEXT_BASE 0x8FFC0000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020032#define CONFIG_SYS_LONGHELP /* undef to save memory */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020033#define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */
34#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
35#define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */
36#define CONFIG_SYS_BARGSIZE 512 /* Buffer size for Boot Arguments passed to kernel */
37#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */
goda.yusukefd768072008-01-25 20:46:36 +090038
39/* SCIF */
Jean-Christophe PLAGNIOL-VILLARD6ce9ea62008-08-13 01:40:38 +020040#define CONFIG_SCIF_CONSOLE 1
goda.yusukefd768072008-01-25 20:46:36 +090041#define CONFIG_CONS_SCIF0 1
goda.yusukefd768072008-01-25 20:46:36 +090042
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020043#define CONFIG_SYS_MEMTEST_START (MIGO_R_SDRAM_BASE)
44#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
goda.yusukefd768072008-01-25 20:46:36 +090045
46/* Enable alternate, more extensive, memory test */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020047#undef CONFIG_SYS_ALT_MEMTEST
goda.yusukefd768072008-01-25 20:46:36 +090048/* Scratch address used by the alternate memory test */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020049#undef CONFIG_SYS_MEMTEST_SCRATCH
goda.yusukefd768072008-01-25 20:46:36 +090050
51/* Enable temporary baudrate change while serial download */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020052#undef CONFIG_SYS_LOADS_BAUD_CHANGE
goda.yusukefd768072008-01-25 20:46:36 +090053
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020054#define CONFIG_SYS_SDRAM_BASE (MIGO_R_SDRAM_BASE)
goda.yusukefd768072008-01-25 20:46:36 +090055/* maybe more, but if so u-boot doesn't know about it... */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020056#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
goda.yusukefd768072008-01-25 20:46:36 +090057/* default load address for scripts ?!? */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020058#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
goda.yusukefd768072008-01-25 20:46:36 +090059
60/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020061#define CONFIG_SYS_MONITOR_BASE (MIGO_R_FLASH_BASE_1)
goda.yusukefd768072008-01-25 20:46:36 +090062/* Monitor size */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020063#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
goda.yusukefd768072008-01-25 20:46:36 +090064/* Size of DRAM reserved for malloc() use */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020065#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020066#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
goda.yusukefd768072008-01-25 20:46:36 +090067
68/* FLASH */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020069#define CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +020070#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020071#undef CONFIG_SYS_FLASH_QUIET_TEST
goda.yusukefd768072008-01-25 20:46:36 +090072/* print 'E' for empty sector on flinfo */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020073#define CONFIG_SYS_FLASH_EMPTY_INFO
goda.yusukefd768072008-01-25 20:46:36 +090074/* Physical start address of Flash memory */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020075#define CONFIG_SYS_FLASH_BASE (MIGO_R_FLASH_BASE_1)
goda.yusukefd768072008-01-25 20:46:36 +090076/* Max number of sectors on each Flash chip */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020077#define CONFIG_SYS_MAX_FLASH_SECT 512
goda.yusukefd768072008-01-25 20:46:36 +090078
79/* if you use all NOR Flash , you change dip-switch. Please see MIGO_R01 Manual. */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020080#define CONFIG_SYS_MAX_FLASH_BANKS 1
81#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + (0 * MIGO_R_FLASH_BANK_SIZE) }
goda.yusukefd768072008-01-25 20:46:36 +090082
83/* Timeout for Flash erase operations (in ms) */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020084#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
goda.yusukefd768072008-01-25 20:46:36 +090085/* Timeout for Flash write operations (in ms) */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020086#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
goda.yusukefd768072008-01-25 20:46:36 +090087/* Timeout for Flash set sector lock bit operations (in ms) */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020088#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
goda.yusukefd768072008-01-25 20:46:36 +090089/* Timeout for Flash clear lock bit operations (in ms) */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020090#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
goda.yusukefd768072008-01-25 20:46:36 +090091
92/* Use hardware flash sectors protection instead of U-Boot software protection */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020093#undef CONFIG_SYS_FLASH_PROTECTION
94#undef CONFIG_SYS_DIRECT_FLASH_TFTP
goda.yusukefd768072008-01-25 20:46:36 +090095
96/* ENV setting */
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +020097#define CONFIG_ENV_IS_IN_FLASH
goda.yusukefd768072008-01-25 20:46:36 +090098#define CONFIG_ENV_OVERWRITE 1
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +020099#define CONFIG_ENV_SECT_SIZE (128 * 1024)
100#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200101#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
102/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
103#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200104#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
goda.yusukefd768072008-01-25 20:46:36 +0900105
106/* Board Clock */
107#define CONFIG_SYS_CLK_FREQ 33333333
Nobuhiro Iwamatsue6984492013-08-21 16:11:21 +0900108#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
109#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
Jean-Christophe PLAGNIOL-VILLARD32e6acc2009-06-04 12:06:48 +0200110#define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */
goda.yusukefd768072008-01-25 20:46:36 +0900111
112#endif /* __MIGO_R_H */