blob: e52abd71a5a30ca013ed861b274cea9395c0a619 [file] [log] [blame]
Michal Simek04b7e622015-01-15 10:01:51 +01001/*
2 * (C) Copyright 2014 - 2015 Xilinx, Inc.
3 * Michal Simek <michal.simek@xilinx.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#ifndef _ASM_ARCH_SYS_PROTO_H
9#define _ASM_ARCH_SYS_PROTO_H
10
Siva Durga Prasad Paladugu0e39bd72017-02-02 01:10:46 +053011#define PAYLOAD_ARG_CNT 5
12
Siva Durga Prasad Paladugu9f0a8e92017-07-25 11:51:36 +053013#define ZYNQMP_CSU_SILICON_VER_MASK 0xF
14
15enum {
16 IDCODE,
17 VERSION,
18};
19
20enum {
21 ZYNQMP_SILICON_V1,
22 ZYNQMP_SILICON_V2,
23 ZYNQMP_SILICON_V3,
24 ZYNQMP_SILICON_V4,
25};
26
Siva Durga Prasad Paladugu5e2a9072017-07-13 19:01:09 +053027enum {
28 TCM_LOCK,
29 TCM_SPLIT,
30};
31
Michal Simekf2e373f2015-07-22 09:27:11 +020032int zynq_slcr_get_mio_pin_status(const char *periph);
Michal Simek04b7e622015-01-15 10:01:51 +010033
34unsigned int zynqmp_get_silicon_version(void);
35
Michal Simek72536fd2015-11-20 13:17:22 +010036void psu_init(void);
37
Michal Simek456e4542017-01-09 10:05:16 +010038void handoff_setup(void);
39
Michal Simek8b353302017-02-07 14:32:26 +010040void zynqmp_pmufw_version(void);
Siva Durga Prasad Paladugu0e39bd72017-02-02 01:10:46 +053041int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value);
42int zynqmp_mmio_read(const u32 address, u32 *value);
43int invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2, u32 arg3,
44 u32 *ret_payload);
45
Siva Durga Prasad Paladugu5e2a9072017-07-13 19:01:09 +053046void initialize_tcm(bool mode);
47
Siva Durga Prasad Paladugucd35d522017-07-25 11:51:38 +053048int chip_id(unsigned char id);
49
Michal Simek04b7e622015-01-15 10:01:51 +010050#endif /* _ASM_ARCH_SYS_PROTO_H */