Kunihiko Hayashi | 7dcdc22 | 2018-05-24 19:24:37 +0900 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /** |
| 3 | * sni_ave.c - Socionext UniPhier AVE ethernet driver |
| 4 | * Copyright 2016-2018 Socionext inc. |
| 5 | */ |
| 6 | |
| 7 | #include <clk.h> |
Simon Glass | 6333448 | 2019-11-14 12:57:39 -0700 | [diff] [blame] | 8 | #include <cpu_func.h> |
Kunihiko Hayashi | 7dcdc22 | 2018-05-24 19:24:37 +0900 | [diff] [blame] | 9 | #include <dm.h> |
| 10 | #include <fdt_support.h> |
| 11 | #include <linux/io.h> |
| 12 | #include <linux/iopoll.h> |
| 13 | #include <miiphy.h> |
| 14 | #include <net.h> |
| 15 | #include <regmap.h> |
| 16 | #include <reset.h> |
| 17 | #include <syscon.h> |
| 18 | |
| 19 | #define AVE_GRST_DELAY_MSEC 40 |
| 20 | #define AVE_MIN_XMITSIZE 60 |
| 21 | #define AVE_SEND_TIMEOUT_COUNT 1000 |
| 22 | #define AVE_MDIO_TIMEOUT_USEC 10000 |
| 23 | #define AVE_HALT_TIMEOUT_USEC 10000 |
| 24 | |
| 25 | /* General Register Group */ |
| 26 | #define AVE_IDR 0x000 /* ID */ |
| 27 | #define AVE_VR 0x004 /* Version */ |
| 28 | #define AVE_GRR 0x008 /* Global Reset */ |
| 29 | #define AVE_CFGR 0x00c /* Configuration */ |
| 30 | |
| 31 | /* Interrupt Register Group */ |
| 32 | #define AVE_GIMR 0x100 /* Global Interrupt Mask */ |
| 33 | #define AVE_GISR 0x104 /* Global Interrupt Status */ |
| 34 | |
| 35 | /* MAC Register Group */ |
| 36 | #define AVE_TXCR 0x200 /* TX Setup */ |
| 37 | #define AVE_RXCR 0x204 /* RX Setup */ |
| 38 | #define AVE_RXMAC1R 0x208 /* MAC address (lower) */ |
| 39 | #define AVE_RXMAC2R 0x20c /* MAC address (upper) */ |
| 40 | #define AVE_MDIOCTR 0x214 /* MDIO Control */ |
| 41 | #define AVE_MDIOAR 0x218 /* MDIO Address */ |
| 42 | #define AVE_MDIOWDR 0x21c /* MDIO Data */ |
| 43 | #define AVE_MDIOSR 0x220 /* MDIO Status */ |
| 44 | #define AVE_MDIORDR 0x224 /* MDIO Rd Data */ |
| 45 | |
| 46 | /* Descriptor Control Register Group */ |
| 47 | #define AVE_DESCC 0x300 /* Descriptor Control */ |
| 48 | #define AVE_TXDC 0x304 /* TX Descriptor Configuration */ |
| 49 | #define AVE_RXDC 0x308 /* RX Descriptor Ring0 Configuration */ |
| 50 | #define AVE_IIRQC 0x34c /* Interval IRQ Control */ |
| 51 | |
| 52 | /* 64bit descriptor memory */ |
| 53 | #define AVE_DESC_SIZE_64 12 /* Descriptor Size */ |
| 54 | #define AVE_TXDM_64 0x1000 /* Tx Descriptor Memory */ |
| 55 | #define AVE_RXDM_64 0x1c00 /* Rx Descriptor Memory */ |
| 56 | |
| 57 | /* 32bit descriptor memory */ |
| 58 | #define AVE_DESC_SIZE_32 8 /* Descriptor Size */ |
| 59 | #define AVE_TXDM_32 0x1000 /* Tx Descriptor Memory */ |
| 60 | #define AVE_RXDM_32 0x1800 /* Rx Descriptor Memory */ |
| 61 | |
| 62 | /* RMII Bridge Register Group */ |
| 63 | #define AVE_RSTCTRL 0x8028 /* Reset control */ |
| 64 | #define AVE_RSTCTRL_RMIIRST BIT(16) |
| 65 | #define AVE_LINKSEL 0x8034 /* Link speed setting */ |
| 66 | #define AVE_LINKSEL_100M BIT(0) |
| 67 | |
| 68 | /* AVE_GRR */ |
| 69 | #define AVE_GRR_PHYRST BIT(4) /* Reset external PHY */ |
| 70 | #define AVE_GRR_GRST BIT(0) /* Reset all MAC */ |
| 71 | |
| 72 | /* AVE_CFGR */ |
| 73 | #define AVE_CFGR_MII BIT(27) /* Func mode (1:MII/RMII, 0:RGMII) */ |
| 74 | |
| 75 | /* AVE_GISR (common with GIMR) */ |
| 76 | #define AVE_GIMR_CLR 0 |
| 77 | #define AVE_GISR_CLR GENMASK(31, 0) |
| 78 | |
| 79 | /* AVE_TXCR */ |
| 80 | #define AVE_TXCR_FLOCTR BIT(18) /* Flow control */ |
| 81 | #define AVE_TXCR_TXSPD_1G BIT(17) |
| 82 | #define AVE_TXCR_TXSPD_100 BIT(16) |
| 83 | |
| 84 | /* AVE_RXCR */ |
| 85 | #define AVE_RXCR_RXEN BIT(30) /* Rx enable */ |
| 86 | #define AVE_RXCR_FDUPEN BIT(22) /* Interface mode */ |
| 87 | #define AVE_RXCR_FLOCTR BIT(21) /* Flow control */ |
| 88 | |
| 89 | /* AVE_MDIOCTR */ |
| 90 | #define AVE_MDIOCTR_RREQ BIT(3) /* Read request */ |
| 91 | #define AVE_MDIOCTR_WREQ BIT(2) /* Write request */ |
| 92 | |
| 93 | /* AVE_MDIOSR */ |
| 94 | #define AVE_MDIOSR_STS BIT(0) /* access status */ |
| 95 | |
| 96 | /* AVE_DESCC */ |
| 97 | #define AVE_DESCC_RXDSTPSTS BIT(20) |
| 98 | #define AVE_DESCC_RD0 BIT(8) /* Enable Rx descriptor Ring0 */ |
| 99 | #define AVE_DESCC_RXDSTP BIT(4) /* Pause Rx descriptor */ |
| 100 | #define AVE_DESCC_TD BIT(0) /* Enable Tx descriptor */ |
| 101 | |
| 102 | /* AVE_TXDC/RXDC */ |
| 103 | #define AVE_DESC_SIZE(priv, num) \ |
| 104 | ((num) * ((priv)->data->is_desc_64bit ? AVE_DESC_SIZE_64 : \ |
| 105 | AVE_DESC_SIZE_32)) |
| 106 | |
| 107 | /* Command status for descriptor */ |
| 108 | #define AVE_STS_OWN BIT(31) /* Descriptor ownership */ |
| 109 | #define AVE_STS_OK BIT(27) /* Normal transmit */ |
| 110 | #define AVE_STS_1ST BIT(26) /* Head of buffer chain */ |
| 111 | #define AVE_STS_LAST BIT(25) /* Tail of buffer chain */ |
| 112 | #define AVE_STS_PKTLEN_TX_MASK GENMASK(15, 0) |
| 113 | #define AVE_STS_PKTLEN_RX_MASK GENMASK(10, 0) |
| 114 | |
| 115 | #define AVE_DESC_OFS_CMDSTS 0 |
| 116 | #define AVE_DESC_OFS_ADDRL 4 |
| 117 | #define AVE_DESC_OFS_ADDRU 8 |
| 118 | |
| 119 | /* Parameter for ethernet frame */ |
| 120 | #define AVE_RXCR_MTU 1518 |
| 121 | |
| 122 | /* SG */ |
| 123 | #define SG_ETPINMODE 0x540 |
| 124 | #define SG_ETPINMODE_EXTPHY BIT(1) /* for LD11 */ |
| 125 | #define SG_ETPINMODE_RMII(ins) BIT(ins) |
| 126 | |
| 127 | #define AVE_MAX_CLKS 4 |
| 128 | #define AVE_MAX_RSTS 2 |
| 129 | |
| 130 | enum desc_id { |
| 131 | AVE_DESCID_TX, |
| 132 | AVE_DESCID_RX, |
| 133 | }; |
| 134 | |
| 135 | struct ave_private { |
| 136 | phys_addr_t iobase; |
| 137 | unsigned int nclks; |
| 138 | struct clk clk[AVE_MAX_CLKS]; |
| 139 | unsigned int nrsts; |
| 140 | struct reset_ctl rst[AVE_MAX_RSTS]; |
| 141 | struct regmap *regmap; |
| 142 | unsigned int regmap_arg; |
| 143 | |
| 144 | struct mii_dev *bus; |
| 145 | struct phy_device *phydev; |
| 146 | int phy_mode; |
| 147 | int max_speed; |
| 148 | |
| 149 | int rx_pos; |
| 150 | int rx_siz; |
| 151 | int rx_off; |
| 152 | int tx_num; |
| 153 | |
| 154 | u8 tx_adj_packetbuf[PKTSIZE_ALIGN + PKTALIGN]; |
| 155 | void *tx_adj_buf; |
| 156 | |
| 157 | const struct ave_soc_data *data; |
| 158 | }; |
| 159 | |
| 160 | struct ave_soc_data { |
| 161 | bool is_desc_64bit; |
| 162 | const char *clock_names[AVE_MAX_CLKS]; |
| 163 | const char *reset_names[AVE_MAX_RSTS]; |
| 164 | int (*get_pinmode)(struct ave_private *priv); |
| 165 | }; |
| 166 | |
| 167 | static u32 ave_desc_read(struct ave_private *priv, enum desc_id id, int entry, |
| 168 | int offset) |
| 169 | { |
| 170 | int desc_size; |
| 171 | u32 addr; |
| 172 | |
| 173 | if (priv->data->is_desc_64bit) { |
| 174 | desc_size = AVE_DESC_SIZE_64; |
| 175 | addr = (id == AVE_DESCID_TX) ? AVE_TXDM_64 : AVE_RXDM_64; |
| 176 | } else { |
| 177 | desc_size = AVE_DESC_SIZE_32; |
| 178 | addr = (id == AVE_DESCID_TX) ? AVE_TXDM_32 : AVE_RXDM_32; |
| 179 | } |
| 180 | |
| 181 | addr += entry * desc_size + offset; |
| 182 | |
| 183 | return readl(priv->iobase + addr); |
| 184 | } |
| 185 | |
| 186 | static u32 ave_desc_read_cmdsts(struct ave_private *priv, enum desc_id id, |
| 187 | int entry) |
| 188 | { |
| 189 | return ave_desc_read(priv, id, entry, AVE_DESC_OFS_CMDSTS); |
| 190 | } |
| 191 | |
| 192 | static void ave_desc_write(struct ave_private *priv, enum desc_id id, |
| 193 | int entry, int offset, u32 val) |
| 194 | { |
| 195 | int desc_size; |
| 196 | u32 addr; |
| 197 | |
| 198 | if (priv->data->is_desc_64bit) { |
| 199 | desc_size = AVE_DESC_SIZE_64; |
| 200 | addr = (id == AVE_DESCID_TX) ? AVE_TXDM_64 : AVE_RXDM_64; |
| 201 | } else { |
| 202 | desc_size = AVE_DESC_SIZE_32; |
| 203 | addr = (id == AVE_DESCID_TX) ? AVE_TXDM_32 : AVE_RXDM_32; |
| 204 | } |
| 205 | |
| 206 | addr += entry * desc_size + offset; |
| 207 | writel(val, priv->iobase + addr); |
| 208 | } |
| 209 | |
| 210 | static void ave_desc_write_cmdsts(struct ave_private *priv, enum desc_id id, |
| 211 | int entry, u32 val) |
| 212 | { |
| 213 | ave_desc_write(priv, id, entry, AVE_DESC_OFS_CMDSTS, val); |
| 214 | } |
| 215 | |
| 216 | static void ave_desc_write_addr(struct ave_private *priv, enum desc_id id, |
| 217 | int entry, uintptr_t paddr) |
| 218 | { |
| 219 | ave_desc_write(priv, id, entry, |
| 220 | AVE_DESC_OFS_ADDRL, lower_32_bits(paddr)); |
| 221 | if (priv->data->is_desc_64bit) |
| 222 | ave_desc_write(priv, id, entry, |
| 223 | AVE_DESC_OFS_ADDRU, upper_32_bits(paddr)); |
| 224 | } |
| 225 | |
| 226 | static void ave_cache_invalidate(uintptr_t vaddr, int len) |
| 227 | { |
| 228 | invalidate_dcache_range(rounddown(vaddr, ARCH_DMA_MINALIGN), |
| 229 | roundup(vaddr + len, ARCH_DMA_MINALIGN)); |
| 230 | } |
| 231 | |
| 232 | static void ave_cache_flush(uintptr_t vaddr, int len) |
| 233 | { |
| 234 | flush_dcache_range(rounddown(vaddr, ARCH_DMA_MINALIGN), |
| 235 | roundup(vaddr + len, ARCH_DMA_MINALIGN)); |
| 236 | } |
| 237 | |
| 238 | static int ave_mdiobus_read(struct mii_dev *bus, |
| 239 | int phyid, int devad, int regnum) |
| 240 | { |
| 241 | struct ave_private *priv = bus->priv; |
| 242 | u32 mdioctl, mdiosr; |
| 243 | int ret; |
| 244 | |
| 245 | /* write address */ |
| 246 | writel((phyid << 8) | regnum, priv->iobase + AVE_MDIOAR); |
| 247 | |
| 248 | /* read request */ |
| 249 | mdioctl = readl(priv->iobase + AVE_MDIOCTR); |
| 250 | writel(mdioctl | AVE_MDIOCTR_RREQ, priv->iobase + AVE_MDIOCTR); |
| 251 | |
| 252 | ret = readl_poll_timeout(priv->iobase + AVE_MDIOSR, mdiosr, |
| 253 | !(mdiosr & AVE_MDIOSR_STS), |
| 254 | AVE_MDIO_TIMEOUT_USEC); |
| 255 | if (ret) { |
| 256 | pr_err("%s: failed to read from mdio (phy:%d reg:%x)\n", |
| 257 | priv->phydev->dev->name, phyid, regnum); |
| 258 | return ret; |
| 259 | } |
| 260 | |
| 261 | return readl(priv->iobase + AVE_MDIORDR) & GENMASK(15, 0); |
| 262 | } |
| 263 | |
| 264 | static int ave_mdiobus_write(struct mii_dev *bus, |
| 265 | int phyid, int devad, int regnum, u16 val) |
| 266 | { |
| 267 | struct ave_private *priv = bus->priv; |
| 268 | u32 mdioctl, mdiosr; |
| 269 | int ret; |
| 270 | |
| 271 | /* write address */ |
| 272 | writel((phyid << 8) | regnum, priv->iobase + AVE_MDIOAR); |
| 273 | |
| 274 | /* write data */ |
| 275 | writel(val, priv->iobase + AVE_MDIOWDR); |
| 276 | |
| 277 | /* write request */ |
| 278 | mdioctl = readl(priv->iobase + AVE_MDIOCTR); |
| 279 | writel((mdioctl | AVE_MDIOCTR_WREQ) & ~AVE_MDIOCTR_RREQ, |
| 280 | priv->iobase + AVE_MDIOCTR); |
| 281 | |
| 282 | ret = readl_poll_timeout(priv->iobase + AVE_MDIOSR, mdiosr, |
| 283 | !(mdiosr & AVE_MDIOSR_STS), |
| 284 | AVE_MDIO_TIMEOUT_USEC); |
| 285 | if (ret) |
| 286 | pr_err("%s: failed to write to mdio (phy:%d reg:%x)\n", |
| 287 | priv->phydev->dev->name, phyid, regnum); |
| 288 | |
| 289 | return ret; |
| 290 | } |
| 291 | |
| 292 | static int ave_adjust_link(struct ave_private *priv) |
| 293 | { |
| 294 | struct phy_device *phydev = priv->phydev; |
| 295 | struct eth_pdata *pdata = dev_get_platdata(phydev->dev); |
| 296 | u32 val, txcr, rxcr, rxcr_org; |
| 297 | u16 rmt_adv = 0, lcl_adv = 0; |
| 298 | u8 cap; |
| 299 | |
| 300 | /* set RGMII speed */ |
| 301 | val = readl(priv->iobase + AVE_TXCR); |
| 302 | val &= ~(AVE_TXCR_TXSPD_100 | AVE_TXCR_TXSPD_1G); |
| 303 | |
| 304 | if (phy_interface_is_rgmii(phydev) && phydev->speed == SPEED_1000) |
| 305 | val |= AVE_TXCR_TXSPD_1G; |
| 306 | else if (phydev->speed == SPEED_100) |
| 307 | val |= AVE_TXCR_TXSPD_100; |
| 308 | |
| 309 | writel(val, priv->iobase + AVE_TXCR); |
| 310 | |
| 311 | /* set RMII speed (100M/10M only) */ |
| 312 | if (!phy_interface_is_rgmii(phydev)) { |
| 313 | val = readl(priv->iobase + AVE_LINKSEL); |
| 314 | if (phydev->speed == SPEED_10) |
| 315 | val &= ~AVE_LINKSEL_100M; |
| 316 | else |
| 317 | val |= AVE_LINKSEL_100M; |
| 318 | writel(val, priv->iobase + AVE_LINKSEL); |
| 319 | } |
| 320 | |
| 321 | /* check current RXCR/TXCR */ |
| 322 | rxcr = readl(priv->iobase + AVE_RXCR); |
| 323 | txcr = readl(priv->iobase + AVE_TXCR); |
| 324 | rxcr_org = rxcr; |
| 325 | |
| 326 | if (phydev->duplex) { |
| 327 | rxcr |= AVE_RXCR_FDUPEN; |
| 328 | |
| 329 | if (phydev->pause) |
| 330 | rmt_adv |= LPA_PAUSE_CAP; |
| 331 | if (phydev->asym_pause) |
| 332 | rmt_adv |= LPA_PAUSE_ASYM; |
| 333 | if (phydev->advertising & ADVERTISED_Pause) |
| 334 | lcl_adv |= ADVERTISE_PAUSE_CAP; |
| 335 | if (phydev->advertising & ADVERTISED_Asym_Pause) |
| 336 | lcl_adv |= ADVERTISE_PAUSE_ASYM; |
| 337 | |
| 338 | cap = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv); |
| 339 | if (cap & FLOW_CTRL_TX) |
| 340 | txcr |= AVE_TXCR_FLOCTR; |
| 341 | else |
| 342 | txcr &= ~AVE_TXCR_FLOCTR; |
| 343 | if (cap & FLOW_CTRL_RX) |
| 344 | rxcr |= AVE_RXCR_FLOCTR; |
| 345 | else |
| 346 | rxcr &= ~AVE_RXCR_FLOCTR; |
| 347 | } else { |
| 348 | rxcr &= ~AVE_RXCR_FDUPEN; |
| 349 | rxcr &= ~AVE_RXCR_FLOCTR; |
| 350 | txcr &= ~AVE_TXCR_FLOCTR; |
| 351 | } |
| 352 | |
| 353 | if (rxcr_org != rxcr) { |
| 354 | /* disable Rx mac */ |
| 355 | writel(rxcr & ~AVE_RXCR_RXEN, priv->iobase + AVE_RXCR); |
| 356 | /* change and enable TX/Rx mac */ |
| 357 | writel(txcr, priv->iobase + AVE_TXCR); |
| 358 | writel(rxcr, priv->iobase + AVE_RXCR); |
| 359 | } |
| 360 | |
| 361 | pr_notice("%s: phy:%s speed:%d mac:%pM\n", |
| 362 | phydev->dev->name, phydev->drv->name, phydev->speed, |
| 363 | pdata->enetaddr); |
| 364 | |
| 365 | return phydev->link; |
| 366 | } |
| 367 | |
| 368 | static int ave_mdiobus_init(struct ave_private *priv, const char *name) |
| 369 | { |
| 370 | struct mii_dev *bus = mdio_alloc(); |
| 371 | |
| 372 | if (!bus) |
| 373 | return -ENOMEM; |
| 374 | |
| 375 | bus->read = ave_mdiobus_read; |
| 376 | bus->write = ave_mdiobus_write; |
| 377 | snprintf(bus->name, sizeof(bus->name), "%s", name); |
| 378 | bus->priv = priv; |
| 379 | |
| 380 | return mdio_register(bus); |
| 381 | } |
| 382 | |
| 383 | static int ave_phy_init(struct ave_private *priv, void *dev) |
| 384 | { |
| 385 | struct phy_device *phydev; |
| 386 | int mask = GENMASK(31, 0), ret; |
| 387 | |
| 388 | phydev = phy_find_by_mask(priv->bus, mask, priv->phy_mode); |
| 389 | if (!phydev) |
| 390 | return -ENODEV; |
| 391 | |
| 392 | phy_connect_dev(phydev, dev); |
| 393 | |
| 394 | phydev->supported &= PHY_GBIT_FEATURES; |
| 395 | if (priv->max_speed) { |
| 396 | ret = phy_set_supported(phydev, priv->max_speed); |
| 397 | if (ret) |
| 398 | return ret; |
| 399 | } |
| 400 | phydev->advertising = phydev->supported; |
| 401 | |
| 402 | priv->phydev = phydev; |
| 403 | phy_config(phydev); |
| 404 | |
| 405 | return 0; |
| 406 | } |
| 407 | |
| 408 | static void ave_stop(struct udevice *dev) |
| 409 | { |
| 410 | struct ave_private *priv = dev_get_priv(dev); |
| 411 | u32 val; |
| 412 | int ret; |
| 413 | |
| 414 | val = readl(priv->iobase + AVE_GRR); |
| 415 | if (val) |
| 416 | return; |
| 417 | |
| 418 | val = readl(priv->iobase + AVE_RXCR); |
| 419 | val &= ~AVE_RXCR_RXEN; |
| 420 | writel(val, priv->iobase + AVE_RXCR); |
| 421 | |
| 422 | writel(0, priv->iobase + AVE_DESCC); |
| 423 | ret = readl_poll_timeout(priv->iobase + AVE_DESCC, val, !val, |
| 424 | AVE_HALT_TIMEOUT_USEC); |
| 425 | if (ret) |
| 426 | pr_warn("%s: halt timeout\n", priv->phydev->dev->name); |
| 427 | |
| 428 | writel(AVE_GRR_GRST, priv->iobase + AVE_GRR); |
| 429 | |
| 430 | phy_shutdown(priv->phydev); |
| 431 | } |
| 432 | |
| 433 | static void ave_reset(struct ave_private *priv) |
| 434 | { |
| 435 | u32 val; |
| 436 | |
| 437 | /* reset RMII register */ |
| 438 | val = readl(priv->iobase + AVE_RSTCTRL); |
| 439 | val &= ~AVE_RSTCTRL_RMIIRST; |
| 440 | writel(val, priv->iobase + AVE_RSTCTRL); |
| 441 | |
| 442 | /* assert reset */ |
| 443 | writel(AVE_GRR_GRST | AVE_GRR_PHYRST, priv->iobase + AVE_GRR); |
| 444 | mdelay(AVE_GRST_DELAY_MSEC); |
| 445 | |
| 446 | /* 1st, negate PHY reset only */ |
| 447 | writel(AVE_GRR_GRST, priv->iobase + AVE_GRR); |
| 448 | mdelay(AVE_GRST_DELAY_MSEC); |
| 449 | |
| 450 | /* negate reset */ |
| 451 | writel(0, priv->iobase + AVE_GRR); |
| 452 | mdelay(AVE_GRST_DELAY_MSEC); |
| 453 | |
| 454 | /* negate RMII register */ |
| 455 | val = readl(priv->iobase + AVE_RSTCTRL); |
| 456 | val |= AVE_RSTCTRL_RMIIRST; |
| 457 | writel(val, priv->iobase + AVE_RSTCTRL); |
| 458 | } |
| 459 | |
| 460 | static int ave_start(struct udevice *dev) |
| 461 | { |
| 462 | struct ave_private *priv = dev_get_priv(dev); |
| 463 | uintptr_t paddr; |
| 464 | u32 val; |
| 465 | int i; |
| 466 | |
| 467 | ave_reset(priv); |
| 468 | |
| 469 | priv->rx_pos = 0; |
| 470 | priv->rx_off = 2; /* RX data has 2byte offsets */ |
| 471 | priv->tx_num = 0; |
| 472 | priv->tx_adj_buf = |
| 473 | (void *)roundup((uintptr_t)&priv->tx_adj_packetbuf[0], |
| 474 | PKTALIGN); |
| 475 | priv->rx_siz = (PKTSIZE_ALIGN - priv->rx_off); |
| 476 | |
| 477 | val = 0; |
| 478 | if (priv->phy_mode != PHY_INTERFACE_MODE_RGMII) |
| 479 | val |= AVE_CFGR_MII; |
| 480 | writel(val, priv->iobase + AVE_CFGR); |
| 481 | |
| 482 | /* use one descriptor for Tx */ |
| 483 | writel(AVE_DESC_SIZE(priv, 1) << 16, priv->iobase + AVE_TXDC); |
| 484 | ave_desc_write_cmdsts(priv, AVE_DESCID_TX, 0, 0); |
| 485 | ave_desc_write_addr(priv, AVE_DESCID_TX, 0, 0); |
| 486 | |
| 487 | /* use PKTBUFSRX descriptors for Rx */ |
| 488 | writel(AVE_DESC_SIZE(priv, PKTBUFSRX) << 16, priv->iobase + AVE_RXDC); |
| 489 | for (i = 0; i < PKTBUFSRX; i++) { |
| 490 | paddr = (uintptr_t)net_rx_packets[i]; |
| 491 | ave_cache_flush(paddr, priv->rx_siz + priv->rx_off); |
| 492 | ave_desc_write_addr(priv, AVE_DESCID_RX, i, paddr); |
| 493 | ave_desc_write_cmdsts(priv, AVE_DESCID_RX, i, priv->rx_siz); |
| 494 | } |
| 495 | |
| 496 | writel(AVE_GISR_CLR, priv->iobase + AVE_GISR); |
| 497 | writel(AVE_GIMR_CLR, priv->iobase + AVE_GIMR); |
| 498 | |
| 499 | writel(AVE_RXCR_RXEN | AVE_RXCR_FDUPEN | AVE_RXCR_FLOCTR | AVE_RXCR_MTU, |
| 500 | priv->iobase + AVE_RXCR); |
| 501 | writel(AVE_DESCC_RD0 | AVE_DESCC_TD, priv->iobase + AVE_DESCC); |
| 502 | |
| 503 | phy_startup(priv->phydev); |
| 504 | ave_adjust_link(priv); |
| 505 | |
| 506 | return 0; |
| 507 | } |
| 508 | |
| 509 | static int ave_write_hwaddr(struct udevice *dev) |
| 510 | { |
| 511 | struct ave_private *priv = dev_get_priv(dev); |
| 512 | struct eth_pdata *pdata = dev_get_platdata(dev); |
| 513 | u8 *mac = pdata->enetaddr; |
| 514 | |
| 515 | writel(mac[0] | mac[1] << 8 | mac[2] << 16 | mac[3] << 24, |
| 516 | priv->iobase + AVE_RXMAC1R); |
| 517 | writel(mac[4] | mac[5] << 8, priv->iobase + AVE_RXMAC2R); |
| 518 | |
| 519 | return 0; |
| 520 | } |
| 521 | |
| 522 | static int ave_send(struct udevice *dev, void *packet, int length) |
| 523 | { |
| 524 | struct ave_private *priv = dev_get_priv(dev); |
| 525 | u32 val; |
| 526 | void *ptr = packet; |
| 527 | int count; |
| 528 | |
| 529 | /* adjust alignment for descriptor */ |
| 530 | if ((uintptr_t)ptr & 0x3) { |
| 531 | memcpy(priv->tx_adj_buf, (const void *)ptr, length); |
| 532 | ptr = priv->tx_adj_buf; |
| 533 | } |
| 534 | |
| 535 | /* padding for minimum length */ |
| 536 | if (length < AVE_MIN_XMITSIZE) { |
| 537 | memset(ptr + length, 0, AVE_MIN_XMITSIZE - length); |
| 538 | length = AVE_MIN_XMITSIZE; |
| 539 | } |
| 540 | |
| 541 | /* check ownership and wait for previous xmit done */ |
| 542 | count = AVE_SEND_TIMEOUT_COUNT; |
| 543 | do { |
| 544 | val = ave_desc_read_cmdsts(priv, AVE_DESCID_TX, 0); |
| 545 | } while ((val & AVE_STS_OWN) && --count); |
| 546 | if (!count) |
| 547 | return -ETIMEDOUT; |
| 548 | |
| 549 | ave_cache_flush((uintptr_t)ptr, length); |
| 550 | ave_desc_write_addr(priv, AVE_DESCID_TX, 0, (uintptr_t)ptr); |
| 551 | |
| 552 | val = AVE_STS_OWN | AVE_STS_1ST | AVE_STS_LAST | |
| 553 | (length & AVE_STS_PKTLEN_TX_MASK); |
| 554 | ave_desc_write_cmdsts(priv, AVE_DESCID_TX, 0, val); |
| 555 | priv->tx_num++; |
| 556 | |
| 557 | count = AVE_SEND_TIMEOUT_COUNT; |
| 558 | do { |
| 559 | val = ave_desc_read_cmdsts(priv, AVE_DESCID_TX, 0); |
| 560 | } while ((val & AVE_STS_OWN) && --count); |
| 561 | if (!count) |
| 562 | return -ETIMEDOUT; |
| 563 | |
| 564 | if (!(val & AVE_STS_OK)) |
| 565 | pr_warn("%s: bad send packet status:%08x\n", |
| 566 | priv->phydev->dev->name, le32_to_cpu(val)); |
| 567 | |
| 568 | return 0; |
| 569 | } |
| 570 | |
| 571 | static int ave_recv(struct udevice *dev, int flags, uchar **packetp) |
| 572 | { |
| 573 | struct ave_private *priv = dev_get_priv(dev); |
| 574 | uchar *ptr; |
| 575 | int length = 0; |
| 576 | u32 cmdsts; |
| 577 | |
| 578 | while (1) { |
| 579 | cmdsts = ave_desc_read_cmdsts(priv, AVE_DESCID_RX, |
| 580 | priv->rx_pos); |
| 581 | if (!(cmdsts & AVE_STS_OWN)) |
| 582 | /* hardware ownership, no received packets */ |
| 583 | return -EAGAIN; |
| 584 | |
| 585 | ptr = net_rx_packets[priv->rx_pos] + priv->rx_off; |
| 586 | if (cmdsts & AVE_STS_OK) |
| 587 | break; |
| 588 | |
| 589 | pr_warn("%s: bad packet[%d] status:%08x ptr:%p\n", |
| 590 | priv->phydev->dev->name, priv->rx_pos, |
| 591 | le32_to_cpu(cmdsts), ptr); |
| 592 | } |
| 593 | |
| 594 | length = cmdsts & AVE_STS_PKTLEN_RX_MASK; |
| 595 | |
| 596 | /* invalidate after DMA is done */ |
| 597 | ave_cache_invalidate((uintptr_t)ptr, length); |
| 598 | *packetp = ptr; |
| 599 | |
| 600 | return length; |
| 601 | } |
| 602 | |
| 603 | static int ave_free_packet(struct udevice *dev, uchar *packet, int length) |
| 604 | { |
| 605 | struct ave_private *priv = dev_get_priv(dev); |
| 606 | |
| 607 | ave_cache_flush((uintptr_t)net_rx_packets[priv->rx_pos], |
| 608 | priv->rx_siz + priv->rx_off); |
| 609 | |
| 610 | ave_desc_write_cmdsts(priv, AVE_DESCID_RX, |
| 611 | priv->rx_pos, priv->rx_siz); |
| 612 | |
| 613 | if (++priv->rx_pos >= PKTBUFSRX) |
| 614 | priv->rx_pos = 0; |
| 615 | |
| 616 | return 0; |
| 617 | } |
| 618 | |
| 619 | static int ave_pro4_get_pinmode(struct ave_private *priv) |
| 620 | { |
| 621 | u32 reg, mask, val = 0; |
| 622 | |
| 623 | if (priv->regmap_arg > 0) |
| 624 | return -EINVAL; |
| 625 | |
| 626 | mask = SG_ETPINMODE_RMII(0); |
| 627 | |
| 628 | switch (priv->phy_mode) { |
| 629 | case PHY_INTERFACE_MODE_RMII: |
| 630 | val = SG_ETPINMODE_RMII(0); |
| 631 | break; |
| 632 | case PHY_INTERFACE_MODE_MII: |
| 633 | case PHY_INTERFACE_MODE_RGMII: |
| 634 | break; |
| 635 | default: |
| 636 | return -EINVAL; |
| 637 | } |
| 638 | |
| 639 | regmap_read(priv->regmap, SG_ETPINMODE, ®); |
| 640 | reg &= ~mask; |
| 641 | reg |= val; |
| 642 | regmap_write(priv->regmap, SG_ETPINMODE, reg); |
| 643 | |
| 644 | return 0; |
| 645 | } |
| 646 | |
| 647 | static int ave_ld11_get_pinmode(struct ave_private *priv) |
| 648 | { |
| 649 | u32 reg, mask, val = 0; |
| 650 | |
| 651 | if (priv->regmap_arg > 0) |
| 652 | return -EINVAL; |
| 653 | |
| 654 | mask = SG_ETPINMODE_EXTPHY | SG_ETPINMODE_RMII(0); |
| 655 | |
| 656 | switch (priv->phy_mode) { |
| 657 | case PHY_INTERFACE_MODE_INTERNAL: |
| 658 | break; |
| 659 | case PHY_INTERFACE_MODE_RMII: |
| 660 | val = SG_ETPINMODE_EXTPHY | SG_ETPINMODE_RMII(0); |
| 661 | break; |
| 662 | default: |
| 663 | return -EINVAL; |
| 664 | } |
| 665 | |
| 666 | regmap_read(priv->regmap, SG_ETPINMODE, ®); |
| 667 | reg &= ~mask; |
| 668 | reg |= val; |
| 669 | regmap_write(priv->regmap, SG_ETPINMODE, reg); |
| 670 | |
| 671 | return 0; |
| 672 | } |
| 673 | |
| 674 | static int ave_ld20_get_pinmode(struct ave_private *priv) |
| 675 | { |
| 676 | u32 reg, mask, val = 0; |
| 677 | |
| 678 | if (priv->regmap_arg > 0) |
| 679 | return -EINVAL; |
| 680 | |
| 681 | mask = SG_ETPINMODE_RMII(0); |
| 682 | |
| 683 | switch (priv->phy_mode) { |
| 684 | case PHY_INTERFACE_MODE_RMII: |
| 685 | val = SG_ETPINMODE_RMII(0); |
| 686 | break; |
| 687 | case PHY_INTERFACE_MODE_RGMII: |
| 688 | break; |
| 689 | default: |
| 690 | return -EINVAL; |
| 691 | } |
| 692 | |
| 693 | regmap_read(priv->regmap, SG_ETPINMODE, ®); |
| 694 | reg &= ~mask; |
| 695 | reg |= val; |
| 696 | regmap_write(priv->regmap, SG_ETPINMODE, reg); |
| 697 | |
| 698 | return 0; |
| 699 | } |
| 700 | |
| 701 | static int ave_pxs3_get_pinmode(struct ave_private *priv) |
| 702 | { |
| 703 | u32 reg, mask, val = 0; |
| 704 | |
| 705 | if (priv->regmap_arg > 1) |
| 706 | return -EINVAL; |
| 707 | |
| 708 | mask = SG_ETPINMODE_RMII(priv->regmap_arg); |
| 709 | |
| 710 | switch (priv->phy_mode) { |
| 711 | case PHY_INTERFACE_MODE_RMII: |
| 712 | val = SG_ETPINMODE_RMII(priv->regmap_arg); |
| 713 | break; |
| 714 | case PHY_INTERFACE_MODE_RGMII: |
| 715 | break; |
| 716 | default: |
| 717 | return -EINVAL; |
| 718 | } |
| 719 | |
| 720 | regmap_read(priv->regmap, SG_ETPINMODE, ®); |
| 721 | reg &= ~mask; |
| 722 | reg |= val; |
| 723 | regmap_write(priv->regmap, SG_ETPINMODE, reg); |
| 724 | |
| 725 | return 0; |
| 726 | } |
| 727 | |
| 728 | static int ave_ofdata_to_platdata(struct udevice *dev) |
| 729 | { |
| 730 | struct eth_pdata *pdata = dev_get_platdata(dev); |
| 731 | struct ave_private *priv = dev_get_priv(dev); |
| 732 | struct ofnode_phandle_args args; |
| 733 | const char *phy_mode; |
| 734 | const u32 *valp; |
| 735 | int ret, nc, nr; |
| 736 | const char *name; |
| 737 | |
| 738 | priv->data = (const struct ave_soc_data *)dev_get_driver_data(dev); |
| 739 | if (!priv->data) |
| 740 | return -EINVAL; |
| 741 | |
| 742 | pdata->iobase = devfdt_get_addr(dev); |
| 743 | pdata->phy_interface = -1; |
| 744 | phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode", |
| 745 | NULL); |
| 746 | if (phy_mode) |
| 747 | pdata->phy_interface = phy_get_interface_by_name(phy_mode); |
| 748 | if (pdata->phy_interface == -1) { |
| 749 | dev_err(dev, "Invalid PHY interface '%s'\n", phy_mode); |
| 750 | return -EINVAL; |
| 751 | } |
| 752 | |
| 753 | pdata->max_speed = 0; |
| 754 | valp = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", |
| 755 | NULL); |
| 756 | if (valp) |
| 757 | pdata->max_speed = fdt32_to_cpu(*valp); |
| 758 | |
| 759 | for (nc = 0; nc < AVE_MAX_CLKS; nc++) { |
| 760 | name = priv->data->clock_names[nc]; |
| 761 | if (!name) |
| 762 | break; |
| 763 | ret = clk_get_by_name(dev, name, &priv->clk[nc]); |
| 764 | if (ret) { |
| 765 | dev_err(dev, "Failed to get clocks property: %d\n", |
| 766 | ret); |
| 767 | goto out_clk_free; |
| 768 | } |
| 769 | priv->nclks++; |
| 770 | } |
| 771 | |
| 772 | for (nr = 0; nr < AVE_MAX_RSTS; nr++) { |
| 773 | name = priv->data->reset_names[nr]; |
| 774 | if (!name) |
| 775 | break; |
| 776 | ret = reset_get_by_name(dev, name, &priv->rst[nr]); |
| 777 | if (ret) { |
| 778 | dev_err(dev, "Failed to get resets property: %d\n", |
| 779 | ret); |
| 780 | goto out_reset_free; |
| 781 | } |
| 782 | priv->nrsts++; |
| 783 | } |
| 784 | |
| 785 | ret = dev_read_phandle_with_args(dev, "socionext,syscon-phy-mode", |
| 786 | NULL, 1, 0, &args); |
| 787 | if (ret) { |
| 788 | dev_err(dev, "Failed to get syscon-phy-mode property: %d\n", |
| 789 | ret); |
| 790 | goto out_reset_free; |
| 791 | } |
| 792 | |
| 793 | priv->regmap = syscon_node_to_regmap(args.node); |
| 794 | if (IS_ERR(priv->regmap)) { |
| 795 | ret = PTR_ERR(priv->regmap); |
| 796 | dev_err(dev, "can't get syscon: %d\n", ret); |
| 797 | goto out_reset_free; |
| 798 | } |
| 799 | |
| 800 | if (args.args_count != 1) { |
| 801 | ret = -EINVAL; |
| 802 | dev_err(dev, "Invalid argument of syscon-phy-mode\n"); |
| 803 | goto out_reset_free; |
| 804 | } |
| 805 | |
| 806 | priv->regmap_arg = args.args[0]; |
| 807 | |
| 808 | return 0; |
| 809 | |
| 810 | out_reset_free: |
| 811 | while (--nr >= 0) |
| 812 | reset_free(&priv->rst[nr]); |
| 813 | out_clk_free: |
| 814 | while (--nc >= 0) |
| 815 | clk_free(&priv->clk[nc]); |
| 816 | |
| 817 | return ret; |
| 818 | } |
| 819 | |
| 820 | static int ave_probe(struct udevice *dev) |
| 821 | { |
| 822 | struct eth_pdata *pdata = dev_get_platdata(dev); |
| 823 | struct ave_private *priv = dev_get_priv(dev); |
| 824 | int ret, nc, nr; |
| 825 | |
| 826 | priv->data = (const struct ave_soc_data *)dev_get_driver_data(dev); |
| 827 | if (!priv->data) |
| 828 | return -EINVAL; |
| 829 | |
| 830 | priv->iobase = pdata->iobase; |
| 831 | priv->phy_mode = pdata->phy_interface; |
| 832 | priv->max_speed = pdata->max_speed; |
| 833 | |
| 834 | ret = priv->data->get_pinmode(priv); |
| 835 | if (ret) { |
| 836 | dev_err(dev, "Invalid phy-mode\n"); |
| 837 | return -EINVAL; |
| 838 | } |
| 839 | |
| 840 | for (nc = 0; nc < priv->nclks; nc++) { |
| 841 | ret = clk_enable(&priv->clk[nc]); |
| 842 | if (ret) { |
| 843 | dev_err(dev, "Failed to enable clk: %d\n", ret); |
| 844 | goto out_clk_release; |
| 845 | } |
| 846 | } |
| 847 | |
| 848 | for (nr = 0; nr < priv->nrsts; nr++) { |
| 849 | ret = reset_deassert(&priv->rst[nr]); |
| 850 | if (ret) { |
| 851 | dev_err(dev, "Failed to deassert reset: %d\n", ret); |
| 852 | goto out_reset_release; |
| 853 | } |
| 854 | } |
| 855 | |
| 856 | ave_reset(priv); |
| 857 | |
| 858 | ret = ave_mdiobus_init(priv, dev->name); |
| 859 | if (ret) { |
| 860 | dev_err(dev, "Failed to initialize mdiobus: %d\n", ret); |
| 861 | goto out_reset_release; |
| 862 | } |
| 863 | |
| 864 | priv->bus = miiphy_get_dev_by_name(dev->name); |
| 865 | |
| 866 | ret = ave_phy_init(priv, dev); |
| 867 | if (ret) { |
| 868 | dev_err(dev, "Failed to initialize phy: %d\n", ret); |
| 869 | goto out_mdiobus_release; |
| 870 | } |
| 871 | |
| 872 | return 0; |
| 873 | |
| 874 | out_mdiobus_release: |
| 875 | mdio_unregister(priv->bus); |
| 876 | mdio_free(priv->bus); |
| 877 | out_reset_release: |
| 878 | reset_release_all(priv->rst, nr); |
| 879 | out_clk_release: |
| 880 | clk_release_all(priv->clk, nc); |
| 881 | |
| 882 | return ret; |
| 883 | } |
| 884 | |
| 885 | static int ave_remove(struct udevice *dev) |
| 886 | { |
| 887 | struct ave_private *priv = dev_get_priv(dev); |
| 888 | |
| 889 | free(priv->phydev); |
| 890 | mdio_unregister(priv->bus); |
| 891 | mdio_free(priv->bus); |
| 892 | reset_release_all(priv->rst, priv->nrsts); |
| 893 | clk_release_all(priv->clk, priv->nclks); |
| 894 | |
| 895 | return 0; |
| 896 | } |
| 897 | |
| 898 | static const struct eth_ops ave_ops = { |
| 899 | .start = ave_start, |
| 900 | .stop = ave_stop, |
| 901 | .send = ave_send, |
| 902 | .recv = ave_recv, |
| 903 | .free_pkt = ave_free_packet, |
| 904 | .write_hwaddr = ave_write_hwaddr, |
| 905 | }; |
| 906 | |
| 907 | static const struct ave_soc_data ave_pro4_data = { |
| 908 | .is_desc_64bit = false, |
| 909 | .clock_names = { |
| 910 | "gio", "ether", "ether-gb", "ether-phy", |
| 911 | }, |
| 912 | .reset_names = { |
| 913 | "gio", "ether", |
| 914 | }, |
| 915 | .get_pinmode = ave_pro4_get_pinmode, |
| 916 | }; |
| 917 | |
| 918 | static const struct ave_soc_data ave_pxs2_data = { |
| 919 | .is_desc_64bit = false, |
| 920 | .clock_names = { |
| 921 | "ether", |
| 922 | }, |
| 923 | .reset_names = { |
| 924 | "ether", |
| 925 | }, |
| 926 | .get_pinmode = ave_pro4_get_pinmode, |
| 927 | }; |
| 928 | |
| 929 | static const struct ave_soc_data ave_ld11_data = { |
| 930 | .is_desc_64bit = false, |
| 931 | .clock_names = { |
| 932 | "ether", |
| 933 | }, |
| 934 | .reset_names = { |
| 935 | "ether", |
| 936 | }, |
| 937 | .get_pinmode = ave_ld11_get_pinmode, |
| 938 | }; |
| 939 | |
| 940 | static const struct ave_soc_data ave_ld20_data = { |
| 941 | .is_desc_64bit = true, |
| 942 | .clock_names = { |
| 943 | "ether", |
| 944 | }, |
| 945 | .reset_names = { |
| 946 | "ether", |
| 947 | }, |
| 948 | .get_pinmode = ave_ld20_get_pinmode, |
| 949 | }; |
| 950 | |
| 951 | static const struct ave_soc_data ave_pxs3_data = { |
| 952 | .is_desc_64bit = false, |
| 953 | .clock_names = { |
| 954 | "ether", |
| 955 | }, |
| 956 | .reset_names = { |
| 957 | "ether", |
| 958 | }, |
| 959 | .get_pinmode = ave_pxs3_get_pinmode, |
| 960 | }; |
| 961 | |
| 962 | static const struct udevice_id ave_ids[] = { |
| 963 | { |
| 964 | .compatible = "socionext,uniphier-pro4-ave4", |
| 965 | .data = (ulong)&ave_pro4_data, |
| 966 | }, |
| 967 | { |
| 968 | .compatible = "socionext,uniphier-pxs2-ave4", |
| 969 | .data = (ulong)&ave_pxs2_data, |
| 970 | }, |
| 971 | { |
| 972 | .compatible = "socionext,uniphier-ld11-ave4", |
| 973 | .data = (ulong)&ave_ld11_data, |
| 974 | }, |
| 975 | { |
| 976 | .compatible = "socionext,uniphier-ld20-ave4", |
| 977 | .data = (ulong)&ave_ld20_data, |
| 978 | }, |
| 979 | { |
| 980 | .compatible = "socionext,uniphier-pxs3-ave4", |
| 981 | .data = (ulong)&ave_pxs3_data, |
| 982 | }, |
| 983 | { /* Sentinel */ } |
| 984 | }; |
| 985 | |
| 986 | U_BOOT_DRIVER(ave) = { |
| 987 | .name = "ave", |
| 988 | .id = UCLASS_ETH, |
| 989 | .of_match = ave_ids, |
| 990 | .probe = ave_probe, |
| 991 | .remove = ave_remove, |
| 992 | .ofdata_to_platdata = ave_ofdata_to_platdata, |
| 993 | .ops = &ave_ops, |
| 994 | .priv_auto_alloc_size = sizeof(struct ave_private), |
| 995 | .platdata_auto_alloc_size = sizeof(struct eth_pdata), |
| 996 | }; |