Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 2 | /* |
| 3 | * Atheros AR71xx / AR9xxx GMAC driver |
| 4 | * |
| 5 | * Copyright (C) 2016 Marek Vasut <marex@denx.de> |
Rosy Song | 51ef2e7 | 2019-03-16 09:24:50 +0800 | [diff] [blame] | 6 | * Copyright (C) 2019 Rosy Song <rosysong@rosinson.com> |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #include <common.h> |
Simon Glass | 6333448 | 2019-11-14 12:57:39 -0700 | [diff] [blame] | 10 | #include <cpu_func.h> |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 11 | #include <dm.h> |
| 12 | #include <errno.h> |
| 13 | #include <miiphy.h> |
| 14 | #include <malloc.h> |
| 15 | #include <linux/compiler.h> |
| 16 | #include <linux/err.h> |
| 17 | #include <linux/mii.h> |
| 18 | #include <wait_bit.h> |
| 19 | #include <asm/io.h> |
| 20 | |
| 21 | #include <mach/ath79.h> |
| 22 | |
| 23 | DECLARE_GLOBAL_DATA_PTR; |
| 24 | |
| 25 | enum ag7xxx_model { |
| 26 | AG7XXX_MODEL_AG933X, |
| 27 | AG7XXX_MODEL_AG934X, |
Rosy Song | 51ef2e7 | 2019-03-16 09:24:50 +0800 | [diff] [blame] | 28 | AG7XXX_MODEL_AG953X, |
| 29 | AG7XXX_MODEL_AG956X |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 30 | }; |
| 31 | |
Joe Hershberger | a1a837d | 2017-06-26 14:40:08 -0500 | [diff] [blame] | 32 | /* MAC Configuration 1 */ |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 33 | #define AG7XXX_ETH_CFG1 0x00 |
| 34 | #define AG7XXX_ETH_CFG1_SOFT_RST BIT(31) |
| 35 | #define AG7XXX_ETH_CFG1_RX_RST BIT(19) |
| 36 | #define AG7XXX_ETH_CFG1_TX_RST BIT(18) |
| 37 | #define AG7XXX_ETH_CFG1_LOOPBACK BIT(8) |
| 38 | #define AG7XXX_ETH_CFG1_RX_EN BIT(2) |
| 39 | #define AG7XXX_ETH_CFG1_TX_EN BIT(0) |
| 40 | |
Joe Hershberger | a1a837d | 2017-06-26 14:40:08 -0500 | [diff] [blame] | 41 | /* MAC Configuration 2 */ |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 42 | #define AG7XXX_ETH_CFG2 0x04 |
| 43 | #define AG7XXX_ETH_CFG2_IF_1000 BIT(9) |
| 44 | #define AG7XXX_ETH_CFG2_IF_10_100 BIT(8) |
| 45 | #define AG7XXX_ETH_CFG2_IF_SPEED_MASK (3 << 8) |
| 46 | #define AG7XXX_ETH_CFG2_HUGE_FRAME_EN BIT(5) |
| 47 | #define AG7XXX_ETH_CFG2_LEN_CHECK BIT(4) |
| 48 | #define AG7XXX_ETH_CFG2_PAD_CRC_EN BIT(2) |
| 49 | #define AG7XXX_ETH_CFG2_FDX BIT(0) |
| 50 | |
Joe Hershberger | a1a837d | 2017-06-26 14:40:08 -0500 | [diff] [blame] | 51 | /* MII Configuration */ |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 52 | #define AG7XXX_ETH_MII_MGMT_CFG 0x20 |
| 53 | #define AG7XXX_ETH_MII_MGMT_CFG_RESET BIT(31) |
| 54 | |
Joe Hershberger | a1a837d | 2017-06-26 14:40:08 -0500 | [diff] [blame] | 55 | /* MII Command */ |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 56 | #define AG7XXX_ETH_MII_MGMT_CMD 0x24 |
| 57 | #define AG7XXX_ETH_MII_MGMT_CMD_READ 0x1 |
| 58 | |
Joe Hershberger | a1a837d | 2017-06-26 14:40:08 -0500 | [diff] [blame] | 59 | /* MII Address */ |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 60 | #define AG7XXX_ETH_MII_MGMT_ADDRESS 0x28 |
| 61 | #define AG7XXX_ETH_MII_MGMT_ADDRESS_SHIFT 8 |
| 62 | |
Joe Hershberger | a1a837d | 2017-06-26 14:40:08 -0500 | [diff] [blame] | 63 | /* MII Control */ |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 64 | #define AG7XXX_ETH_MII_MGMT_CTRL 0x2c |
| 65 | |
Joe Hershberger | a1a837d | 2017-06-26 14:40:08 -0500 | [diff] [blame] | 66 | /* MII Status */ |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 67 | #define AG7XXX_ETH_MII_MGMT_STATUS 0x30 |
| 68 | |
Joe Hershberger | a1a837d | 2017-06-26 14:40:08 -0500 | [diff] [blame] | 69 | /* MII Indicators */ |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 70 | #define AG7XXX_ETH_MII_MGMT_IND 0x34 |
| 71 | #define AG7XXX_ETH_MII_MGMT_IND_INVALID BIT(2) |
| 72 | #define AG7XXX_ETH_MII_MGMT_IND_BUSY BIT(0) |
| 73 | |
Joe Hershberger | a1a837d | 2017-06-26 14:40:08 -0500 | [diff] [blame] | 74 | /* STA Address 1 & 2 */ |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 75 | #define AG7XXX_ETH_ADDR1 0x40 |
| 76 | #define AG7XXX_ETH_ADDR2 0x44 |
| 77 | |
Joe Hershberger | a1a837d | 2017-06-26 14:40:08 -0500 | [diff] [blame] | 78 | /* ETH Configuration 0 - 5 */ |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 79 | #define AG7XXX_ETH_FIFO_CFG_0 0x48 |
| 80 | #define AG7XXX_ETH_FIFO_CFG_1 0x4c |
| 81 | #define AG7XXX_ETH_FIFO_CFG_2 0x50 |
| 82 | #define AG7XXX_ETH_FIFO_CFG_3 0x54 |
| 83 | #define AG7XXX_ETH_FIFO_CFG_4 0x58 |
| 84 | #define AG7XXX_ETH_FIFO_CFG_5 0x5c |
| 85 | |
Joe Hershberger | a1a837d | 2017-06-26 14:40:08 -0500 | [diff] [blame] | 86 | /* DMA Transfer Control for Queue 0 */ |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 87 | #define AG7XXX_ETH_DMA_TX_CTRL 0x180 |
| 88 | #define AG7XXX_ETH_DMA_TX_CTRL_TXE BIT(0) |
| 89 | |
Joe Hershberger | a1a837d | 2017-06-26 14:40:08 -0500 | [diff] [blame] | 90 | /* Descriptor Address for Queue 0 Tx */ |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 91 | #define AG7XXX_ETH_DMA_TX_DESC 0x184 |
| 92 | |
Joe Hershberger | a1a837d | 2017-06-26 14:40:08 -0500 | [diff] [blame] | 93 | /* DMA Tx Status */ |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 94 | #define AG7XXX_ETH_DMA_TX_STATUS 0x188 |
| 95 | |
Joe Hershberger | a1a837d | 2017-06-26 14:40:08 -0500 | [diff] [blame] | 96 | /* Rx Control */ |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 97 | #define AG7XXX_ETH_DMA_RX_CTRL 0x18c |
| 98 | #define AG7XXX_ETH_DMA_RX_CTRL_RXE BIT(0) |
| 99 | |
Joe Hershberger | a1a837d | 2017-06-26 14:40:08 -0500 | [diff] [blame] | 100 | /* Pointer to Rx Descriptor */ |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 101 | #define AG7XXX_ETH_DMA_RX_DESC 0x190 |
| 102 | |
Joe Hershberger | a1a837d | 2017-06-26 14:40:08 -0500 | [diff] [blame] | 103 | /* Rx Status */ |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 104 | #define AG7XXX_ETH_DMA_RX_STATUS 0x194 |
| 105 | |
Rosy Song | 361c69e | 2019-02-05 17:50:44 +0800 | [diff] [blame] | 106 | /* Custom register at 0x1805002C */ |
| 107 | #define AG7XXX_ETH_XMII 0x2C |
| 108 | #define AG7XXX_ETH_XMII_TX_INVERT BIT(31) |
| 109 | #define AG7XXX_ETH_XMII_RX_DELAY_LSB 28 |
| 110 | #define AG7XXX_ETH_XMII_RX_DELAY_MASK 0x30000000 |
| 111 | #define AG7XXX_ETH_XMII_RX_DELAY_SET(x) \ |
| 112 | (((x) << AG7XXX_ETH_XMII_RX_DELAY_LSB) & AG7XXX_ETH_XMII_RX_DELAY_MASK) |
| 113 | #define AG7XXX_ETH_XMII_TX_DELAY_LSB 26 |
| 114 | #define AG7XXX_ETH_XMII_TX_DELAY_MASK 0x0c000000 |
| 115 | #define AG7XXX_ETH_XMII_TX_DELAY_SET(x) \ |
| 116 | (((x) << AG7XXX_ETH_XMII_TX_DELAY_LSB) & AG7XXX_ETH_XMII_TX_DELAY_MASK) |
| 117 | #define AG7XXX_ETH_XMII_GIGE BIT(25) |
| 118 | |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 119 | /* Custom register at 0x18070000 */ |
| 120 | #define AG7XXX_GMAC_ETH_CFG 0x00 |
Rosy Song | 361c69e | 2019-02-05 17:50:44 +0800 | [diff] [blame] | 121 | #define AG7XXX_ETH_CFG_RXDV_DELAY_LSB 16 |
| 122 | #define AG7XXX_ETH_CFG_RXDV_DELAY_MASK 0x00030000 |
| 123 | #define AG7XXX_ETH_CFG_RXDV_DELAY_SET(x) \ |
| 124 | (((x) << AG7XXX_ETH_CFG_RXDV_DELAY_LSB) & AG7XXX_ETH_CFG_RXDV_DELAY_MASK) |
| 125 | #define AG7XXX_ETH_CFG_RXD_DELAY_LSB 14 |
| 126 | #define AG7XXX_ETH_CFG_RXD_DELAY_MASK 0x0000c000 |
| 127 | #define AG7XXX_ETH_CFG_RXD_DELAY_SET(x) \ |
| 128 | (((x) << AG7XXX_ETH_CFG_RXD_DELAY_LSB) & AG7XXX_ETH_CFG_RXD_DELAY_MASK) |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 129 | #define AG7XXX_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8) |
| 130 | #define AG7XXX_ETH_CFG_SW_PHY_SWAP BIT(7) |
| 131 | #define AG7XXX_ETH_CFG_SW_ONLY_MODE BIT(6) |
| 132 | #define AG7XXX_ETH_CFG_GE0_ERR_EN BIT(5) |
| 133 | #define AG7XXX_ETH_CFG_MII_GE0_SLAVE BIT(4) |
| 134 | #define AG7XXX_ETH_CFG_MII_GE0_MASTER BIT(3) |
| 135 | #define AG7XXX_ETH_CFG_GMII_GE0 BIT(2) |
| 136 | #define AG7XXX_ETH_CFG_MII_GE0 BIT(1) |
| 137 | #define AG7XXX_ETH_CFG_RGMII_GE0 BIT(0) |
| 138 | |
| 139 | #define CONFIG_TX_DESCR_NUM 8 |
| 140 | #define CONFIG_RX_DESCR_NUM 8 |
| 141 | #define CONFIG_ETH_BUFSIZE 2048 |
| 142 | #define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM) |
| 143 | #define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM) |
| 144 | |
| 145 | /* DMA descriptor. */ |
| 146 | struct ag7xxx_dma_desc { |
| 147 | u32 data_addr; |
| 148 | #define AG7XXX_DMADESC_IS_EMPTY BIT(31) |
| 149 | #define AG7XXX_DMADESC_FTPP_OVERRIDE_OFFSET 16 |
| 150 | #define AG7XXX_DMADESC_PKT_SIZE_OFFSET 0 |
| 151 | #define AG7XXX_DMADESC_PKT_SIZE_MASK 0xfff |
| 152 | u32 config; |
| 153 | u32 next_desc; |
| 154 | u32 _pad[5]; |
| 155 | }; |
| 156 | |
| 157 | struct ar7xxx_eth_priv { |
| 158 | struct ag7xxx_dma_desc tx_mac_descrtable[CONFIG_TX_DESCR_NUM]; |
| 159 | struct ag7xxx_dma_desc rx_mac_descrtable[CONFIG_RX_DESCR_NUM]; |
| 160 | char txbuffs[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN); |
| 161 | char rxbuffs[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN); |
| 162 | |
| 163 | void __iomem *regs; |
| 164 | void __iomem *phyregs; |
| 165 | |
| 166 | struct eth_device *dev; |
| 167 | struct phy_device *phydev; |
| 168 | struct mii_dev *bus; |
| 169 | |
| 170 | u32 interface; |
| 171 | u32 tx_currdescnum; |
| 172 | u32 rx_currdescnum; |
| 173 | enum ag7xxx_model model; |
| 174 | }; |
| 175 | |
| 176 | /* |
| 177 | * Switch and MDIO access |
| 178 | */ |
| 179 | static int ag7xxx_switch_read(struct mii_dev *bus, int addr, int reg, u16 *val) |
| 180 | { |
| 181 | struct ar7xxx_eth_priv *priv = bus->priv; |
| 182 | void __iomem *regs = priv->phyregs; |
| 183 | int ret; |
| 184 | |
| 185 | writel(0x0, regs + AG7XXX_ETH_MII_MGMT_CMD); |
| 186 | writel((addr << AG7XXX_ETH_MII_MGMT_ADDRESS_SHIFT) | reg, |
| 187 | regs + AG7XXX_ETH_MII_MGMT_ADDRESS); |
| 188 | writel(AG7XXX_ETH_MII_MGMT_CMD_READ, |
| 189 | regs + AG7XXX_ETH_MII_MGMT_CMD); |
| 190 | |
Álvaro Fernández Rojas | 918de03 | 2018-01-23 17:14:55 +0100 | [diff] [blame] | 191 | ret = wait_for_bit_le32(regs + AG7XXX_ETH_MII_MGMT_IND, |
| 192 | AG7XXX_ETH_MII_MGMT_IND_BUSY, 0, 1000, 0); |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 193 | if (ret) |
| 194 | return ret; |
| 195 | |
| 196 | *val = readl(regs + AG7XXX_ETH_MII_MGMT_STATUS) & 0xffff; |
| 197 | writel(0x0, regs + AG7XXX_ETH_MII_MGMT_CMD); |
| 198 | |
| 199 | return 0; |
| 200 | } |
| 201 | |
| 202 | static int ag7xxx_switch_write(struct mii_dev *bus, int addr, int reg, u16 val) |
| 203 | { |
| 204 | struct ar7xxx_eth_priv *priv = bus->priv; |
| 205 | void __iomem *regs = priv->phyregs; |
| 206 | int ret; |
| 207 | |
| 208 | writel((addr << AG7XXX_ETH_MII_MGMT_ADDRESS_SHIFT) | reg, |
| 209 | regs + AG7XXX_ETH_MII_MGMT_ADDRESS); |
| 210 | writel(val, regs + AG7XXX_ETH_MII_MGMT_CTRL); |
| 211 | |
Álvaro Fernández Rojas | 918de03 | 2018-01-23 17:14:55 +0100 | [diff] [blame] | 212 | ret = wait_for_bit_le32(regs + AG7XXX_ETH_MII_MGMT_IND, |
| 213 | AG7XXX_ETH_MII_MGMT_IND_BUSY, 0, 1000, 0); |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 214 | |
| 215 | return ret; |
| 216 | } |
| 217 | |
| 218 | static int ag7xxx_switch_reg_read(struct mii_dev *bus, int reg, u32 *val) |
| 219 | { |
| 220 | struct ar7xxx_eth_priv *priv = bus->priv; |
| 221 | u32 phy_addr; |
| 222 | u32 reg_addr; |
| 223 | u32 phy_temp; |
| 224 | u32 reg_temp; |
Rosy Song | 51ef2e7 | 2019-03-16 09:24:50 +0800 | [diff] [blame] | 225 | u32 reg_temp_w = (reg & 0xfffffffc) >> 1; |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 226 | u16 rv = 0; |
| 227 | int ret; |
| 228 | |
Rosy Song | 361c69e | 2019-02-05 17:50:44 +0800 | [diff] [blame] | 229 | if (priv->model == AG7XXX_MODEL_AG933X || |
| 230 | priv->model == AG7XXX_MODEL_AG953X) { |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 231 | phy_addr = 0x1f; |
| 232 | reg_addr = 0x10; |
Rosy Song | 51ef2e7 | 2019-03-16 09:24:50 +0800 | [diff] [blame] | 233 | } else if (priv->model == AG7XXX_MODEL_AG934X || |
| 234 | priv->model == AG7XXX_MODEL_AG956X) { |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 235 | phy_addr = 0x18; |
| 236 | reg_addr = 0x00; |
| 237 | } else |
| 238 | return -EINVAL; |
| 239 | |
Rosy Song | 51ef2e7 | 2019-03-16 09:24:50 +0800 | [diff] [blame] | 240 | if (priv->model == AG7XXX_MODEL_AG956X) |
| 241 | ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, (reg >> 9) & 0x1ff); |
| 242 | else |
| 243 | ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, reg >> 9); |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 244 | if (ret) |
| 245 | return ret; |
| 246 | |
| 247 | phy_temp = ((reg >> 6) & 0x7) | 0x10; |
Rosy Song | 51ef2e7 | 2019-03-16 09:24:50 +0800 | [diff] [blame] | 248 | if (priv->model == AG7XXX_MODEL_AG956X) |
| 249 | reg_temp = reg_temp_w & 0x1f; |
| 250 | else |
| 251 | reg_temp = (reg >> 1) & 0x1e; |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 252 | *val = 0; |
| 253 | |
| 254 | ret = ag7xxx_switch_read(bus, phy_temp, reg_temp | 0, &rv); |
| 255 | if (ret < 0) |
| 256 | return ret; |
| 257 | *val |= rv; |
| 258 | |
Rosy Song | 51ef2e7 | 2019-03-16 09:24:50 +0800 | [diff] [blame] | 259 | if (priv->model == AG7XXX_MODEL_AG956X) { |
| 260 | phy_temp = (((reg_temp_w + 1) >> 5) & 0x7) | 0x10; |
| 261 | reg_temp = (reg_temp_w + 1) & 0x1f; |
| 262 | ret = ag7xxx_switch_read(bus, phy_temp, reg_temp, &rv); |
| 263 | } else { |
| 264 | ret = ag7xxx_switch_read(bus, phy_temp, reg_temp | 1, &rv); |
| 265 | } |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 266 | if (ret < 0) |
| 267 | return ret; |
| 268 | *val |= (rv << 16); |
| 269 | |
| 270 | return 0; |
| 271 | } |
| 272 | |
| 273 | static int ag7xxx_switch_reg_write(struct mii_dev *bus, int reg, u32 val) |
| 274 | { |
| 275 | struct ar7xxx_eth_priv *priv = bus->priv; |
| 276 | u32 phy_addr; |
| 277 | u32 reg_addr; |
| 278 | u32 phy_temp; |
| 279 | u32 reg_temp; |
Rosy Song | 51ef2e7 | 2019-03-16 09:24:50 +0800 | [diff] [blame] | 280 | u32 reg_temp_w = (reg & 0xfffffffc) >> 1; |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 281 | int ret; |
| 282 | |
Rosy Song | 361c69e | 2019-02-05 17:50:44 +0800 | [diff] [blame] | 283 | if (priv->model == AG7XXX_MODEL_AG933X || |
| 284 | priv->model == AG7XXX_MODEL_AG953X) { |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 285 | phy_addr = 0x1f; |
| 286 | reg_addr = 0x10; |
Rosy Song | 51ef2e7 | 2019-03-16 09:24:50 +0800 | [diff] [blame] | 287 | } else if (priv->model == AG7XXX_MODEL_AG934X || |
| 288 | priv->model == AG7XXX_MODEL_AG956X) { |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 289 | phy_addr = 0x18; |
| 290 | reg_addr = 0x00; |
| 291 | } else |
| 292 | return -EINVAL; |
| 293 | |
Rosy Song | 51ef2e7 | 2019-03-16 09:24:50 +0800 | [diff] [blame] | 294 | if (priv->model == AG7XXX_MODEL_AG956X) |
| 295 | ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, (reg >> 9) & 0x1ff); |
| 296 | else |
| 297 | ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, reg >> 9); |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 298 | if (ret) |
| 299 | return ret; |
| 300 | |
Rosy Song | 51ef2e7 | 2019-03-16 09:24:50 +0800 | [diff] [blame] | 301 | if (priv->model == AG7XXX_MODEL_AG956X) { |
| 302 | reg_temp = (reg_temp_w + 1) & 0x1f; |
| 303 | phy_temp = (((reg_temp_w + 1) >> 5) & 0x7) | 0x10; |
| 304 | } else { |
| 305 | phy_temp = ((reg >> 6) & 0x7) | 0x10; |
| 306 | reg_temp = (reg >> 1) & 0x1e; |
| 307 | } |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 308 | |
| 309 | /* |
| 310 | * The switch on AR933x has some special register behavior, which |
| 311 | * expects particular write order of their nibbles: |
| 312 | * 0x40 ..... MSB first, LSB second |
| 313 | * 0x50 ..... MSB first, LSB second |
| 314 | * 0x98 ..... LSB first, MSB second |
| 315 | * others ... don't care |
| 316 | */ |
| 317 | if ((priv->model == AG7XXX_MODEL_AG933X) && (reg == 0x98)) { |
| 318 | ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 0, val & 0xffff); |
| 319 | if (ret < 0) |
| 320 | return ret; |
| 321 | |
| 322 | ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 1, val >> 16); |
| 323 | if (ret < 0) |
| 324 | return ret; |
| 325 | } else { |
Rosy Song | 51ef2e7 | 2019-03-16 09:24:50 +0800 | [diff] [blame] | 326 | if (priv->model == AG7XXX_MODEL_AG956X) |
| 327 | ret = ag7xxx_switch_write(bus, phy_temp, reg_temp, val >> 16); |
| 328 | else |
| 329 | ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 1, val >> 16); |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 330 | if (ret < 0) |
| 331 | return ret; |
| 332 | |
Rosy Song | 51ef2e7 | 2019-03-16 09:24:50 +0800 | [diff] [blame] | 333 | if (priv->model == AG7XXX_MODEL_AG956X) { |
| 334 | phy_temp = ((reg_temp_w >> 5) & 0x7) | 0x10; |
| 335 | reg_temp = reg_temp_w & 0x1f; |
| 336 | } |
| 337 | |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 338 | ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 0, val & 0xffff); |
| 339 | if (ret < 0) |
| 340 | return ret; |
| 341 | } |
| 342 | |
| 343 | return 0; |
| 344 | } |
| 345 | |
Joe Hershberger | 5a41d66 | 2017-06-26 14:40:09 -0500 | [diff] [blame] | 346 | static int ag7xxx_mdio_rw(struct mii_dev *bus, int addr, int reg, u32 val) |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 347 | { |
| 348 | u32 data; |
Joe Hershberger | 5a41d66 | 2017-06-26 14:40:09 -0500 | [diff] [blame] | 349 | unsigned long start; |
| 350 | int ret; |
| 351 | /* No idea if this is long enough or too long */ |
| 352 | int timeout_ms = 1000; |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 353 | |
| 354 | /* Dummy read followed by PHY read/write command. */ |
Joe Hershberger | 5a41d66 | 2017-06-26 14:40:09 -0500 | [diff] [blame] | 355 | ret = ag7xxx_switch_reg_read(bus, 0x98, &data); |
| 356 | if (ret < 0) |
| 357 | return ret; |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 358 | data = val | (reg << 16) | (addr << 21) | BIT(30) | BIT(31); |
Joe Hershberger | 5a41d66 | 2017-06-26 14:40:09 -0500 | [diff] [blame] | 359 | ret = ag7xxx_switch_reg_write(bus, 0x98, data); |
| 360 | if (ret < 0) |
| 361 | return ret; |
| 362 | |
| 363 | start = get_timer(0); |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 364 | |
| 365 | /* Wait for operation to finish */ |
| 366 | do { |
Joe Hershberger | 5a41d66 | 2017-06-26 14:40:09 -0500 | [diff] [blame] | 367 | ret = ag7xxx_switch_reg_read(bus, 0x98, &data); |
| 368 | if (ret < 0) |
| 369 | return ret; |
| 370 | |
| 371 | if (get_timer(start) > timeout_ms) |
| 372 | return -ETIMEDOUT; |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 373 | } while (data & BIT(31)); |
| 374 | |
| 375 | return data & 0xffff; |
| 376 | } |
| 377 | |
| 378 | static int ag7xxx_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) |
| 379 | { |
| 380 | return ag7xxx_mdio_rw(bus, addr, reg, BIT(27)); |
| 381 | } |
| 382 | |
| 383 | static int ag7xxx_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, |
| 384 | u16 val) |
| 385 | { |
Joe Hershberger | 5a41d66 | 2017-06-26 14:40:09 -0500 | [diff] [blame] | 386 | int ret; |
| 387 | |
| 388 | ret = ag7xxx_mdio_rw(bus, addr, reg, val); |
| 389 | if (ret < 0) |
| 390 | return ret; |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 391 | return 0; |
| 392 | } |
| 393 | |
| 394 | /* |
| 395 | * DMA ring handlers |
| 396 | */ |
| 397 | static void ag7xxx_dma_clean_tx(struct udevice *dev) |
| 398 | { |
| 399 | struct ar7xxx_eth_priv *priv = dev_get_priv(dev); |
| 400 | struct ag7xxx_dma_desc *curr, *next; |
| 401 | u32 start, end; |
| 402 | int i; |
| 403 | |
| 404 | for (i = 0; i < CONFIG_TX_DESCR_NUM; i++) { |
| 405 | curr = &priv->tx_mac_descrtable[i]; |
| 406 | next = &priv->tx_mac_descrtable[(i + 1) % CONFIG_TX_DESCR_NUM]; |
| 407 | |
| 408 | curr->data_addr = virt_to_phys(&priv->txbuffs[i * CONFIG_ETH_BUFSIZE]); |
| 409 | curr->config = AG7XXX_DMADESC_IS_EMPTY; |
| 410 | curr->next_desc = virt_to_phys(next); |
| 411 | } |
| 412 | |
| 413 | priv->tx_currdescnum = 0; |
| 414 | |
| 415 | /* Cache: Flush descriptors, don't care about buffers. */ |
| 416 | start = (u32)(&priv->tx_mac_descrtable[0]); |
| 417 | end = start + sizeof(priv->tx_mac_descrtable); |
| 418 | flush_dcache_range(start, end); |
| 419 | } |
| 420 | |
| 421 | static void ag7xxx_dma_clean_rx(struct udevice *dev) |
| 422 | { |
| 423 | struct ar7xxx_eth_priv *priv = dev_get_priv(dev); |
| 424 | struct ag7xxx_dma_desc *curr, *next; |
| 425 | u32 start, end; |
| 426 | int i; |
| 427 | |
| 428 | for (i = 0; i < CONFIG_RX_DESCR_NUM; i++) { |
| 429 | curr = &priv->rx_mac_descrtable[i]; |
| 430 | next = &priv->rx_mac_descrtable[(i + 1) % CONFIG_RX_DESCR_NUM]; |
| 431 | |
| 432 | curr->data_addr = virt_to_phys(&priv->rxbuffs[i * CONFIG_ETH_BUFSIZE]); |
| 433 | curr->config = AG7XXX_DMADESC_IS_EMPTY; |
| 434 | curr->next_desc = virt_to_phys(next); |
| 435 | } |
| 436 | |
| 437 | priv->rx_currdescnum = 0; |
| 438 | |
| 439 | /* Cache: Flush+Invalidate descriptors, Invalidate buffers. */ |
| 440 | start = (u32)(&priv->rx_mac_descrtable[0]); |
| 441 | end = start + sizeof(priv->rx_mac_descrtable); |
| 442 | flush_dcache_range(start, end); |
| 443 | invalidate_dcache_range(start, end); |
| 444 | |
| 445 | start = (u32)&priv->rxbuffs; |
| 446 | end = start + sizeof(priv->rxbuffs); |
| 447 | invalidate_dcache_range(start, end); |
| 448 | } |
| 449 | |
| 450 | /* |
| 451 | * Ethernet I/O |
| 452 | */ |
| 453 | static int ag7xxx_eth_send(struct udevice *dev, void *packet, int length) |
| 454 | { |
| 455 | struct ar7xxx_eth_priv *priv = dev_get_priv(dev); |
| 456 | struct ag7xxx_dma_desc *curr; |
| 457 | u32 start, end; |
| 458 | |
| 459 | curr = &priv->tx_mac_descrtable[priv->tx_currdescnum]; |
| 460 | |
| 461 | /* Cache: Invalidate descriptor. */ |
| 462 | start = (u32)curr; |
| 463 | end = start + sizeof(*curr); |
| 464 | invalidate_dcache_range(start, end); |
| 465 | |
| 466 | if (!(curr->config & AG7XXX_DMADESC_IS_EMPTY)) { |
| 467 | printf("ag7xxx: Out of TX DMA descriptors!\n"); |
| 468 | return -EPERM; |
| 469 | } |
| 470 | |
| 471 | /* Copy the packet into the data buffer. */ |
| 472 | memcpy(phys_to_virt(curr->data_addr), packet, length); |
| 473 | curr->config = length & AG7XXX_DMADESC_PKT_SIZE_MASK; |
| 474 | |
| 475 | /* Cache: Flush descriptor, Flush buffer. */ |
| 476 | start = (u32)curr; |
| 477 | end = start + sizeof(*curr); |
| 478 | flush_dcache_range(start, end); |
| 479 | start = (u32)phys_to_virt(curr->data_addr); |
| 480 | end = start + length; |
| 481 | flush_dcache_range(start, end); |
| 482 | |
| 483 | /* Load the DMA descriptor and start TX DMA. */ |
| 484 | writel(AG7XXX_ETH_DMA_TX_CTRL_TXE, |
| 485 | priv->regs + AG7XXX_ETH_DMA_TX_CTRL); |
| 486 | |
| 487 | /* Switch to next TX descriptor. */ |
| 488 | priv->tx_currdescnum = (priv->tx_currdescnum + 1) % CONFIG_TX_DESCR_NUM; |
| 489 | |
| 490 | return 0; |
| 491 | } |
| 492 | |
| 493 | static int ag7xxx_eth_recv(struct udevice *dev, int flags, uchar **packetp) |
| 494 | { |
| 495 | struct ar7xxx_eth_priv *priv = dev_get_priv(dev); |
| 496 | struct ag7xxx_dma_desc *curr; |
| 497 | u32 start, end, length; |
| 498 | |
| 499 | curr = &priv->rx_mac_descrtable[priv->rx_currdescnum]; |
| 500 | |
| 501 | /* Cache: Invalidate descriptor. */ |
| 502 | start = (u32)curr; |
| 503 | end = start + sizeof(*curr); |
| 504 | invalidate_dcache_range(start, end); |
| 505 | |
| 506 | /* No packets received. */ |
| 507 | if (curr->config & AG7XXX_DMADESC_IS_EMPTY) |
| 508 | return -EAGAIN; |
| 509 | |
| 510 | length = curr->config & AG7XXX_DMADESC_PKT_SIZE_MASK; |
| 511 | |
| 512 | /* Cache: Invalidate buffer. */ |
| 513 | start = (u32)phys_to_virt(curr->data_addr); |
| 514 | end = start + length; |
| 515 | invalidate_dcache_range(start, end); |
| 516 | |
| 517 | /* Receive one packet and return length. */ |
| 518 | *packetp = phys_to_virt(curr->data_addr); |
| 519 | return length; |
| 520 | } |
| 521 | |
| 522 | static int ag7xxx_eth_free_pkt(struct udevice *dev, uchar *packet, |
| 523 | int length) |
| 524 | { |
| 525 | struct ar7xxx_eth_priv *priv = dev_get_priv(dev); |
| 526 | struct ag7xxx_dma_desc *curr; |
| 527 | u32 start, end; |
| 528 | |
| 529 | curr = &priv->rx_mac_descrtable[priv->rx_currdescnum]; |
| 530 | |
| 531 | curr->config = AG7XXX_DMADESC_IS_EMPTY; |
| 532 | |
| 533 | /* Cache: Flush descriptor. */ |
| 534 | start = (u32)curr; |
| 535 | end = start + sizeof(*curr); |
| 536 | flush_dcache_range(start, end); |
| 537 | |
| 538 | /* Switch to next RX descriptor. */ |
| 539 | priv->rx_currdescnum = (priv->rx_currdescnum + 1) % CONFIG_RX_DESCR_NUM; |
| 540 | |
| 541 | return 0; |
| 542 | } |
| 543 | |
| 544 | static int ag7xxx_eth_start(struct udevice *dev) |
| 545 | { |
| 546 | struct ar7xxx_eth_priv *priv = dev_get_priv(dev); |
| 547 | |
| 548 | /* FIXME: Check if link up */ |
| 549 | |
| 550 | /* Clear the DMA rings. */ |
| 551 | ag7xxx_dma_clean_tx(dev); |
| 552 | ag7xxx_dma_clean_rx(dev); |
| 553 | |
| 554 | /* Load DMA descriptors and start the RX DMA. */ |
| 555 | writel(virt_to_phys(&priv->tx_mac_descrtable[priv->tx_currdescnum]), |
| 556 | priv->regs + AG7XXX_ETH_DMA_TX_DESC); |
| 557 | writel(virt_to_phys(&priv->rx_mac_descrtable[priv->rx_currdescnum]), |
| 558 | priv->regs + AG7XXX_ETH_DMA_RX_DESC); |
| 559 | writel(AG7XXX_ETH_DMA_RX_CTRL_RXE, |
| 560 | priv->regs + AG7XXX_ETH_DMA_RX_CTRL); |
| 561 | |
| 562 | return 0; |
| 563 | } |
| 564 | |
| 565 | static void ag7xxx_eth_stop(struct udevice *dev) |
| 566 | { |
| 567 | struct ar7xxx_eth_priv *priv = dev_get_priv(dev); |
| 568 | |
| 569 | /* Stop the TX DMA. */ |
| 570 | writel(0, priv->regs + AG7XXX_ETH_DMA_TX_CTRL); |
Álvaro Fernández Rojas | 918de03 | 2018-01-23 17:14:55 +0100 | [diff] [blame] | 571 | wait_for_bit_le32(priv->regs + AG7XXX_ETH_DMA_TX_CTRL, ~0, 0, |
| 572 | 1000, 0); |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 573 | |
| 574 | /* Stop the RX DMA. */ |
| 575 | writel(0, priv->regs + AG7XXX_ETH_DMA_RX_CTRL); |
Álvaro Fernández Rojas | 918de03 | 2018-01-23 17:14:55 +0100 | [diff] [blame] | 576 | wait_for_bit_le32(priv->regs + AG7XXX_ETH_DMA_RX_CTRL, ~0, 0, |
| 577 | 1000, 0); |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 578 | } |
| 579 | |
| 580 | /* |
| 581 | * Hardware setup |
| 582 | */ |
| 583 | static int ag7xxx_eth_write_hwaddr(struct udevice *dev) |
| 584 | { |
| 585 | struct eth_pdata *pdata = dev_get_platdata(dev); |
| 586 | struct ar7xxx_eth_priv *priv = dev_get_priv(dev); |
| 587 | unsigned char *mac = pdata->enetaddr; |
| 588 | u32 macid_lo, macid_hi; |
| 589 | |
| 590 | macid_hi = mac[3] | (mac[2] << 8) | (mac[1] << 16) | (mac[0] << 24); |
| 591 | macid_lo = (mac[5] << 16) | (mac[4] << 24); |
| 592 | |
| 593 | writel(macid_lo, priv->regs + AG7XXX_ETH_ADDR1); |
| 594 | writel(macid_hi, priv->regs + AG7XXX_ETH_ADDR2); |
| 595 | |
| 596 | return 0; |
| 597 | } |
| 598 | |
| 599 | static void ag7xxx_hw_setup(struct udevice *dev) |
| 600 | { |
| 601 | struct ar7xxx_eth_priv *priv = dev_get_priv(dev); |
| 602 | u32 speed; |
| 603 | |
| 604 | setbits_be32(priv->regs + AG7XXX_ETH_CFG1, |
| 605 | AG7XXX_ETH_CFG1_RX_RST | AG7XXX_ETH_CFG1_TX_RST | |
| 606 | AG7XXX_ETH_CFG1_SOFT_RST); |
| 607 | |
| 608 | mdelay(10); |
| 609 | |
| 610 | writel(AG7XXX_ETH_CFG1_RX_EN | AG7XXX_ETH_CFG1_TX_EN, |
| 611 | priv->regs + AG7XXX_ETH_CFG1); |
| 612 | |
| 613 | if (priv->interface == PHY_INTERFACE_MODE_RMII) |
| 614 | speed = AG7XXX_ETH_CFG2_IF_10_100; |
| 615 | else |
| 616 | speed = AG7XXX_ETH_CFG2_IF_1000; |
| 617 | |
| 618 | clrsetbits_be32(priv->regs + AG7XXX_ETH_CFG2, |
| 619 | AG7XXX_ETH_CFG2_IF_SPEED_MASK, |
| 620 | speed | AG7XXX_ETH_CFG2_PAD_CRC_EN | |
| 621 | AG7XXX_ETH_CFG2_LEN_CHECK); |
| 622 | |
| 623 | writel(0xfff0000, priv->regs + AG7XXX_ETH_FIFO_CFG_1); |
| 624 | writel(0x1fff, priv->regs + AG7XXX_ETH_FIFO_CFG_2); |
| 625 | |
| 626 | writel(0x1f00, priv->regs + AG7XXX_ETH_FIFO_CFG_0); |
| 627 | setbits_be32(priv->regs + AG7XXX_ETH_FIFO_CFG_4, 0x3ffff); |
| 628 | writel(0x10ffff, priv->regs + AG7XXX_ETH_FIFO_CFG_1); |
| 629 | writel(0xaaa0555, priv->regs + AG7XXX_ETH_FIFO_CFG_2); |
| 630 | writel(0x7eccf, priv->regs + AG7XXX_ETH_FIFO_CFG_5); |
| 631 | writel(0x1f00140, priv->regs + AG7XXX_ETH_FIFO_CFG_3); |
| 632 | } |
| 633 | |
| 634 | static int ag7xxx_mii_get_div(void) |
| 635 | { |
| 636 | ulong freq = get_bus_freq(0); |
| 637 | |
| 638 | switch (freq / 1000000) { |
| 639 | case 150: return 0x7; |
| 640 | case 175: return 0x5; |
| 641 | case 200: return 0x4; |
| 642 | case 210: return 0x9; |
| 643 | case 220: return 0x9; |
| 644 | default: return 0x7; |
| 645 | } |
| 646 | } |
| 647 | |
| 648 | static int ag7xxx_mii_setup(struct udevice *dev) |
| 649 | { |
| 650 | struct ar7xxx_eth_priv *priv = dev_get_priv(dev); |
| 651 | int i, ret, div = ag7xxx_mii_get_div(); |
| 652 | u32 reg; |
| 653 | |
| 654 | if (priv->model == AG7XXX_MODEL_AG933X) { |
| 655 | /* Unit 0 is PHY-less on AR9331, see datasheet Figure 2-3 */ |
| 656 | if (priv->interface == PHY_INTERFACE_MODE_RMII) |
| 657 | return 0; |
| 658 | } |
| 659 | |
Rosy Song | 361c69e | 2019-02-05 17:50:44 +0800 | [diff] [blame] | 660 | if (priv->model == AG7XXX_MODEL_AG934X) |
| 661 | reg = 0x4; |
| 662 | else if (priv->model == AG7XXX_MODEL_AG953X) |
| 663 | reg = 0x2; |
Rosy Song | 51ef2e7 | 2019-03-16 09:24:50 +0800 | [diff] [blame] | 664 | else if (priv->model == AG7XXX_MODEL_AG956X) |
| 665 | reg = 0x7; |
Rosy Song | 361c69e | 2019-02-05 17:50:44 +0800 | [diff] [blame] | 666 | |
| 667 | if (priv->model == AG7XXX_MODEL_AG934X || |
Rosy Song | 51ef2e7 | 2019-03-16 09:24:50 +0800 | [diff] [blame] | 668 | priv->model == AG7XXX_MODEL_AG953X || |
| 669 | priv->model == AG7XXX_MODEL_AG956X) { |
Rosy Song | 361c69e | 2019-02-05 17:50:44 +0800 | [diff] [blame] | 670 | writel(AG7XXX_ETH_MII_MGMT_CFG_RESET | reg, |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 671 | priv->regs + AG7XXX_ETH_MII_MGMT_CFG); |
Rosy Song | 361c69e | 2019-02-05 17:50:44 +0800 | [diff] [blame] | 672 | writel(reg, priv->regs + AG7XXX_ETH_MII_MGMT_CFG); |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 673 | return 0; |
| 674 | } |
| 675 | |
| 676 | for (i = 0; i < 10; i++) { |
| 677 | writel(AG7XXX_ETH_MII_MGMT_CFG_RESET | div, |
| 678 | priv->regs + AG7XXX_ETH_MII_MGMT_CFG); |
| 679 | writel(div, priv->regs + AG7XXX_ETH_MII_MGMT_CFG); |
| 680 | |
| 681 | /* Check the switch */ |
| 682 | ret = ag7xxx_switch_reg_read(priv->bus, 0x10c, ®); |
| 683 | if (ret) |
| 684 | continue; |
| 685 | |
| 686 | if (reg != 0x18007fff) |
| 687 | continue; |
| 688 | |
| 689 | return 0; |
| 690 | } |
| 691 | |
| 692 | return -EINVAL; |
| 693 | } |
| 694 | |
| 695 | static int ag933x_phy_setup_wan(struct udevice *dev) |
| 696 | { |
| 697 | struct ar7xxx_eth_priv *priv = dev_get_priv(dev); |
| 698 | |
| 699 | /* Configure switch port 4 (GMAC0) */ |
| 700 | return ag7xxx_mdio_write(priv->bus, 4, 0, MII_BMCR, 0x9000); |
| 701 | } |
| 702 | |
| 703 | static int ag933x_phy_setup_lan(struct udevice *dev) |
| 704 | { |
| 705 | struct ar7xxx_eth_priv *priv = dev_get_priv(dev); |
| 706 | int i, ret; |
| 707 | u32 reg; |
| 708 | |
| 709 | /* Reset the switch */ |
| 710 | ret = ag7xxx_switch_reg_read(priv->bus, 0, ®); |
| 711 | if (ret) |
| 712 | return ret; |
| 713 | reg |= BIT(31); |
| 714 | ret = ag7xxx_switch_reg_write(priv->bus, 0, reg); |
| 715 | if (ret) |
| 716 | return ret; |
| 717 | |
| 718 | do { |
| 719 | ret = ag7xxx_switch_reg_read(priv->bus, 0, ®); |
| 720 | if (ret) |
| 721 | return ret; |
| 722 | } while (reg & BIT(31)); |
| 723 | |
| 724 | /* Configure switch ports 0...3 (GMAC1) */ |
| 725 | for (i = 0; i < 4; i++) { |
| 726 | ret = ag7xxx_mdio_write(priv->bus, 0x4, 0, MII_BMCR, 0x9000); |
| 727 | if (ret) |
| 728 | return ret; |
| 729 | } |
| 730 | |
| 731 | /* Enable CPU port */ |
| 732 | ret = ag7xxx_switch_reg_write(priv->bus, 0x78, BIT(8)); |
| 733 | if (ret) |
| 734 | return ret; |
| 735 | |
| 736 | for (i = 0; i < 4; i++) { |
| 737 | ret = ag7xxx_switch_reg_write(priv->bus, i * 0x100, BIT(9)); |
| 738 | if (ret) |
| 739 | return ret; |
| 740 | } |
| 741 | |
| 742 | /* QM Control */ |
| 743 | ret = ag7xxx_switch_reg_write(priv->bus, 0x38, 0xc000050e); |
| 744 | if (ret) |
| 745 | return ret; |
| 746 | |
| 747 | /* Disable Atheros header */ |
| 748 | ret = ag7xxx_switch_reg_write(priv->bus, 0x104, 0x4004); |
| 749 | if (ret) |
| 750 | return ret; |
| 751 | |
| 752 | /* Tag priority mapping */ |
| 753 | ret = ag7xxx_switch_reg_write(priv->bus, 0x70, 0xfa50); |
| 754 | if (ret) |
| 755 | return ret; |
| 756 | |
| 757 | /* Enable ARP packets to the CPU */ |
| 758 | ret = ag7xxx_switch_reg_read(priv->bus, 0x5c, ®); |
| 759 | if (ret) |
| 760 | return ret; |
| 761 | reg |= 0x100000; |
| 762 | ret = ag7xxx_switch_reg_write(priv->bus, 0x5c, reg); |
| 763 | if (ret) |
| 764 | return ret; |
| 765 | |
Rosy Song | 361c69e | 2019-02-05 17:50:44 +0800 | [diff] [blame] | 766 | return 0; |
| 767 | } |
| 768 | |
| 769 | static int ag953x_phy_setup_wan(struct udevice *dev) |
| 770 | { |
| 771 | int ret; |
| 772 | u32 reg = 0; |
| 773 | struct ar7xxx_eth_priv *priv = dev_get_priv(dev); |
| 774 | |
| 775 | /* Set wan port connect to GE0 */ |
| 776 | ret = ag7xxx_switch_reg_read(priv->bus, 0x8, ®); |
| 777 | if (ret) |
| 778 | return ret; |
| 779 | |
| 780 | ret = ag7xxx_switch_reg_write(priv->bus, 0x8, reg | BIT(28)); |
| 781 | if (ret) |
| 782 | return ret; |
| 783 | |
| 784 | /* Configure switch port 4 (GMAC0) */ |
| 785 | ret = ag7xxx_switch_write(priv->bus, 4, MII_BMCR, 0x9000); |
| 786 | if (ret) |
| 787 | return ret; |
| 788 | |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 789 | return 0; |
| 790 | } |
| 791 | |
Rosy Song | 361c69e | 2019-02-05 17:50:44 +0800 | [diff] [blame] | 792 | static int ag953x_phy_setup_lan(struct udevice *dev) |
| 793 | { |
| 794 | struct ar7xxx_eth_priv *priv = dev_get_priv(dev); |
| 795 | int i, ret; |
| 796 | u32 reg = 0; |
| 797 | |
| 798 | /* Reset the switch */ |
| 799 | ret = ag7xxx_switch_reg_read(priv->bus, 0, ®); |
| 800 | if (ret) |
| 801 | return ret; |
| 802 | |
| 803 | ret = ag7xxx_switch_reg_write(priv->bus, 0, reg | BIT(31)); |
| 804 | if (ret) |
| 805 | return ret; |
| 806 | |
| 807 | do { |
| 808 | ret = ag7xxx_switch_reg_read(priv->bus, 0, ®); |
| 809 | if (ret) |
| 810 | return ret; |
| 811 | } while (reg & BIT(31)); |
| 812 | |
| 813 | ret = ag7xxx_switch_reg_write(priv->bus, 0x100, 0x4e); |
| 814 | if (ret) |
| 815 | return ret; |
| 816 | |
| 817 | /* Set GMII mode */ |
| 818 | ret = ag7xxx_switch_reg_read(priv->bus, 0x4, ®); |
| 819 | if (ret) |
| 820 | return ret; |
| 821 | |
| 822 | ret = ag7xxx_switch_reg_write(priv->bus, 0x4, reg | BIT(6)); |
| 823 | if (ret) |
| 824 | return ret; |
| 825 | |
| 826 | /* Configure switch ports 0...4 (GMAC1) */ |
| 827 | for (i = 0; i < 5; i++) { |
| 828 | ret = ag7xxx_switch_write(priv->bus, i, MII_BMCR, 0x9000); |
| 829 | if (ret) |
| 830 | return ret; |
| 831 | } |
| 832 | |
| 833 | for (i = 0; i < 5; i++) { |
| 834 | ret = ag7xxx_switch_reg_write(priv->bus, (i + 2) * 0x100, BIT(9)); |
| 835 | if (ret) |
| 836 | return ret; |
| 837 | } |
| 838 | |
| 839 | /* QM Control */ |
| 840 | ret = ag7xxx_switch_reg_write(priv->bus, 0x38, 0xc000050e); |
| 841 | if (ret) |
| 842 | return ret; |
| 843 | |
| 844 | /* Disable Atheros header */ |
| 845 | ret = ag7xxx_switch_reg_write(priv->bus, 0x104, 0x4004); |
| 846 | if (ret) |
| 847 | return ret; |
| 848 | |
| 849 | /* Tag priority mapping */ |
| 850 | ret = ag7xxx_switch_reg_write(priv->bus, 0x70, 0xfa50); |
| 851 | if (ret) |
| 852 | return ret; |
| 853 | |
| 854 | /* Enable ARP packets to the CPU */ |
| 855 | ret = ag7xxx_switch_reg_read(priv->bus, 0x5c, ®); |
| 856 | if (ret) |
| 857 | return ret; |
| 858 | |
| 859 | ret = ag7xxx_switch_reg_write(priv->bus, 0x5c, reg | 0x100000); |
| 860 | if (ret) |
| 861 | return ret; |
| 862 | |
| 863 | /* Enable broadcast packets to the CPU */ |
| 864 | ret = ag7xxx_switch_reg_read(priv->bus, 0x2c, ®); |
| 865 | if (ret) |
| 866 | return ret; |
| 867 | |
| 868 | ret = ag7xxx_switch_reg_write(priv->bus, 0x2c, reg | BIT(25) | BIT(26)); |
| 869 | if (ret) |
| 870 | return ret; |
| 871 | |
| 872 | return 0; |
| 873 | } |
| 874 | |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 875 | static int ag933x_phy_setup_reset_set(struct udevice *dev, int port) |
| 876 | { |
| 877 | struct ar7xxx_eth_priv *priv = dev_get_priv(dev); |
| 878 | int ret; |
| 879 | |
Rosy Song | 51ef2e7 | 2019-03-16 09:24:50 +0800 | [diff] [blame] | 880 | if (priv->model == AG7XXX_MODEL_AG953X || |
| 881 | priv->model == AG7XXX_MODEL_AG956X) { |
Rosy Song | 361c69e | 2019-02-05 17:50:44 +0800 | [diff] [blame] | 882 | ret = ag7xxx_switch_write(priv->bus, port, MII_ADVERTISE, |
| 883 | ADVERTISE_ALL); |
| 884 | } else { |
| 885 | ret = ag7xxx_mdio_write(priv->bus, port, 0, MII_ADVERTISE, |
| 886 | ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | |
| 887 | ADVERTISE_PAUSE_ASYM); |
| 888 | } |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 889 | if (ret) |
| 890 | return ret; |
| 891 | |
| 892 | if (priv->model == AG7XXX_MODEL_AG934X) { |
| 893 | ret = ag7xxx_mdio_write(priv->bus, port, 0, MII_CTRL1000, |
| 894 | ADVERTISE_1000FULL); |
| 895 | if (ret) |
| 896 | return ret; |
Rosy Song | 51ef2e7 | 2019-03-16 09:24:50 +0800 | [diff] [blame] | 897 | } else if (priv->model == AG7XXX_MODEL_AG956X) { |
| 898 | ret = ag7xxx_switch_write(priv->bus, port, MII_CTRL1000, |
| 899 | ADVERTISE_1000FULL); |
| 900 | if (ret) |
| 901 | return ret; |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 902 | } |
| 903 | |
Rosy Song | 51ef2e7 | 2019-03-16 09:24:50 +0800 | [diff] [blame] | 904 | if (priv->model == AG7XXX_MODEL_AG953X || |
| 905 | priv->model == AG7XXX_MODEL_AG956X) |
Rosy Song | 361c69e | 2019-02-05 17:50:44 +0800 | [diff] [blame] | 906 | return ag7xxx_switch_write(priv->bus, port, MII_BMCR, |
| 907 | BMCR_ANENABLE | BMCR_RESET); |
| 908 | |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 909 | return ag7xxx_mdio_write(priv->bus, port, 0, MII_BMCR, |
| 910 | BMCR_ANENABLE | BMCR_RESET); |
| 911 | } |
| 912 | |
| 913 | static int ag933x_phy_setup_reset_fin(struct udevice *dev, int port) |
| 914 | { |
| 915 | struct ar7xxx_eth_priv *priv = dev_get_priv(dev); |
| 916 | int ret; |
Rosy Song | 361c69e | 2019-02-05 17:50:44 +0800 | [diff] [blame] | 917 | u16 reg; |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 918 | |
Rosy Song | 51ef2e7 | 2019-03-16 09:24:50 +0800 | [diff] [blame] | 919 | if (priv->model == AG7XXX_MODEL_AG953X || |
| 920 | priv->model == AG7XXX_MODEL_AG956X) { |
Rosy Song | 361c69e | 2019-02-05 17:50:44 +0800 | [diff] [blame] | 921 | do { |
| 922 | ret = ag7xxx_switch_read(priv->bus, port, MII_BMCR, ®); |
| 923 | if (ret < 0) |
| 924 | return ret; |
| 925 | mdelay(10); |
| 926 | } while (reg & BMCR_RESET); |
| 927 | } else { |
| 928 | do { |
| 929 | ret = ag7xxx_mdio_read(priv->bus, port, 0, MII_BMCR); |
| 930 | if (ret < 0) |
| 931 | return ret; |
| 932 | mdelay(10); |
| 933 | } while (ret & BMCR_RESET); |
| 934 | } |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 935 | |
| 936 | return 0; |
| 937 | } |
| 938 | |
| 939 | static int ag933x_phy_setup_common(struct udevice *dev) |
| 940 | { |
| 941 | struct ar7xxx_eth_priv *priv = dev_get_priv(dev); |
| 942 | int i, ret, phymax; |
Rosy Song | 361c69e | 2019-02-05 17:50:44 +0800 | [diff] [blame] | 943 | u16 reg; |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 944 | |
| 945 | if (priv->model == AG7XXX_MODEL_AG933X) |
| 946 | phymax = 4; |
Rosy Song | 361c69e | 2019-02-05 17:50:44 +0800 | [diff] [blame] | 947 | else if (priv->model == AG7XXX_MODEL_AG934X || |
Rosy Song | 51ef2e7 | 2019-03-16 09:24:50 +0800 | [diff] [blame] | 948 | priv->model == AG7XXX_MODEL_AG953X || |
| 949 | priv->model == AG7XXX_MODEL_AG956X) |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 950 | phymax = 5; |
| 951 | else |
| 952 | return -EINVAL; |
| 953 | |
| 954 | if (priv->interface == PHY_INTERFACE_MODE_RMII) { |
| 955 | ret = ag933x_phy_setup_reset_set(dev, phymax); |
| 956 | if (ret) |
| 957 | return ret; |
| 958 | |
| 959 | ret = ag933x_phy_setup_reset_fin(dev, phymax); |
| 960 | if (ret) |
| 961 | return ret; |
| 962 | |
| 963 | /* Read out link status */ |
Rosy Song | 361c69e | 2019-02-05 17:50:44 +0800 | [diff] [blame] | 964 | if (priv->model == AG7XXX_MODEL_AG953X) |
| 965 | ret = ag7xxx_switch_read(priv->bus, phymax, MII_MIPSCR, ®); |
| 966 | else |
| 967 | ret = ag7xxx_mdio_read(priv->bus, phymax, 0, MII_MIPSCR); |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 968 | if (ret < 0) |
| 969 | return ret; |
| 970 | |
| 971 | return 0; |
| 972 | } |
| 973 | |
| 974 | /* Switch ports */ |
| 975 | for (i = 0; i < phymax; i++) { |
| 976 | ret = ag933x_phy_setup_reset_set(dev, i); |
| 977 | if (ret) |
| 978 | return ret; |
| 979 | } |
| 980 | |
| 981 | for (i = 0; i < phymax; i++) { |
| 982 | ret = ag933x_phy_setup_reset_fin(dev, i); |
| 983 | if (ret) |
| 984 | return ret; |
| 985 | } |
| 986 | |
| 987 | for (i = 0; i < phymax; i++) { |
| 988 | /* Read out link status */ |
Rosy Song | 51ef2e7 | 2019-03-16 09:24:50 +0800 | [diff] [blame] | 989 | if (priv->model == AG7XXX_MODEL_AG953X || |
| 990 | priv->model == AG7XXX_MODEL_AG956X) |
Rosy Song | 361c69e | 2019-02-05 17:50:44 +0800 | [diff] [blame] | 991 | ret = ag7xxx_switch_read(priv->bus, i, MII_MIPSCR, ®); |
| 992 | else |
| 993 | ret = ag7xxx_mdio_read(priv->bus, i, 0, MII_MIPSCR); |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 994 | if (ret < 0) |
| 995 | return ret; |
| 996 | } |
| 997 | |
| 998 | return 0; |
| 999 | } |
| 1000 | |
| 1001 | static int ag934x_phy_setup(struct udevice *dev) |
| 1002 | { |
| 1003 | struct ar7xxx_eth_priv *priv = dev_get_priv(dev); |
| 1004 | int i, ret; |
| 1005 | u32 reg; |
| 1006 | |
| 1007 | ret = ag7xxx_switch_reg_write(priv->bus, 0x624, 0x7f7f7f7f); |
| 1008 | if (ret) |
| 1009 | return ret; |
| 1010 | ret = ag7xxx_switch_reg_write(priv->bus, 0x10, 0x40000000); |
| 1011 | if (ret) |
| 1012 | return ret; |
| 1013 | ret = ag7xxx_switch_reg_write(priv->bus, 0x4, 0x07600000); |
| 1014 | if (ret) |
| 1015 | return ret; |
| 1016 | ret = ag7xxx_switch_reg_write(priv->bus, 0xc, 0x01000000); |
| 1017 | if (ret) |
| 1018 | return ret; |
| 1019 | ret = ag7xxx_switch_reg_write(priv->bus, 0x7c, 0x0000007e); |
| 1020 | if (ret) |
| 1021 | return ret; |
| 1022 | |
| 1023 | /* AR8327/AR8328 v1.0 fixup */ |
| 1024 | ret = ag7xxx_switch_reg_read(priv->bus, 0, ®); |
| 1025 | if (ret) |
| 1026 | return ret; |
| 1027 | if ((reg & 0xffff) == 0x1201) { |
| 1028 | for (i = 0; i < 5; i++) { |
| 1029 | ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1d, 0x0); |
| 1030 | if (ret) |
| 1031 | return ret; |
| 1032 | ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1e, 0x02ea); |
| 1033 | if (ret) |
| 1034 | return ret; |
| 1035 | ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1d, 0x3d); |
| 1036 | if (ret) |
| 1037 | return ret; |
| 1038 | ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1e, 0x68a0); |
| 1039 | if (ret) |
| 1040 | return ret; |
| 1041 | } |
| 1042 | } |
| 1043 | |
| 1044 | ret = ag7xxx_switch_reg_read(priv->bus, 0x66c, ®); |
| 1045 | if (ret) |
| 1046 | return ret; |
| 1047 | reg &= ~0x70000; |
| 1048 | ret = ag7xxx_switch_reg_write(priv->bus, 0x66c, reg); |
| 1049 | if (ret) |
| 1050 | return ret; |
| 1051 | |
| 1052 | return 0; |
| 1053 | } |
| 1054 | |
Rosy Song | 51ef2e7 | 2019-03-16 09:24:50 +0800 | [diff] [blame] | 1055 | static int ag956x_phy_setup(struct udevice *dev) |
| 1056 | { |
| 1057 | struct ar7xxx_eth_priv *priv = dev_get_priv(dev); |
| 1058 | int i, ret; |
| 1059 | u32 reg, ctrl; |
| 1060 | |
| 1061 | ret = ag7xxx_switch_reg_read(priv->bus, 0x0, ®); |
| 1062 | if (ret) |
| 1063 | return ret; |
| 1064 | if ((reg & 0xffff) >= 0x1301) |
| 1065 | ctrl = 0xc74164de; |
| 1066 | else |
| 1067 | ctrl = 0xc74164d0; |
| 1068 | |
| 1069 | ret = ag7xxx_switch_reg_write(priv->bus, 0x4, BIT(7)); |
| 1070 | if (ret) |
| 1071 | return ret; |
| 1072 | |
| 1073 | ret = ag7xxx_switch_reg_write(priv->bus, 0xe0, ctrl); |
| 1074 | if (ret) |
| 1075 | return ret; |
| 1076 | |
| 1077 | ret = ag7xxx_switch_reg_write(priv->bus, 0x624, 0x7f7f7f7f); |
| 1078 | if (ret) |
| 1079 | return ret; |
| 1080 | |
| 1081 | /* |
| 1082 | * Values suggested by the switch team when s17 in sgmii |
| 1083 | * configuration. 0x10(S17_PWS_REG) = 0x602613a0 |
| 1084 | */ |
| 1085 | ret = ag7xxx_switch_reg_write(priv->bus, 0x10, 0x602613a0); |
| 1086 | if (ret) |
| 1087 | return ret; |
| 1088 | |
| 1089 | ret = ag7xxx_switch_reg_write(priv->bus, 0x7c, 0x0000007e); |
| 1090 | if (ret) |
| 1091 | return ret; |
| 1092 | |
| 1093 | /* AR8337/AR8334 v1.0 fixup */ |
| 1094 | ret = ag7xxx_switch_reg_read(priv->bus, 0, ®); |
| 1095 | if (ret) |
| 1096 | return ret; |
| 1097 | if ((reg & 0xffff) == 0x1301) { |
| 1098 | for (i = 0; i < 5; i++) { |
| 1099 | /* Turn on Gigabit clock */ |
| 1100 | ret = ag7xxx_switch_write(priv->bus, i, 0x1d, 0x3d); |
| 1101 | if (ret) |
| 1102 | return ret; |
| 1103 | ret = ag7xxx_switch_write(priv->bus, i, 0x1e, 0x6820); |
| 1104 | if (ret) |
| 1105 | return ret; |
| 1106 | } |
| 1107 | } |
| 1108 | |
| 1109 | return 0; |
| 1110 | } |
| 1111 | |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 1112 | static int ag7xxx_mac_probe(struct udevice *dev) |
| 1113 | { |
| 1114 | struct ar7xxx_eth_priv *priv = dev_get_priv(dev); |
| 1115 | int ret; |
| 1116 | |
| 1117 | ag7xxx_hw_setup(dev); |
| 1118 | ret = ag7xxx_mii_setup(dev); |
| 1119 | if (ret) |
| 1120 | return ret; |
| 1121 | |
| 1122 | ag7xxx_eth_write_hwaddr(dev); |
| 1123 | |
| 1124 | if (priv->model == AG7XXX_MODEL_AG933X) { |
| 1125 | if (priv->interface == PHY_INTERFACE_MODE_RMII) |
| 1126 | ret = ag933x_phy_setup_wan(dev); |
| 1127 | else |
| 1128 | ret = ag933x_phy_setup_lan(dev); |
Rosy Song | 361c69e | 2019-02-05 17:50:44 +0800 | [diff] [blame] | 1129 | } else if (priv->model == AG7XXX_MODEL_AG953X) { |
| 1130 | if (priv->interface == PHY_INTERFACE_MODE_RMII) |
| 1131 | ret = ag953x_phy_setup_wan(dev); |
| 1132 | else |
| 1133 | ret = ag953x_phy_setup_lan(dev); |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 1134 | } else if (priv->model == AG7XXX_MODEL_AG934X) { |
| 1135 | ret = ag934x_phy_setup(dev); |
Rosy Song | 51ef2e7 | 2019-03-16 09:24:50 +0800 | [diff] [blame] | 1136 | } else if (priv->model == AG7XXX_MODEL_AG956X) { |
| 1137 | ret = ag956x_phy_setup(dev); |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 1138 | } else { |
| 1139 | return -EINVAL; |
| 1140 | } |
| 1141 | |
| 1142 | if (ret) |
| 1143 | return ret; |
| 1144 | |
| 1145 | return ag933x_phy_setup_common(dev); |
| 1146 | } |
| 1147 | |
| 1148 | static int ag7xxx_mdio_probe(struct udevice *dev) |
| 1149 | { |
| 1150 | struct ar7xxx_eth_priv *priv = dev_get_priv(dev); |
| 1151 | struct mii_dev *bus = mdio_alloc(); |
| 1152 | |
| 1153 | if (!bus) |
| 1154 | return -ENOMEM; |
| 1155 | |
| 1156 | bus->read = ag7xxx_mdio_read; |
| 1157 | bus->write = ag7xxx_mdio_write; |
| 1158 | snprintf(bus->name, sizeof(bus->name), dev->name); |
| 1159 | |
| 1160 | bus->priv = (void *)priv; |
| 1161 | |
| 1162 | return mdio_register(bus); |
| 1163 | } |
| 1164 | |
| 1165 | static int ag7xxx_get_phy_iface_offset(struct udevice *dev) |
| 1166 | { |
| 1167 | int offset; |
| 1168 | |
Simon Glass | dd79d6e | 2017-01-17 16:52:55 -0700 | [diff] [blame] | 1169 | offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev), "phy"); |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 1170 | if (offset <= 0) { |
| 1171 | debug("%s: PHY OF node not found (ret=%i)\n", __func__, offset); |
| 1172 | return -EINVAL; |
| 1173 | } |
| 1174 | |
| 1175 | offset = fdt_parent_offset(gd->fdt_blob, offset); |
| 1176 | if (offset <= 0) { |
| 1177 | debug("%s: PHY OF node parent MDIO bus not found (ret=%i)\n", |
| 1178 | __func__, offset); |
| 1179 | return -EINVAL; |
| 1180 | } |
| 1181 | |
| 1182 | offset = fdt_parent_offset(gd->fdt_blob, offset); |
| 1183 | if (offset <= 0) { |
| 1184 | debug("%s: PHY MDIO OF node parent MAC not found (ret=%i)\n", |
| 1185 | __func__, offset); |
| 1186 | return -EINVAL; |
| 1187 | } |
| 1188 | |
| 1189 | return offset; |
| 1190 | } |
| 1191 | |
| 1192 | static int ag7xxx_eth_probe(struct udevice *dev) |
| 1193 | { |
| 1194 | struct eth_pdata *pdata = dev_get_platdata(dev); |
| 1195 | struct ar7xxx_eth_priv *priv = dev_get_priv(dev); |
| 1196 | void __iomem *iobase, *phyiobase; |
| 1197 | int ret, phyreg; |
| 1198 | |
| 1199 | /* Decoding of convoluted PHY wiring on Atheros MIPS. */ |
| 1200 | ret = ag7xxx_get_phy_iface_offset(dev); |
| 1201 | if (ret <= 0) |
| 1202 | return ret; |
| 1203 | phyreg = fdtdec_get_int(gd->fdt_blob, ret, "reg", -1); |
| 1204 | |
| 1205 | iobase = map_physmem(pdata->iobase, 0x200, MAP_NOCACHE); |
| 1206 | phyiobase = map_physmem(phyreg, 0x200, MAP_NOCACHE); |
| 1207 | |
| 1208 | debug("%s, iobase=%p, phyiobase=%p, priv=%p\n", |
| 1209 | __func__, iobase, phyiobase, priv); |
| 1210 | priv->regs = iobase; |
| 1211 | priv->phyregs = phyiobase; |
| 1212 | priv->interface = pdata->phy_interface; |
| 1213 | priv->model = dev_get_driver_data(dev); |
| 1214 | |
| 1215 | ret = ag7xxx_mdio_probe(dev); |
| 1216 | if (ret) |
| 1217 | return ret; |
| 1218 | |
| 1219 | priv->bus = miiphy_get_dev_by_name(dev->name); |
| 1220 | |
| 1221 | ret = ag7xxx_mac_probe(dev); |
| 1222 | debug("%s, ret=%d\n", __func__, ret); |
| 1223 | |
| 1224 | return ret; |
| 1225 | } |
| 1226 | |
| 1227 | static int ag7xxx_eth_remove(struct udevice *dev) |
| 1228 | { |
| 1229 | struct ar7xxx_eth_priv *priv = dev_get_priv(dev); |
| 1230 | |
| 1231 | free(priv->phydev); |
| 1232 | mdio_unregister(priv->bus); |
| 1233 | mdio_free(priv->bus); |
| 1234 | |
| 1235 | return 0; |
| 1236 | } |
| 1237 | |
| 1238 | static const struct eth_ops ag7xxx_eth_ops = { |
| 1239 | .start = ag7xxx_eth_start, |
| 1240 | .send = ag7xxx_eth_send, |
| 1241 | .recv = ag7xxx_eth_recv, |
| 1242 | .free_pkt = ag7xxx_eth_free_pkt, |
| 1243 | .stop = ag7xxx_eth_stop, |
| 1244 | .write_hwaddr = ag7xxx_eth_write_hwaddr, |
| 1245 | }; |
| 1246 | |
| 1247 | static int ag7xxx_eth_ofdata_to_platdata(struct udevice *dev) |
| 1248 | { |
| 1249 | struct eth_pdata *pdata = dev_get_platdata(dev); |
| 1250 | const char *phy_mode; |
| 1251 | int ret; |
| 1252 | |
Simon Glass | ba1dea4 | 2017-05-17 17:18:05 -0600 | [diff] [blame] | 1253 | pdata->iobase = devfdt_get_addr(dev); |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 1254 | pdata->phy_interface = -1; |
| 1255 | |
| 1256 | /* Decoding of convoluted PHY wiring on Atheros MIPS. */ |
| 1257 | ret = ag7xxx_get_phy_iface_offset(dev); |
| 1258 | if (ret <= 0) |
| 1259 | return ret; |
| 1260 | |
| 1261 | phy_mode = fdt_getprop(gd->fdt_blob, ret, "phy-mode", NULL); |
| 1262 | if (phy_mode) |
| 1263 | pdata->phy_interface = phy_get_interface_by_name(phy_mode); |
| 1264 | if (pdata->phy_interface == -1) { |
| 1265 | debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); |
| 1266 | return -EINVAL; |
| 1267 | } |
| 1268 | |
| 1269 | return 0; |
| 1270 | } |
| 1271 | |
| 1272 | static const struct udevice_id ag7xxx_eth_ids[] = { |
| 1273 | { .compatible = "qca,ag933x-mac", .data = AG7XXX_MODEL_AG933X }, |
| 1274 | { .compatible = "qca,ag934x-mac", .data = AG7XXX_MODEL_AG934X }, |
Rosy Song | 361c69e | 2019-02-05 17:50:44 +0800 | [diff] [blame] | 1275 | { .compatible = "qca,ag953x-mac", .data = AG7XXX_MODEL_AG953X }, |
Rosy Song | 51ef2e7 | 2019-03-16 09:24:50 +0800 | [diff] [blame] | 1276 | { .compatible = "qca,ag956x-mac", .data = AG7XXX_MODEL_AG956X }, |
Marek Vasut | 0a3d0e1 | 2016-05-24 23:29:09 +0200 | [diff] [blame] | 1277 | { } |
| 1278 | }; |
| 1279 | |
| 1280 | U_BOOT_DRIVER(eth_ag7xxx) = { |
| 1281 | .name = "eth_ag7xxx", |
| 1282 | .id = UCLASS_ETH, |
| 1283 | .of_match = ag7xxx_eth_ids, |
| 1284 | .ofdata_to_platdata = ag7xxx_eth_ofdata_to_platdata, |
| 1285 | .probe = ag7xxx_eth_probe, |
| 1286 | .remove = ag7xxx_eth_remove, |
| 1287 | .ops = &ag7xxx_eth_ops, |
| 1288 | .priv_auto_alloc_size = sizeof(struct ar7xxx_eth_priv), |
| 1289 | .platdata_auto_alloc_size = sizeof(struct eth_pdata), |
| 1290 | .flags = DM_FLAG_ALLOC_PRIV_DMA, |
| 1291 | }; |