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git01.mediatek.com / filogic / uboot / 2e83487171a7d1ebce20cb15ca9fb3c0d9cd6cd7 / . / dts / upstream / src / arm / sunplus / sunplus-sp7021.dtsi
blob: ae9bbe0320b8da4ae1139d4be40ebd1408e4fccd [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for Sunplus SP7021
4 *
5 * Copyright (C) 2021 Sunplus Technology Co.
6 */
7
8#include <dt-bindings/clock/sunplus,sp7021-clkc.h>
9#include <dt-bindings/interrupt-controller/irq.h>
10#include <dt-bindings/reset/sunplus,sp7021-reset.h>
11#include <dt-bindings/pinctrl/sppctl-sp7021.h>
12#include <dt-bindings/gpio/gpio.h>
13
14#define XTAL 27000000
15
16/ {
17 compatible = "sunplus,sp7021";
18 model = "Sunplus SP7021";
19
20 clocks {
21 extclk: osc0 {
22 compatible = "fixed-clock";
23 #clock-cells = <0>;
24 clock-frequency = <XTAL>;
25 clock-output-names = "extclk";
26 };
27 };
28
29 soc@9c000000 {
30 compatible = "simple-bus";
31 #address-cells = <1>;
32 #size-cells = <1>;
33 ranges = <0 0x9c000000 0x400000>;
34 interrupt-parent = <&intc>;
35
36 clkc: clock-controller@4 {
37 compatible = "sunplus,sp7021-clkc";
38 reg = <0x4 0x28>,
39 <0x200 0x44>,
40 <0x268 0x04>;
41 clocks = <&extclk>;
42 #clock-cells = <1>;
43 };
44
45 intc: interrupt-controller@780 {
46 compatible = "sunplus,sp7021-intc";
47 reg = <0x780 0x80>, <0xa80 0x80>;
48 interrupt-controller;
49 #interrupt-cells = <2>;
50 };
51
52 otp: otp@af00 {
53 compatible = "sunplus,sp7021-ocotp";
54 reg = <0xaf00 0x34>, <0xaf80 0x58>;
55 reg-names = "hb_gpio", "otprx";
56 clocks = <&clkc CLK_OTPRX>;
57 resets = <&rstc RST_OTPRX>;
58 #address-cells = <1>;
59 #size-cells = <1>;
60
61 therm_calib: thermal-calibration@14 {
62 reg = <0x14 0x3>;
63 };
64 disc_vol: disconnect-voltage@18 {
65 reg = <0x18 0x2>;
66 };
67 mac_addr0: mac-address0@34 {
68 reg = <0x34 0x6>;
69 };
70 mac_addr1: mac-address1@3a {
71 reg = <0x3a 0x6>;
72 };
73 };
74
75 pctl: pinctrl@100 {
76 compatible = "sunplus,sp7021-pctl";
77 reg = <0x100 0x100>,
78 <0x300 0x100>,
79 <0x32e4 0x1C>,
80 <0x80 0x20>;
81 reg-names = "moon2", "gpioxt", "first", "moon1";
82 gpio-controller;
83 #gpio-cells = <2>;
84 clocks = <&clkc CLK_GPIO>;
85 resets = <&rstc RST_GPIO>;
86
87 emac_pins: pinmux-emac-pins {
88 sunplus,pins = <
89 SPPCTL_IOPAD(49,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_CLK_OUT,0)
90 SPPCTL_IOPAD(44,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_MAC_SMI_MDC,0)
91 SPPCTL_IOPAD(43,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_MAC_SMI_MDIO,0)
92 SPPCTL_IOPAD(52,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXEN,0)
93 SPPCTL_IOPAD(50,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXD0,0)
94 SPPCTL_IOPAD(51,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXD1,0)
95 SPPCTL_IOPAD(46,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_CRSDV,0)
96 SPPCTL_IOPAD(47,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_RXD0,0)
97 SPPCTL_IOPAD(48,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_RXD1,0)
98 SPPCTL_IOPAD(45,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_RXER,0)
99 SPPCTL_IOPAD(59,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_TXEN,0)
100 SPPCTL_IOPAD(57,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_TXD0,0)
101 SPPCTL_IOPAD(58,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_TXD1,0)
102 SPPCTL_IOPAD(54,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_CRSDV,0)
103 SPPCTL_IOPAD(55,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_RXD0,0)
104 SPPCTL_IOPAD(56,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_RXD1,0)
105 SPPCTL_IOPAD(53,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_RXER,0)
106 >;
107 sunplus,zerofunc = <
108 MUXF_L2SW_LED_FLASH0
109 MUXF_L2SW_LED_FLASH1
110 MUXF_L2SW_LED_ON0
111 MUXF_L2SW_LED_ON1
112 MUXF_DAISY_MODE
113 >;
114 };
115
116 emmc_pins: pinmux-emmc-pins {
117 function = "CARD0_EMMC";
118 groups = "CARD0_EMMC";
119 };
120
121 leds_pins: pinmux-leds-pins {
122 sunplus,pins = < SPPCTL_IOPAD(0,SPPCTL_PCTL_G_GPIO,0,SPPCTL_PCTL_L_OUT) >;
123 };
124
125 sdcard_pins: pinmux-sdcard-pins {
126 function = "SD_CARD";
127 groups = "SD_CARD";
128 sunplus,pins = < SPPCTL_IOPAD(91, SPPCTL_PCTL_G_GPIO, 0, 0) >;
129 };
130
131 spi0_pins: pinmux-spi0-pins {
132 sunplus,pins = <
133 SPPCTL_IOPAD(26,SPPCTL_PCTL_G_GPIO,0,0)
134 SPPCTL_IOPAD(28,SPPCTL_PCTL_G_GPIO,0,0)
135 SPPCTL_IOPAD(23,SPPCTL_PCTL_G_PMUX,MUXF_SPI0S_DO,0)
136 SPPCTL_IOPAD(25,SPPCTL_PCTL_G_PMUX,MUXF_SPI0S_DI,0)
137 SPPCTL_IOPAD(27,SPPCTL_PCTL_G_PMUX,MUXF_SPI0S_CLK,0)
138 >;
139 };
140
141 uart0_pins: pinmux-uart0-pins {
142 function = "UA0";
143 groups = "UA0";
144 };
145
146 uart1_pins: pinmux-uart1-pins {
147 sunplus,pins = <
148 SPPCTL_IOPAD(14,SPPCTL_PCTL_G_PMUX,MUXF_UA4_TX,0)
149 SPPCTL_IOPAD(16,SPPCTL_PCTL_G_PMUX,MUXF_UA4_RX,0)
150 >;
151 };
152
153 uart2_pins: pinmux-uart2-pins {
154 sunplus,pins = <
155 SPPCTL_IOPAD(16,SPPCTL_PCTL_G_PMUX,MUXF_UA2_TX,0)
156 SPPCTL_IOPAD(17,SPPCTL_PCTL_G_PMUX,MUXF_UA2_RX,0)
157 SPPCTL_IOPAD(18,SPPCTL_PCTL_G_PMUX,MUXF_UA2_RTS,0)
158 SPPCTL_IOPAD(19,SPPCTL_PCTL_G_PMUX,MUXF_UA2_CTS,0)
159 >;
160 };
161
162 uart4_pins: pinmux-uart4-pins {
163 sunplus,pins = <
164 SPPCTL_IOPAD(22,SPPCTL_PCTL_G_PMUX,MUXF_UA4_TX,0)
165 SPPCTL_IOPAD(20,SPPCTL_PCTL_G_PMUX,MUXF_UA4_RX,0)
166 SPPCTL_IOPAD(23,SPPCTL_PCTL_G_PMUX,MUXF_UA4_RTS,0)
167 SPPCTL_IOPAD(21,SPPCTL_PCTL_G_PMUX,MUXF_UA4_CTS,0)
168 >;
169 };
170 };
171
172 rstc: reset@54 {
173 compatible = "sunplus,sp7021-reset";
174 reg = <0x54 0x28>;
175 #reset-cells = <1>;
176 };
177
178 rtc: rtc@3a00 {
179 compatible = "sunplus,sp7021-rtc";
180 reg = <0x3a00 0x80>;
181 reg-names = "rtc";
182 clocks = <&clkc CLK_RTC>;
183 resets = <&rstc RST_RTC>;
184 interrupts = <163 IRQ_TYPE_EDGE_RISING>;
185 };
186
187 spi_controller0: spi@2d80 {
188 compatible = "sunplus,sp7021-spi";
189 reg = <0x2d80 0x80>, <0x2e00 0x80>;
190 reg-names = "master", "slave";
191 interrupts = <144 IRQ_TYPE_LEVEL_HIGH>,
192 <146 IRQ_TYPE_LEVEL_HIGH>,
193 <145 IRQ_TYPE_LEVEL_HIGH>;
194 interrupt-names = "dma_w", "master_risc", "slave_risc";
195 clocks = <&clkc CLK_SPI_COMBO_0>;
196 resets = <&rstc RST_SPI_COMBO_0>;
197
198 pinctrl-names = "default";
199 pinctrl-0 = <&spi0_pins>;
200 cs-gpios = <&pctl 26 GPIO_ACTIVE_LOW>,
201 <&pctl 28 GPIO_ACTIVE_LOW>;
202 };
203
204 spi_controller1: spi@f480 {
205 compatible = "sunplus,sp7021-spi";
206 reg = <0xf480 0x80>, <0xf500 0x80>;
207 reg-names = "master", "slave";
208 interrupts = <67 IRQ_TYPE_LEVEL_HIGH>,
209 <69 IRQ_TYPE_LEVEL_HIGH>,
210 <68 IRQ_TYPE_LEVEL_HIGH>;
211 interrupt-names = "dma_w", "master_risc", "slave_risc";
212 clocks = <&clkc CLK_SPI_COMBO_1>;
213 resets = <&rstc RST_SPI_COMBO_1>;
214 status = "disabled";
215 };
216
217 spi_controller2: spi@f600 {
218 compatible = "sunplus,sp7021-spi";
219 reg = <0xf600 0x80>, <0xf680 0x80>;
220 reg-names = "master", "slave";
221 interrupts = <70 IRQ_TYPE_LEVEL_HIGH>,
222 <72 IRQ_TYPE_LEVEL_HIGH>,
223 <71 IRQ_TYPE_LEVEL_HIGH>;
224 interrupt-names = "dma_w", "master_risc", "slave_risc";
225 clocks = <&clkc CLK_SPI_COMBO_2>;
226 resets = <&rstc RST_SPI_COMBO_2>;
227 status = "disabled";
228 };
229
230 spi_controller3: spi@f780 {
231 compatible = "sunplus,sp7021-spi";
232 reg = <0xf780 0x80>, <0xf800 0x80>;
233 reg-names = "master", "slave";
234 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>,
235 <75 IRQ_TYPE_LEVEL_HIGH>,
236 <74 IRQ_TYPE_LEVEL_HIGH>;
237 interrupt-names = "dma_w", "master_risc", "slave_risc";
238 clocks = <&clkc CLK_SPI_COMBO_3>;
239 resets = <&rstc RST_SPI_COMBO_3>;
240 status = "disabled";
241 };
242
243 uart0: serial@900 {
244 compatible = "sunplus,sp7021-uart";
245 reg = <0x900 0x80>;
246 interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
247 clocks = <&clkc CLK_UA0>;
248 resets = <&rstc RST_UA0>;
249 pinctrl-names = "default";
250 pinctrl-0 = <&uart0_pins>;
251 };
252
253 uart1: serial@980 {
254 compatible = "sunplus,sp7021-uart";
255 reg = <0x980 0x80>;
256 interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
257 clocks = <&clkc CLK_UA1>;
258 resets = <&rstc RST_UA1>;
259 pinctrl-names = "default";
260 pinctrl-0 = <&uart1_pins>;
261 status = "disabled";
262 };
263
264 uart2: serial@800 {
265 compatible = "sunplus,sp7021-uart";
266 reg = <0x800 0x80>;
267 interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
268 clocks = <&clkc CLK_UA2>;
269 resets = <&rstc RST_UA2>;
270 pinctrl-names = "default";
271 pinctrl-0 = <&uart2_pins>;
272 status = "disabled";
273 };
274
275 uart3: serial@880 {
276 compatible = "sunplus,sp7021-uart";
277 reg = <0x880 0x80>;
278 interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
279 clocks = <&clkc CLK_UA3>;
280 resets = <&rstc RST_UA3>;
281 status = "disabled";
282 };
283
284 uart4: serial@8780 {
285 compatible = "sunplus,sp7021-uart";
286 reg = <0x8780 0x80>;
287 interrupts = <134 IRQ_TYPE_LEVEL_HIGH>;
288 clocks = <&clkc CLK_UA4>;
289 resets = <&rstc RST_UA4>;
290 pinctrl-names = "default";
291 pinctrl-0 = <&uart4_pins>;
292 status = "disabled";
293 };
294 };
295
296 leds {
297 compatible = "gpio-leds";
298 pinctrl-names = "default";
299 pinctrl-0 = <&leds_pins>;
300 system-led {
301 label = "system-led";
302 gpios = <&pctl 0 GPIO_ACTIVE_HIGH>;
303 default-state = "off";
304 linux,default-trigger = "heartbeat";
305 };
306 };
307};