blob: cfd5479cd7308354b31815a1817aaca25ff79c45 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Peng Fanb11a7342018-01-10 13:20:20 +08002/*
3 * Copyright 2017 NXP
Peng Fanb11a7342018-01-10 13:20:20 +08004 */
5
Peng Fan39945c12018-11-20 10:19:25 +00006#ifndef __ASM_ARCH_IMX8M_REGS_H__
7#define __ASM_ARCH_IMX8M_REGS_H__
Peng Fanb11a7342018-01-10 13:20:20 +08008
Peng Fan00565bf2019-05-09 08:33:55 +00009#define ARCH_MXC
10
Peng Fanb11a7342018-01-10 13:20:20 +080011#include <asm/mach-imx/regs-lcdif.h>
12
Peng Fan2f8c5e12019-08-27 06:25:14 +000013#define ROM_VERSION_A0 IS_ENABLED(CONFIG_IMX8MQ) ? 0x800 : 0x800
14#define ROM_VERSION_B0 IS_ENABLED(CONFIG_IMX8MQ) ? 0x83C : 0x800
Peng Fanb11a7342018-01-10 13:20:20 +080015
Peng Fanc627b302019-08-27 06:25:10 +000016#define M4_BOOTROM_BASE_ADDR 0x007E0000
Peng Fanb11a7342018-01-10 13:20:20 +080017
Peng Fanb11a7342018-01-10 13:20:20 +080018#define GPIO1_BASE_ADDR 0X30200000
19#define GPIO2_BASE_ADDR 0x30210000
20#define GPIO3_BASE_ADDR 0x30220000
21#define GPIO4_BASE_ADDR 0x30230000
22#define GPIO5_BASE_ADDR 0x30240000
Peng Fanb11a7342018-01-10 13:20:20 +080023#define WDOG1_BASE_ADDR 0x30280000
24#define WDOG2_BASE_ADDR 0x30290000
25#define WDOG3_BASE_ADDR 0x302A0000
Peng Fanb11a7342018-01-10 13:20:20 +080026#define IOMUXC_BASE_ADDR 0x30330000
27#define IOMUXC_GPR_BASE_ADDR 0x30340000
28#define OCOTP_BASE_ADDR 0x30350000
29#define ANATOP_BASE_ADDR 0x30360000
Marek Vasutf7b184e2022-09-19 21:37:07 +020030#define SNVS_BASE_ADDR 0x30370000
Peng Fanb11a7342018-01-10 13:20:20 +080031#define CCM_BASE_ADDR 0x30380000
32#define SRC_BASE_ADDR 0x30390000
33#define GPC_BASE_ADDR 0x303A0000
Peng Fanb11a7342018-01-10 13:20:20 +080034
Peng Fanb11a7342018-01-10 13:20:20 +080035#define SYSCNT_RD_BASE_ADDR 0x306A0000
36#define SYSCNT_CMP_BASE_ADDR 0x306B0000
37#define SYSCNT_CTRL_BASE_ADDR 0x306C0000
Peng Fanb11a7342018-01-10 13:20:20 +080038
Peng Fanb11a7342018-01-10 13:20:20 +080039#define UART1_BASE_ADDR 0x30860000
40#define UART3_BASE_ADDR 0x30880000
41#define UART2_BASE_ADDR 0x30890000
Peng Fanb11a7342018-01-10 13:20:20 +080042#define I2C1_BASE_ADDR 0x30A20000
43#define I2C2_BASE_ADDR 0x30A30000
44#define I2C3_BASE_ADDR 0x30A40000
45#define I2C4_BASE_ADDR 0x30A50000
46#define UART4_BASE_ADDR 0x30A60000
Martyn Welchc445dc42022-10-25 10:54:59 +010047#ifdef CONFIG_IMX8MP
48#define I2C5_BASE_ADDR 0x30AD0000
49#define I2C6_BASE_ADDR 0x30AE0000
50#endif
Peng Fanb11a7342018-01-10 13:20:20 +080051#define USDHC1_BASE_ADDR 0x30B40000
52#define USDHC2_BASE_ADDR 0x30B50000
Mamta Shuklad5b90f02022-07-12 14:36:21 +000053#define QSPI0_AMBA_BASE 0x08000000
Martyn Welch8bd54a22022-10-25 10:54:58 +010054#if defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MP)
Peng Fan2f8c5e12019-08-27 06:25:14 +000055#define USDHC3_BASE_ADDR 0x30B60000
56#endif
Marek Vasut86a27482022-04-24 23:44:03 +020057#define UART_BASE_ADDR(n) ( \
58 !!sizeof(struct { \
59 static_assert((n) >= 1 && (n) <= 4); \
60 int pad; \
61 }) * ( \
62 (n) == 1 ? UART1_BASE_ADDR : \
63 (n) == 2 ? UART2_BASE_ADDR : \
64 (n) == 3 ? UART3_BASE_ADDR : \
65 UART4_BASE_ADDR) \
66 )
Peng Fanb11a7342018-01-10 13:20:20 +080067
Peng Fanb11a7342018-01-10 13:20:20 +080068#define TZASC_BASE_ADDR 0x32F80000
Peng Fanb11a7342018-01-10 13:20:20 +080069
Peng Fan2f8c5e12019-08-27 06:25:14 +000070#define MXS_LCDIF_BASE IS_ENABLED(CONFIG_IMX8MQ) ? \
71 0x30320000 : 0x32e00000
Peng Fanb11a7342018-01-10 13:20:20 +080072
73#define SRC_IPS_BASE_ADDR 0x30390000
74#define SRC_DDRC_RCR_ADDR 0x30391000
75#define SRC_DDRC2_RCR_ADDR 0x30391004
76
Michael Trimarchi5175d6c2022-04-12 10:31:32 -030077#define APBH_DMA_ARB_BASE_ADDR 0x33000000
78#define APBH_DMA_ARB_END_ADDR 0x33007FFF
79#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR
80
81#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000)
82#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
83
Marek Vasut2e2fc972022-12-22 01:46:39 +010084#define GICD_BASE 0x38800000
85#define GICR_BASE 0x38880000
86
Peng Fanb11a7342018-01-10 13:20:20 +080087#define DDRC_DDR_SS_GPR0 0x3d000000
88#define DDRC_IPS_BASE_ADDR(X) (0x3d400000 + ((X) * 0x2000000))
89#define DDR_CSD1_BASE_ADDR 0x40000000
90
Peng Fan4f0c97b2020-12-25 16:16:34 +080091#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK 0x70000
Marek Vasutbefffe72021-02-25 22:02:26 +010092#define FEC_QUIRK_ENET_MAC
Peng Fan4f0c97b2020-12-25 16:16:34 +080093
Peng Fan956da002021-03-25 17:30:01 +080094#define CAAM_ARB_BASE_ADDR (0x00100000)
95#define CAAM_ARB_END_ADDR (0x00107FFF)
96#define CAAM_IPS_BASE_ADDR (0x30900000)
Tom Rini376b88a2022-10-28 20:27:13 -040097#define CFG_SYS_FSL_SEC_OFFSET (0)
98#define CFG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \
99 CFG_SYS_FSL_SEC_OFFSET)
100#define CFG_SYS_FSL_JR0_OFFSET (0x1000)
101#define CFG_SYS_FSL_JR0_ADDR (CFG_SYS_FSL_SEC_ADDR + \
102 CFG_SYS_FSL_JR0_OFFSET)
Peng Fanb11a7342018-01-10 13:20:20 +0800103#if !defined(__ASSEMBLY__)
104#include <asm/types.h>
105#include <linux/bitops.h>
106#include <stdbool.h>
107
Andrey Zhizhikin7c2d23a2022-01-24 21:48:09 +0100108#define GPR_TZASC_EN BIT(0)
109#define GPR_TZASC_ID_SWAP_BYPASS BIT(1)
110#define GPR_TZASC_EN_LOCK BIT(16)
111#define GPR_TZASC_ID_SWAP_BYPASS_LOCK BIT(17)
Peng Fanb11a7342018-01-10 13:20:20 +0800112
113#define SRC_SCR_M4_ENABLE_OFFSET 3
114#define SRC_SCR_M4_ENABLE_MASK BIT(3)
115#define SRC_SCR_M4C_NON_SCLR_RST_OFFSET 0
116#define SRC_SCR_M4C_NON_SCLR_RST_MASK BIT(0)
117#define SRC_DDR1_ENABLE_MASK 0x8F000000UL
118#define SRC_DDR2_ENABLE_MASK 0x8F000000UL
119#define SRC_DDR1_RCR_PHY_PWROKIN_N_MASK BIT(3)
120#define SRC_DDR1_RCR_PHY_RESET_MASK BIT(2)
121#define SRC_DDR1_RCR_CORE_RESET_N_MASK BIT(1)
122#define SRC_DDR1_RCR_PRESET_N_MASK BIT(0)
123
Marek Vasutf7b184e2022-09-19 21:37:07 +0200124#define SNVS_LPSR 0x4c
125#define SNVS_LPLVDR 0x64
126#define SNVS_LPPGDR_INIT 0x41736166
127
Peng Fanb11a7342018-01-10 13:20:20 +0800128struct iomuxc_gpr_base_regs {
129 u32 gpr[47];
130};
131
132struct ocotp_regs {
133 u32 ctrl;
134 u32 ctrl_set;
135 u32 ctrl_clr;
136 u32 ctrl_tog;
137 u32 timing;
138 u32 rsvd0[3];
139 u32 data;
140 u32 rsvd1[3];
141 u32 read_ctrl;
142 u32 rsvd2[3];
143 u32 read_fuse_data;
144 u32 rsvd3[3];
145 u32 sw_sticky;
146 u32 rsvd4[3];
147 u32 scs;
148 u32 scs_set;
149 u32 scs_clr;
150 u32 scs_tog;
151 u32 crc_addr;
152 u32 rsvd5[3];
153 u32 crc_value;
154 u32 rsvd6[3];
155 u32 version;
156 u32 rsvd7[0xdb];
157
158 /* fuse banks */
159 struct fuse_bank {
160 u32 fuse_regs[0x10];
161 } bank[0];
162};
163
Peng Fan438b52a2021-03-19 15:57:15 +0800164#ifdef CONFIG_IMX8MP
Peng Fanb11a7342018-01-10 13:20:20 +0800165struct fuse_bank0_regs {
166 u32 lock;
Peng Fan438b52a2021-03-19 15:57:15 +0800167 u32 rsvd0[7];
168 u32 uid_low;
169 u32 rsvd1[3];
170 u32 uid_high;
171 u32 rsvd2[3];
172};
173#else
174struct fuse_bank0_regs {
175 u32 lock;
Peng Fanb11a7342018-01-10 13:20:20 +0800176 u32 rsvd0[3];
177 u32 uid_low;
178 u32 rsvd1[3];
179 u32 uid_high;
180 u32 rsvd2[7];
181};
Peng Fan438b52a2021-03-19 15:57:15 +0800182#endif
Peng Fanb11a7342018-01-10 13:20:20 +0800183
184struct fuse_bank1_regs {
185 u32 tester3;
186 u32 rsvd0[3];
187 u32 tester4;
188 u32 rsvd1[3];
189 u32 tester5;
190 u32 rsvd2[3];
191 u32 cfg0;
192 u32 rsvd3[3];
193};
194
Peng Fan60767632020-05-03 22:19:56 +0800195struct fuse_bank3_regs {
196 u32 mem_trim0;
197 u32 rsvd0[3];
198 u32 mem_trim1;
199 u32 rsvd1[3];
200 u32 mem_trim2;
201 u32 rsvd2[3];
202 u32 ana0;
203 u32 rsvd3[3];
204};
205
206struct fuse_bank9_regs {
207 u32 mac_addr0;
208 u32 rsvd0[3];
209 u32 mac_addr1;
210 u32 rsvd1[11];
211};
212
213struct fuse_bank38_regs {
214 u32 ana_trim1; /* trim0 is at 0xD70, bank 37*/
215 u32 rsvd0[3];
216 u32 ana_trim2;
217 u32 rsvd1[3];
218 u32 ana_trim3;
219 u32 rsvd2[3];
220 u32 ana_trim4;
221 u32 rsvd3[3];
222};
223
224struct fuse_bank39_regs {
225 u32 ana_trim5;
226 u32 rsvd[15];
227};
228
Peng Fan2f8c5e12019-08-27 06:25:14 +0000229#ifdef CONFIG_IMX8MQ
Peng Fanb11a7342018-01-10 13:20:20 +0800230struct anamix_pll {
231 u32 audio_pll1_cfg0;
232 u32 audio_pll1_cfg1;
233 u32 audio_pll2_cfg0;
234 u32 audio_pll2_cfg1;
235 u32 video_pll_cfg0;
236 u32 video_pll_cfg1;
237 u32 gpu_pll_cfg0;
238 u32 gpu_pll_cfg1;
239 u32 vpu_pll_cfg0;
240 u32 vpu_pll_cfg1;
241 u32 arm_pll_cfg0;
242 u32 arm_pll_cfg1;
243 u32 sys_pll1_cfg0;
244 u32 sys_pll1_cfg1;
245 u32 sys_pll1_cfg2;
246 u32 sys_pll2_cfg0;
247 u32 sys_pll2_cfg1;
248 u32 sys_pll2_cfg2;
249 u32 sys_pll3_cfg0;
250 u32 sys_pll3_cfg1;
251 u32 sys_pll3_cfg2;
252 u32 video_pll2_cfg0;
253 u32 video_pll2_cfg1;
254 u32 video_pll2_cfg2;
255 u32 dram_pll_cfg0;
256 u32 dram_pll_cfg1;
257 u32 dram_pll_cfg2;
258 u32 digprog;
259 u32 osc_misc_cfg;
260 u32 pllout_monitor_cfg;
261 u32 frac_pllout_div_cfg;
262 u32 sscg_pllout_div_cfg;
263};
Peng Fan2f8c5e12019-08-27 06:25:14 +0000264#else
265struct anamix_pll {
266 u32 audio_pll1_gnrl_ctl;
267 u32 audio_pll1_fdiv_ctl0;
268 u32 audio_pll1_fdiv_ctl1;
269 u32 audio_pll1_sscg_ctl;
270 u32 audio_pll1_mnit_ctl;
271 u32 audio_pll2_gnrl_ctl;
272 u32 audio_pll2_fdiv_ctl0;
273 u32 audio_pll2_fdiv_ctl1;
274 u32 audio_pll2_sscg_ctl;
275 u32 audio_pll2_mnit_ctl;
276 u32 video_pll1_gnrl_ctl;
277 u32 video_pll1_fdiv_ctl0;
278 u32 video_pll1_fdiv_ctl1;
279 u32 video_pll1_sscg_ctl;
280 u32 video_pll1_mnit_ctl;
281 u32 reserved[5];
282 u32 dram_pll_gnrl_ctl;
283 u32 dram_pll_fdiv_ctl0;
284 u32 dram_pll_fdiv_ctl1;
285 u32 dram_pll_sscg_ctl;
286 u32 dram_pll_mnit_ctl;
287 u32 gpu_pll_gnrl_ctl;
288 u32 gpu_pll_div_ctl;
289 u32 gpu_pll_locked_ctl1;
290 u32 gpu_pll_mnit_ctl;
291 u32 vpu_pll_gnrl_ctl;
292 u32 vpu_pll_div_ctl;
293 u32 vpu_pll_locked_ctl1;
294 u32 vpu_pll_mnit_ctl;
295 u32 arm_pll_gnrl_ctl;
296 u32 arm_pll_div_ctl;
297 u32 arm_pll_locked_ctl1;
298 u32 arm_pll_mnit_ctl;
299 u32 sys_pll1_gnrl_ctl;
300 u32 sys_pll1_div_ctl;
301 u32 sys_pll1_locked_ctl1;
302 u32 reserved2[24];
303 u32 sys_pll1_mnit_ctl;
304 u32 sys_pll2_gnrl_ctl;
305 u32 sys_pll2_div_ctl;
306 u32 sys_pll2_locked_ctl1;
307 u32 sys_pll2_mnit_ctl;
308 u32 sys_pll3_gnrl_ctl;
309 u32 sys_pll3_div_ctl;
310 u32 sys_pll3_locked_ctl1;
311 u32 sys_pll3_mnit_ctl;
312 u32 anamix_misc_ctl;
313 u32 anamix_clk_mnit_ctl;
314 u32 reserved3[437];
315 u32 digprog;
316};
317#endif
Peng Fanb11a7342018-01-10 13:20:20 +0800318
Peng Fanb11a7342018-01-10 13:20:20 +0800319/* System Reset Controller (SRC) */
320struct src {
321 u32 scr;
322 u32 a53rcr;
323 u32 a53rcr1;
324 u32 m4rcr;
325 u32 reserved1[4];
326 u32 usbophy1_rcr;
327 u32 usbophy2_rcr;
328 u32 mipiphy_rcr;
329 u32 pciephy_rcr;
330 u32 hdmi_rcr;
331 u32 disp_rcr;
332 u32 reserved2[2];
333 u32 gpu_rcr;
334 u32 vpu_rcr;
335 u32 pcie2_rcr;
336 u32 mipiphy1_rcr;
337 u32 mipiphy2_rcr;
338 u32 reserved3;
339 u32 sbmr1;
340 u32 srsr;
341 u32 reserved4[2];
342 u32 sisr;
343 u32 simr;
344 u32 sbmr2;
345 u32 gpr1;
346 u32 gpr2;
347 u32 gpr3;
348 u32 gpr4;
349 u32 gpr5;
350 u32 gpr6;
351 u32 gpr7;
352 u32 gpr8;
353 u32 gpr9;
354 u32 gpr10;
355 u32 reserved5[985];
356 u32 ddr1_rcr;
357 u32 ddr2_rcr;
358};
359
Tommaso Merciai9c884162022-03-26 12:19:02 +0100360#define PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4)
361#define PWMCR_DOZEEN (1 << 24)
362#define PWMCR_WAITEN (1 << 23)
363#define PWMCR_DBGEN (1 << 22)
364#define PWMCR_CLKSRC_IPG_HIGH (2 << 16)
365#define PWMCR_CLKSRC_IPG (1 << 16)
366#define PWMCR_EN (1 << 0)
367
Tommaso Merciai28354e82022-03-26 12:19:03 +0100368struct pwm_regs {
369 u32 cr;
370 u32 sr;
371 u32 ir;
372 u32 sar;
373 u32 pr;
374 u32 cnr;
375};
376
Peng Fanb11a7342018-01-10 13:20:20 +0800377#define WDOG_WDT_MASK BIT(3)
378#define WDOG_WDZST_MASK BIT(0)
379struct wdog_regs {
380 u16 wcr; /* Control */
381 u16 wsr; /* Service */
382 u16 wrsr; /* Reset Status */
383 u16 wicr; /* Interrupt Control */
384 u16 wmcr; /* Miscellaneous Control */
385};
386
387struct bootrom_sw_info {
388 u8 reserved_1;
389 u8 boot_dev_instance;
390 u8 boot_dev_type;
391 u8 reserved_2;
392 u32 core_freq;
393 u32 axi_freq;
394 u32 ddr_freq;
395 u32 tick_freq;
396 u32 reserved_3[3];
397};
398
Peng Fan2f8c5e12019-08-27 06:25:14 +0000399#define ROM_SW_INFO_ADDR_B0 (IS_ENABLED(CONFIG_IMX8MQ) ? 0x00000968 :\
400 0x000009e8)
Peng Fanb11a7342018-01-10 13:20:20 +0800401#define ROM_SW_INFO_ADDR_A0 0x000009e8
402
403#define ROM_SW_INFO_ADDR is_soc_rev(CHIP_REV_1_0) ? \
404 (struct bootrom_sw_info **)ROM_SW_INFO_ADDR_A0 : \
405 (struct bootrom_sw_info **)ROM_SW_INFO_ADDR_B0
Peng Fan9cf2aa32020-07-09 13:52:41 +0800406
407struct gpc_reg {
408 u32 lpcr_bsc;
409 u32 lpcr_ad;
410 u32 lpcr_cpu1;
411 u32 lpcr_cpu2;
412 u32 lpcr_cpu3;
413 u32 slpcr;
414 u32 mst_cpu_mapping;
415 u32 mmdc_cpu_mapping;
416 u32 mlpcr;
417 u32 pgc_ack_sel;
418 u32 pgc_ack_sel_m4;
419 u32 gpc_misc;
420 u32 imr1_core0;
421 u32 imr2_core0;
422 u32 imr3_core0;
423 u32 imr4_core0;
424 u32 imr1_core1;
425 u32 imr2_core1;
426 u32 imr3_core1;
427 u32 imr4_core1;
428 u32 imr1_cpu1;
429 u32 imr2_cpu1;
430 u32 imr3_cpu1;
431 u32 imr4_cpu1;
432 u32 imr1_cpu3;
433 u32 imr2_cpu3;
434 u32 imr3_cpu3;
435 u32 imr4_cpu3;
436 u32 isr1_cpu0;
437 u32 isr2_cpu0;
438 u32 isr3_cpu0;
439 u32 isr4_cpu0;
440 u32 isr1_cpu1;
441 u32 isr2_cpu1;
442 u32 isr3_cpu1;
443 u32 isr4_cpu1;
444 u32 isr1_cpu2;
445 u32 isr2_cpu2;
446 u32 isr3_cpu2;
447 u32 isr4_cpu2;
448 u32 isr1_cpu3;
449 u32 isr2_cpu3;
450 u32 isr3_cpu3;
451 u32 isr4_cpu3;
452 u32 slt0_cfg;
453 u32 slt1_cfg;
454 u32 slt2_cfg;
455 u32 slt3_cfg;
456 u32 slt4_cfg;
457 u32 slt5_cfg;
458 u32 slt6_cfg;
459 u32 slt7_cfg;
460 u32 slt8_cfg;
461 u32 slt9_cfg;
462 u32 slt10_cfg;
463 u32 slt11_cfg;
464 u32 slt12_cfg;
465 u32 slt13_cfg;
466 u32 slt14_cfg;
467 u32 pgc_cpu_0_1_mapping;
468 u32 cpu_pgc_up_trg;
469 u32 mix_pgc_up_trg;
470 u32 pu_pgc_up_trg;
471 u32 cpu_pgc_dn_trg;
472 u32 mix_pgc_dn_trg;
473 u32 pu_pgc_dn_trg;
474 u32 lpcr_bsc2;
475 u32 pgc_cpu_2_3_mapping;
476 u32 lps_cpu0;
477 u32 lps_cpu1;
478 u32 lps_cpu2;
479 u32 lps_cpu3;
480 u32 gpc_gpr;
481 u32 gtor;
482 u32 debug_addr1;
483 u32 debug_addr2;
484 u32 cpu_pgc_up_status1;
485 u32 mix_pgc_up_status0;
486 u32 mix_pgc_up_status1;
487 u32 mix_pgc_up_status2;
488 u32 m4_mix_pgc_up_status0;
489 u32 m4_mix_pgc_up_status1;
490 u32 m4_mix_pgc_up_status2;
491 u32 pu_pgc_up_status0;
492 u32 pu_pgc_up_status1;
493 u32 pu_pgc_up_status2;
494 u32 m4_pu_pgc_up_status0;
495 u32 m4_pu_pgc_up_status1;
496 u32 m4_pu_pgc_up_status2;
497 u32 a53_lp_io_0;
498 u32 a53_lp_io_1;
499 u32 a53_lp_io_2;
500 u32 cpu_pgc_dn_status1;
501 u32 mix_pgc_dn_status0;
502 u32 mix_pgc_dn_status1;
503 u32 mix_pgc_dn_status2;
504 u32 m4_mix_pgc_dn_status0;
505 u32 m4_mix_pgc_dn_status1;
506 u32 m4_mix_pgc_dn_status2;
507 u32 pu_pgc_dn_status0;
508 u32 pu_pgc_dn_status1;
509 u32 pu_pgc_dn_status2;
510 u32 m4_pu_pgc_dn_status0;
511 u32 m4_pu_pgc_dn_status1;
512 u32 m4_pu_pgc_dn_status2;
513 u32 res[3];
514 u32 mix_pdn_flg;
515 u32 pu_pdn_flg;
516 u32 m4_mix_pdn_flg;
517 u32 m4_pu_pdn_flg;
518 u32 imr1_core2;
519 u32 imr2_core2;
520 u32 imr3_core2;
521 u32 imr4_core2;
522 u32 imr1_core3;
523 u32 imr2_core3;
524 u32 imr3_core3;
525 u32 imr4_core3;
526 u32 pgc_ack_sel_pu;
527 u32 pgc_ack_sel_m4_pu;
528 u32 slt15_cfg;
529 u32 slt16_cfg;
530 u32 slt17_cfg;
531 u32 slt18_cfg;
532 u32 slt19_cfg;
533 u32 gpc_pu_pwrhsk;
534 u32 slt0_cfg_pu;
535 u32 slt1_cfg_pu;
536 u32 slt2_cfg_pu;
537 u32 slt3_cfg_pu;
538 u32 slt4_cfg_pu;
539 u32 slt5_cfg_pu;
540 u32 slt6_cfg_pu;
541 u32 slt7_cfg_pu;
542 u32 slt8_cfg_pu;
543 u32 slt9_cfg_pu;
544 u32 slt10_cfg_pu;
545 u32 slt11_cfg_pu;
546 u32 slt12_cfg_pu;
547 u32 slt13_cfg_pu;
548 u32 slt14_cfg_pu;
549 u32 slt15_cfg_pu;
550 u32 slt16_cfg_pu;
551 u32 slt17_cfg_pu;
552 u32 slt18_cfg_pu;
553 u32 slt19_cfg_pu;
554};
555
556struct pgc_reg {
557 u32 pgcr;
558 u32 pgpupscr;
559 u32 pgpdnscr;
560 u32 pgsr;
561 u32 pgauxsw;
562 u32 pgdr;
563};
Peng Fanb11a7342018-01-10 13:20:20 +0800564#endif
565#endif