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git01.mediatek.com / filogic / uboot / 2e262c4d264234214dd8effae071205ddf8d2dc0 / . / configs / chromebit_mickey_defconfig
blob: 2a308eeaeb668b5703363ff17f9b9c9986940ea9 [file] [log] [blame]
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]1CONFIG_ARM=y
Urja Rannikko35bd7c62019-05-13 13:51:05 +0000[diff] [blame]2# CONFIG_SPL_USE_ARCH_MEMCPY is not set
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]3CONFIG_ARCH_ROCKCHIP=y
Tom Rini07edfae2018-02-03 12:10:38 -0500[diff] [blame]4CONFIG_SYS_TEXT_BASE=0x00100000
Tom Rini2e262c42020-08-10 15:31:07 -0400[diff] [blame^]5CONFIG_NR_DRAM_BANKS=1
Tom Rini47dece32020-04-28 16:15:47 -0400[diff] [blame]6CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
Tom Rini0332a1a2020-07-06 13:54:25 -0400[diff] [blame]7CONFIG_SPL_TEXT_BASE=0xff704000
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]8CONFIG_ROCKCHIP_RK3288=y
Tom Rini9834b902017-03-13 13:48:42 -0400[diff] [blame]9# CONFIG_SPL_MMC_SUPPORT is not set
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]10CONFIG_TARGET_CHROMEBIT_MICKEY=y
Tom Rinic9285bf2019-04-29 15:54:04 -0400[diff] [blame]11CONFIG_SPL_STACK_R_ADDR=0x80000
Tom Rinie0056d72018-06-04 11:57:37 -0400[diff] [blame]12CONFIG_DEBUG_UART_BASE=0xff690000
13CONFIG_DEBUG_UART_CLOCK=24000000
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]14CONFIG_SPL_SPI_FLASH_SUPPORT=y
15CONFIG_SPL_SPI_SUPPORT=y
Tom Rini47dece32020-04-28 16:15:47 -0400[diff] [blame]16CONFIG_SPL_PAYLOAD="u-boot.img"
Tom Rini90fa4e92020-07-06 15:46:38 -0400[diff] [blame]17CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-mickey"
Tom Rini84610272020-07-28 08:46:52 -0400[diff] [blame]18CONFIG_DEBUG_UART=y
Simon Glass4be229d2019-07-20 20:51:14 -0600[diff] [blame]19CONFIG_USE_PREBOOT=y
Klaus Goger2b6b4f22018-05-25 23:45:05 +0200[diff] [blame]20CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-mickey.dtb"
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]21# CONFIG_DISPLAY_CPUINFO is not set
Mario Sixf7055442018-03-28 14:38:17 +0200[diff] [blame]22CONFIG_DISPLAY_BOARDINFO_LATE=y
Urja Rannikkoe8c4c962020-05-13 19:15:21 +0000[diff] [blame]23CONFIG_BOARD_EARLY_INIT_R=y
Urja Rannikko35bd7c62019-05-13 13:51:05 +0000[diff] [blame]24# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]25CONFIG_SPL_STACK_R=y
26CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
Urja Rannikko35bd7c62019-05-13 13:51:05 +0000[diff] [blame]27# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
28# CONFIG_SPL_CRC32_SUPPORT is not set
Marek Vasute2542252018-04-07 16:05:27 +0200[diff] [blame]29CONFIG_SPL_SPI_LOAD=y
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]30CONFIG_CMD_GPIO=y
Patrick Delaunay73287092017-01-27 11:00:42 +0100[diff] [blame]31CONFIG_CMD_GPT=y
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]32CONFIG_CMD_I2C=y
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]33CONFIG_CMD_MMC=y
Simon Glass86b1b652017-08-04 16:34:46 -0600[diff] [blame]34CONFIG_CMD_SF_TEST=y
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]35CONFIG_CMD_SPI=y
Eddie Caib3501fe2017-12-15 08:17:13 +0800[diff] [blame]36CONFIG_CMD_USB=y
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]37# CONFIG_CMD_SETEXPR is not set
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]38CONFIG_CMD_CACHE=y
39CONFIG_CMD_TIME=y
40CONFIG_CMD_PMIC=y
41CONFIG_CMD_REGULATOR=y
Patrick Delaunayf7e07722017-01-27 11:00:37 +0100[diff] [blame]42# CONFIG_SPL_DOS_PARTITION is not set
Patrick Delaunay8a4f2bd2017-01-27 11:00:41 +0100[diff] [blame]43# CONFIG_SPL_EFI_PARTITION is not set
Patrick Delaunay73287092017-01-27 11:00:42 +0100[diff] [blame]44CONFIG_SPL_PARTITION_UUIDS=y
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]45CONFIG_SPL_OF_CONTROL=y
46CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
Urja Rannikko35bd7c62019-05-13 13:51:05 +0000[diff] [blame]47CONFIG_SPL_OF_PLATDATA=y
Tom Rinica63e712019-11-12 22:46:36 -0500[diff] [blame]48CONFIG_SYS_RELOC_GD_ENV_ADDR=y
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]49CONFIG_REGMAP=y
50CONFIG_SPL_REGMAP=y
51CONFIG_SYSCON=y
52CONFIG_SPL_SYSCON=y
53# CONFIG_SPL_SIMPLE_BUS is not set
Urja Rannikko35bd7c62019-05-13 13:51:05 +0000[diff] [blame]54# CONFIG_SPL_BLK is not set
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]55CONFIG_CLK=y
56CONFIG_SPL_CLK=y
57CONFIG_ROCKCHIP_GPIO=y
58CONFIG_I2C_CROS_EC_TUNNEL=y
59CONFIG_SYS_I2C_ROCKCHIP=y
60CONFIG_I2C_MUX=y
Masahiro Yamada74f09b82016-12-07 22:10:25 +0900[diff] [blame]61CONFIG_DM_KEYBOARD=y
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]62CONFIG_CROS_EC_KEYB=y
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]63CONFIG_CROS_EC=y
64CONFIG_CROS_EC_SPI=y
65CONFIG_PWRSEQ=y
Urja Rannikko35bd7c62019-05-13 13:51:05 +0000[diff] [blame]66# CONFIG_SPL_DM_MMC is not set
Masahiro Yamada7942e912017-01-10 13:32:04 +0900[diff] [blame]67CONFIG_MMC_DW=y
Masahiro Yamadadc607f82017-01-10 13:32:03 +0900[diff] [blame]68CONFIG_MMC_DW_ROCKCHIP=y
Miquel Raynal2e35dbb2019-10-03 19:50:05 +0200[diff] [blame]69CONFIG_MTD=y
Urja Rannikko35bd7c62019-05-13 13:51:05 +0000[diff] [blame]70CONFIG_SF_DEFAULT_BUS=2
Patrick Delaunay0df81042019-02-27 15:20:36 +0100[diff] [blame]71CONFIG_SF_DEFAULT_SPEED=20000000
Urja Rannikko7a19eec2019-05-13 13:51:03 +0000[diff] [blame]72CONFIG_SPI_FLASH_GIGADEVICE=y
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]73CONFIG_PINCTRL=y
Urja Rannikko35bd7c62019-05-13 13:51:05 +0000[diff] [blame]74CONFIG_PINCONF=y
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]75CONFIG_SPL_PINCTRL=y
Urja Rannikkoaa02ec02020-05-13 19:15:23 +0000[diff] [blame]76# CONFIG_SPL_PINCTRL_FULL is not set
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]77CONFIG_DM_PMIC=y
78# CONFIG_SPL_PMIC_CHILDREN is not set
Jacob Chen614704b2017-05-02 14:54:52 +0800[diff] [blame]79CONFIG_PMIC_RK8XX=y
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]80CONFIG_SPL_DM_REGULATOR=y
81CONFIG_DM_REGULATOR_FIXED=y
Jacob Chen614704b2017-05-02 14:54:52 +0800[diff] [blame]82CONFIG_REGULATOR_RK8XX=y
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]83CONFIG_PWM_ROCKCHIP=y
84CONFIG_RAM=y
85CONFIG_SPL_RAM=y
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]86CONFIG_DEBUG_UART_SHIFT=2
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]87CONFIG_ROCKCHIP_SPI=y
88CONFIG_SYSRESET=y
Tom Rini504997e2017-08-25 17:50:26 -0400[diff] [blame]89CONFIG_USB=y
Urja Rannikko35bd7c62019-05-13 13:51:05 +0000[diff] [blame]90# CONFIG_SPL_DM_USB is not set
91CONFIG_USB_DWC2=y
Adam Fordd4183d62018-01-02 10:39:52 -0600[diff] [blame]92CONFIG_ROCKCHIP_USB2_PHY=y
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]93CONFIG_DM_VIDEO=y
Anatolij Gustschindba36702020-02-04 22:43:06 +0100[diff] [blame]94# CONFIG_VIDEO_BPP8 is not set
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]95CONFIG_DISPLAY=y
96CONFIG_VIDEO_ROCKCHIP=y
eric.gao@rock-chips.com735ddea2017-04-17 22:24:23 +0800[diff] [blame]97CONFIG_DISPLAY_ROCKCHIP_HDMI=y
Urja Rannikko35bd7c62019-05-13 13:51:05 +0000[diff] [blame]98CONFIG_SPL_TINY_MEMSET=y
Simon Glassbf8d7bf2016-11-13 14:22:16 -0700[diff] [blame]99CONFIG_CMD_DHRYSTONE=y
100CONFIG_ERRNO_STR=y