| Simon Glass | ec3be54 | 2015-08-30 16:55:41 -0600 | [diff] [blame] | 1 | CONFIG_ARM=y |
| 2 | CONFIG_ARCH_ROCKCHIP=y |
| 3 | CONFIG_SYS_MALLOC_F_LEN=0x2000 |
| 4 | CONFIG_ROCKCHIP_RK3288=y |
| 5 | CONFIG_TARGET_FIREFLY_RK3288=y |
| Thomas Chou | 3a077cd | 2015-11-11 21:39:33 +0800 | [diff] [blame] | 6 | CONFIG_SPL_STACK_R_ADDR=0x80000 |
| Simon Glass | ec3be54 | 2015-08-30 16:55:41 -0600 | [diff] [blame] | 7 | CONFIG_DEFAULT_DEVICE_TREE="rk3288-firefly" |
| 8 | CONFIG_SPL_STACK_R=y |
| Simon Glass | 3b4057b | 2016-01-21 19:43:35 -0700 | [diff] [blame] | 9 | CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 |
| Simon Glass | ec3be54 | 2015-08-30 16:55:41 -0600 | [diff] [blame] | 10 | # CONFIG_CMD_IMLS is not set |
| 11 | # CONFIG_CMD_SETEXPR is not set |
| 12 | CONFIG_CMD_PMIC=y |
| 13 | CONFIG_CMD_REGULATOR=y |
| 14 | CONFIG_SPL_OF_CONTROL=y |
| Simon Glass | 8d32f4b | 2016-01-21 19:43:38 -0700 | [diff] [blame] | 15 | CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent" |
| Simon Glass | ec3be54 | 2015-08-30 16:55:41 -0600 | [diff] [blame] | 16 | CONFIG_REGMAP=y |
| huang lin | dd8515e | 2015-11-17 14:20:13 +0800 | [diff] [blame] | 17 | CONFIG_SPL_REGMAP=y |
| Simon Glass | ec3be54 | 2015-08-30 16:55:41 -0600 | [diff] [blame] | 18 | CONFIG_SYSCON=y |
| Simon Glass | 3b4057b | 2016-01-21 19:43:35 -0700 | [diff] [blame] | 19 | CONFIG_SPL_SYSCON=y |
| Simon Glass | 70bad91 | 2016-01-21 19:43:49 -0700 | [diff] [blame] | 20 | # CONFIG_SPL_SIMPLE_BUS is not set |
| Bin Meng | 63c1098 | 2015-09-28 05:14:15 -0700 | [diff] [blame] | 21 | CONFIG_CLK=y |
| 22 | CONFIG_SPL_CLK=y |
| 23 | CONFIG_ROCKCHIP_GPIO=y |
| 24 | CONFIG_SYS_I2C_ROCKCHIP=y |
| Simon Glass | ec3be54 | 2015-08-30 16:55:41 -0600 | [diff] [blame] | 25 | CONFIG_LED=y |
| Simon Glass | ec3be54 | 2015-08-30 16:55:41 -0600 | [diff] [blame] | 26 | CONFIG_LED_GPIO=y |
| Bin Meng | 63c1098 | 2015-09-28 05:14:15 -0700 | [diff] [blame] | 27 | CONFIG_RESET=y |
| 28 | CONFIG_DM_MMC=y |
| 29 | CONFIG_ROCKCHIP_DWMMC=y |
| Simon Glass | ec3be54 | 2015-08-30 16:55:41 -0600 | [diff] [blame] | 30 | CONFIG_PINCTRL=y |
| Bin Meng | 63c1098 | 2015-09-28 05:14:15 -0700 | [diff] [blame] | 31 | CONFIG_SPL_PINCTRL=y |
| Simon Glass | ec3be54 | 2015-08-30 16:55:41 -0600 | [diff] [blame] | 32 | # CONFIG_SPL_PINCTRL_FULL is not set |
| 33 | CONFIG_ROCKCHIP_PINCTRL=y |
| Simon Glass | ec3be54 | 2015-08-30 16:55:41 -0600 | [diff] [blame] | 34 | CONFIG_DM_PMIC=y |
| Simon Glass | 52de646 | 2016-01-21 19:45:20 -0700 | [diff] [blame] | 35 | # CONFIG_SPL_PMIC_CHILDREN is not set |
| Simon Glass | ec3be54 | 2015-08-30 16:55:41 -0600 | [diff] [blame] | 36 | CONFIG_PMIC_ACT8846=y |
| 37 | CONFIG_DM_REGULATOR=y |
| 38 | CONFIG_REGULATOR_ACT8846=y |
| Simon Glass | c08ebf6 | 2016-02-22 22:55:40 -0700 | [diff] [blame] | 39 | CONFIG_DM_REGULATOR_FIXED=y |
| Simon Glass | 52de646 | 2016-01-21 19:45:20 -0700 | [diff] [blame] | 40 | CONFIG_DM_PWM=y |
| 41 | CONFIG_PWM_ROCKCHIP=y |
| Simon Glass | ec3be54 | 2015-08-30 16:55:41 -0600 | [diff] [blame] | 42 | CONFIG_RAM=y |
| 43 | CONFIG_SPL_RAM=y |
| Bin Meng | 63c1098 | 2015-09-28 05:14:15 -0700 | [diff] [blame] | 44 | CONFIG_DEBUG_UART=y |
| 45 | CONFIG_DEBUG_UART_BASE=0xff690000 |
| 46 | CONFIG_DEBUG_UART_CLOCK=24000000 |
| 47 | CONFIG_DEBUG_UART_SHIFT=2 |
| Thomas Chou | a6cec01 | 2015-11-19 21:48:14 +0800 | [diff] [blame] | 48 | CONFIG_SYS_NS16550=y |
| Simon Glass | 52de646 | 2016-01-21 19:45:20 -0700 | [diff] [blame] | 49 | CONFIG_DM_VIDEO=y |
| Anatolij Gustschin | 4601eb4 | 2016-01-25 17:17:22 +0100 | [diff] [blame] | 50 | CONFIG_DISPLAY=y |
| Simon Glass | 52de646 | 2016-01-21 19:45:20 -0700 | [diff] [blame] | 51 | CONFIG_VIDEO_ROCKCHIP=y |
| Simon Glass | ec3be54 | 2015-08-30 16:55:41 -0600 | [diff] [blame] | 52 | CONFIG_USE_PRIVATE_LIBGCC=y |
| Sjoerd Simons | f26619a | 2015-12-04 23:27:41 +0100 | [diff] [blame] | 53 | CONFIG_USE_TINY_PRINTF=y |
| Simon Glass | ec3be54 | 2015-08-30 16:55:41 -0600 | [diff] [blame] | 54 | CONFIG_CMD_DHRYSTONE=y |
| 55 | CONFIG_ERRNO_STR=y |