| Marek Vasut | 2e8edf5 | 2013-04-25 10:16:03 +0000 | [diff] [blame] | 1 | /* |
| 2 | * DENX M53 DRAM init values |
| 3 | * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de> |
| 4 | * |
| Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
| Marek Vasut | 2e8edf5 | 2013-04-25 10:16:03 +0000 | [diff] [blame] | 6 | * |
| 7 | * Refer docs/README.imxmage for more details about how-to configure |
| 8 | * and create imximage boot image |
| 9 | * |
| 10 | * The syntax is taken as close as possible with the kwbimage |
| 11 | */ |
| 12 | #include <asm/imx-common/imximage.cfg> |
| 13 | |
| 14 | /* image version */ |
| 15 | IMAGE_VERSION 2 |
| 16 | |
| 17 | |
| 18 | /* Boot Offset 0x400, valid for both SD and NAND boot. */ |
| 19 | BOOT_OFFSET FLASH_OFFSET_STANDARD |
| 20 | |
| 21 | /* |
| 22 | * Device Configuration Data (DCD) |
| 23 | * |
| 24 | * Each entry must have the format: |
| 25 | * Addr-type Address Value |
| 26 | * |
| 27 | * where: |
| 28 | * Addr-type register length (1,2 or 4 bytes) |
| 29 | * Address absolute address of the register |
| 30 | * value value to be stored in the register |
| 31 | */ |
| 32 | DATA 4 0x53fa86f4 0x00000000 /* GRP_DDRMODE_CTL */ |
| 33 | DATA 4 0x53fa8714 0x00000000 /* GRP_DDRMODE */ |
| 34 | DATA 4 0x53fa86fc 0x00000000 /* GRP_DDRPKE */ |
| 35 | DATA 4 0x53fa8724 0x04000000 /* GRP_DDR_TYPE */ |
| 36 | |
| 37 | DATA 4 0x53fa872c 0x00300000 /* GRP_B3DS */ |
| 38 | DATA 4 0x53fa8554 0x00300000 /* DRAM_DQM3 */ |
| 39 | DATA 4 0x53fa8558 0x00300040 /* DRAM_SDQS3 */ |
| 40 | |
| 41 | DATA 4 0x53fa8728 0x00300000 /* GRP_B2DS */ |
| 42 | DATA 4 0x53fa8560 0x00300000 /* DRAM_DQM2 */ |
| 43 | DATA 4 0x53fa8568 0x00300040 /* DRAM_SDQS2 */ |
| 44 | |
| 45 | DATA 4 0x53fa871c 0x00300000 /* GRP_B1DS */ |
| 46 | DATA 4 0x53fa8594 0x00300000 /* DRAM_DQM1 */ |
| 47 | DATA 4 0x53fa8590 0x00300040 /* DRAM_SDQS1 */ |
| 48 | |
| 49 | DATA 4 0x53fa8718 0x00300000 /* GRP_B0DS */ |
| 50 | DATA 4 0x53fa8584 0x00300000 /* DRAM_DQM0 */ |
| 51 | DATA 4 0x53fa857c 0x00300040 /* DRAM_SDQS0 */ |
| 52 | |
| 53 | DATA 4 0x53fa8578 0x00300000 /* DRAM_SDCLK_0 */ |
| 54 | DATA 4 0x53fa8570 0x00300000 /* DRAM_SDCLK_1 */ |
| 55 | |
| 56 | DATA 4 0x53fa8574 0x00300000 /* DRAM_CAS */ |
| 57 | DATA 4 0x53fa8588 0x00300000 /* DRAM_RAS */ |
| 58 | DATA 4 0x53fa86f0 0x00300000 /* GRP_ADDDS */ |
| 59 | DATA 4 0x53fa8720 0x00300000 /* GRP_CTLDS */ |
| 60 | |
| 61 | DATA 4 0x53fa8564 0x00300040 /* DRAM_SDODT1 */ |
| 62 | DATA 4 0x53fa8580 0x00300040 /* DRAM_SDODT0 */ |
| 63 | |
| 64 | /* ESDCTL */ |
| 65 | DATA 4 0x63fd9088 0x32383535 |
| 66 | DATA 4 0x63fd9090 0x40383538 |
| 67 | DATA 4 0x63fd907c 0x0136014d |
| 68 | DATA 4 0x63fd9080 0x01510141 |
| 69 | |
| 70 | DATA 4 0x63fd9018 0x00011740 |
| 71 | DATA 4 0x63fd9000 0xc3190000 |
| 72 | DATA 4 0x63fd900c 0x555952e3 |
| 73 | DATA 4 0x63fd9010 0xb68e8b63 |
| 74 | DATA 4 0x63fd9014 0x01ff00db |
| 75 | DATA 4 0x63fd902c 0x000026d2 |
| 76 | DATA 4 0x63fd9030 0x009f0e21 |
| 77 | DATA 4 0x63fd9008 0x12273030 |
| 78 | DATA 4 0x63fd9004 0x0002002d |
| 79 | DATA 4 0x63fd901c 0x00008032 |
| 80 | DATA 4 0x63fd901c 0x00008033 |
| 81 | DATA 4 0x63fd901c 0x00028031 |
| 82 | DATA 4 0x63fd901c 0x092080b0 |
| 83 | DATA 4 0x63fd901c 0x04008040 |
| 84 | DATA 4 0x63fd901c 0x0000803a |
| 85 | DATA 4 0x63fd901c 0x0000803b |
| 86 | DATA 4 0x63fd901c 0x00028039 |
| 87 | DATA 4 0x63fd901c 0x09208138 |
| 88 | DATA 4 0x63fd901c 0x04008048 |
| 89 | DATA 4 0x63fd9020 0x00001800 |
| 90 | DATA 4 0x63fd9040 0x04b80003 |
| 91 | DATA 4 0x63fd9058 0x00022227 |
| 92 | DATA 4 0x63fd901c 0x00000000 |